Tài liệu Ambit BuildGates Synthesis User Guide ppt

Ambit BuildGates Synthesis User Guide
Product Version 4.0.8
May 2001
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Ambit BuildGates Synthesis User Guide
May 2001 iii Product Version 4.0.8
Preface 9
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Other Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
About the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Using Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Using Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1
Introduction to Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . 13
Separately Licensed Software Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Low Power Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Physically Knowledgeable Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Datapath Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC_Shell / DC_Shell Equivalencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Invoking Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Getting Help for Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Exiting Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Files Used in Ambit BuildGates Synthesis Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Key Bindings and Mouse Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3
Using the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Main Menu Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
File Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Edit Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Contents

Ambit BuildGates Synthesis User Guide
May 2001 iv Product Version 4.0.8
View Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Commands Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Reports Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Window Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Help Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
The Main Tool Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
The Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
The Module Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
The Variable Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Work Area Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
HDL and Tcl Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Constraints Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
The Schematic Viewer and Symbol Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Distributed Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
The ac_shell Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
The Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4
Flow Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Read the Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Read the Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Build a Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Set Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Optimize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Generate Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Save Final Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5

Viewing the Schematic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
How to Use the Schematic Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Mouse Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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May 2001 v Product Version 4.0.8
Objects in the Schematic Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Accessing Context-Sensitive Pop-Up Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Highlighting Path Between Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Viewing Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
The Schematic Tool Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
The Module Title Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Searching for an Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Grouping Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Dissolving Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Creating a Unique Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Displaying Logic Cones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Extracting Logic Cones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Displaying Port Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Printing a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6
Setting Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Units in Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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May 2001 vi Product Version 4.0.8
7
Optimizing Before Place-and-Route. . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Running do_optimize Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Top-Down Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Bottom-Up Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Deriving Constraints from Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Time Budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Preserving Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Uniquifying Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Collapsing Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Incremental Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Applying Timing Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
8
Optimizing with Logic Transforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Introduction to Transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Logic Optimization Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Optimizing Generic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Mapping and Unmapping of Generic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Constraint-Driven Optimizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Summary Listing of Transform Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9
Optimizing After Place-and-Route. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Backannotating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
A Script Showing the Backannotation of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Reading SDF Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Ambit BuildGates Synthesis User Guide
May 2001 vii Product Version 4.0.8
Optimizing to Correct Late and Early Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10
Report Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Report Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Area Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Sample Area Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Library Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Hierarchy Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Sample Hierarchy Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Design Rule Violations Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Sample Design Rule Violations Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
VHDL Library Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Sample VHDL Library Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
End Point Slack and Path Histogram Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Fanin and Fanout Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Sample Fanin Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Finite State Machine Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Sample FSM Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Customizing Report Column Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
A
Using Tcl within ac_shell and pks_shell . . . . . . . . . . . . . . . . . . . . . . 189
The Tcl Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Tcl Variables and Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
find Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
get_names Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Abbreviating Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Searching for Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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May 2001 viii Product Version 4.0.8
Accessing Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Returning Unix Command Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
B
Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Ambit BuildGates Synthesis User Guide
May 2001 9 Product Version 4.0.8
Preface
This preface contains the following sections:
■ About This Manual on page 9
■ Other Information Sources on page 9
■ Syntax Conventions on page 10
■ About the Graphical User Interface on page 11
About This Manual
This manual describes the Ambit
®
BuildGates
®
synthesis software. BuildGates synthesis can
be run both in command line mode and in graphical user interface (GUI) mode. See
Getting
Started on page 27 for an explanation on how to use both modes.
Other Information Sources
For more information about Ambit BuildGates synthesis and other related products, you can
consult the sources listed here.
■
Command Reference for Ambit BuildGates Synthesis and Cadence PKS
■
Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS
■
Test Synthesis for Ambit BuildGates Synthesis and Cadence PKS

■
HDL Modeling for Ambit BuildGates Synthesis
■
Distributed Processing of Ambit BuildGates Synthesis
■
Synthesis Place-and-Route (SP&R) Flow Guide
■
Constraint Translator for Ambit BuildGates Synthesis and Cadence PKS
Depending on the product licenses your site has purchased, you could also have these
documents.
■
PKS User Guide
Ambit BuildGates Synthesis User Guide
Preface
May 2001 10 Product Version 4.0.8
■
Datapath Option of Ambit BuildGates Synthesis and Cadence PKS
■
Low Power Option of Ambit BuildGates Synthesis and Cadence PKS
BuildGates synthesis is often used with other Cadence
®
tools during various design flows.
The following documents provide information about these tools and flows. Availability of these
documents depends on the product licenses your site has purchased.
■
Cadence Timing Library Format Reference
■
Cadence Pearl Timing Analyzer User Guide
■
Cadence General Constraint Format Reference

The following books are helpful references.
■ IEEE 1364 Verilog HDL LRM
■ TCL Reference,
Tcl and the Tk Toolkit
, John K. Ousterhout, Addison-Wesley
Publishing Company
Syntax Conventions
This section provides the Text Command Syntax used in this document.
Text Command Syntax
The list below describes the syntax conventions used for the Ambit BuildGates synthesis text
interface commands.
Important
Command names and arguments are case sensitive. User-defined information is
case sensitive for Verilog designs and, depending on the value specified for the
global variable
hdl_vhdl_case, may be case sensitive as well.
literal Nonitalic words indicate keywords that you must enter literally.
These keywords represent command or option names.
argument
Words in italics indicate user-defined arguments or information
for which you must substitute a name or a value.
| Vertical bars (OR-bars) separate possible choices for a single
argument.
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Preface
May 2001 11 Product Version 4.0.8
[ ] Brackets denote optional arguments. When used with OR-bars,
they enclose a list of choices from which you can choose one.
{ } Braces are used to indicate that a choice is required from the list
of arguments separated by OR-bars. You must choose one from

the list.
{ argument1 | argument2 | argument3 }
{ } Bold braces are used in Tcl commands to indicate that the
braces must be typed in literally.
Three dots ( ) indicate that you can repeat the previous
argument. If the three dots are used with brackets (that is,
[argument] ), you can specify zero or more arguments. If
the three dots are used without brackets (argument ),you
must specify at least one argument, but can specify more.
# The pound sign precedes comments in command files.
About the Graphical User Interface
This section describes the conventions used for the BuildGates synthesis graphical user
interface (GUI) commands and describes how to use the menus and forms in the BuildGates
synthesis software.
Using Menus
The GUI commands are located on menus at the top of the window. They can take one of
three forms.
CommandName
A command name with no dots or arrow executes immediately.
CommandName
… A command name with three dots displays a form for choosing
options.
CommandName
-> A command name with a right arrow displays an additional menu
with more commands. Multiple layers of menus and commands
are presented in what are called command sequences, for
example:
File – Import – LEF
. In this example, you go to the File
menu, then the Import submenu, and, finally, the LEF command.

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Preface
May 2001 12 Product Version 4.0.8
Using Forms
… A menu button that contains only three dots provides browsing
capability. When you select the browse button, a list of choices
appears.
Ok The
Ok
button executes the command and closes the form.
Cancel The
Cancel
button cancels the command and closes the form.
Defaults The
Defaults
button displays default values for options on the
form.
Apply The
Apply
button executes the command but does not close the
form.
Help The
Help
button provides information about the command.
Ambit BuildGates Synthesis User Guide
May 2001 13 Product Version 4.0.8
1
Introduction to Ambit BuildGates
Synthesis
This chapter provides a description of the Ambit

®
BuildGates
®
synthesis software, including
brief descriptions of the three software options that are offered. This chapter also provides a
comparison table of dc_shell and
ac_shell command equivalents.
Capable of running in both command line mode and in graphical user interface (GUI) mode,
the BuildGates synthesis tool delivers dramatic performance and productivity benefits over
conventional synthesis tools. The key features of the Ambit BuildGates synthesis tool are
described in the following paragraphs.
At the heart of the Ambit BuildGates synthesis tool is a signoff-quality, fast, full-chip timing
engine that enables high-capacity and high-performance chip-level synthesis. Fast and
flexible, BuildGates synthesis supports a wide variety of design styles such as multiple clocks,
including both edge triggered and level sensitive with cycle stealing.
BuildGates synthesis has a high capacity database that allows synthesis of more of the
design at once. Its fast runtime assures rapid turnaround, making chip-level synthesis
practical. In addition, high-capacity enables productivity gains by eliminating the need for
excessive resources and time required for elaborate bottom-up script development.
BuildGates synthesis also offers automatic time budgeting, integration with physical design
tools, VHDL and Verilog support, support of both reads and writes of netlist EDIF 2.0, Tcl
command line interface for shell level control, transforms for performing focused
optimizations, schematic and textual report capabilities, and integrated DFT analysis and
scan insertion.
Separately Licensed Software Products
Cadence
®
low power synthesis, Cadence physically knowledgeable synthesis (PKS), and
Cadence datapath synthesis option are companion products to the basic Ambit BuildGates
synthesis software and require separate licenses. For details on these products, please

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Introduction to Ambit BuildGates Synthesis
May 2001 14 Product Version 4.0.8
contact your Cadence marketing representative. If you are a licensed user, the appropriate
software and documentation are included in your installation package.
Low Power Synthesis
The low power module provides both power analysis and power optimization capabilities.
Power analysis estimates the power consuming modules in your design at the gate-level
through each phase of the design cycle until you have met your power specifications. The
power optimizer synthesizes a minimum power netlist that meets your specified timing
constraints, optimizing design power consumption at the register-transfer level (RTL).
Licensed users can refer to the
Low Power Option of Ambit BuildGates Synthesis and
Cadence PKS
for details.
Physically Knowledgeable Synthesis
Cadence physically knowledgeable synthesis (PKS) performs placement-driven timing by
adding a physical model of the netlist to the timing and interconnect models that currently
exist in the Ambit BuildGates synthesis tool. The physical model allows for timing estimations
to take place during the optimization process, virtually eliminating the need for third-party
placement tools.
Placement information is read into PKS using a PDEF file, which includes the
x,y
location
of every cell. PKS uses highly accurate Steiner routes to estimate interconnect, resulting in
closer correlation between the timing in BuildGates synthesis and the timing that results after
running a place-and-route tool.
Licensed users can refer to the
PKS User Guide
for details.

Datapath Synthesis
The Cadence datapath synthesis option product performs complex arithmetic operations that
manipulate data in the RTL (in Verilog or VHDL format) to aid in the development of
sophisticated, high-performance ASICs. Arithmetic components such as adders, subtractors,
multipliers, comparators, and shifters are used to define the mathematical properties of the
design.
Licensed users can refer to the
Datapath Option of Ambit BuildGates Synthesis and
Cadence PKS
for details.
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Introduction to Ambit BuildGates Synthesis
May 2001 15 Product Version 4.0.8
AC_Shell / DC_Shell Equivalencies
The table below shows the dc_shell commands and their ac_shell equivalents.
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 1 of 11)
dc_shell ac_shell
alias alias
all_clocks find -ports -clocks
all_connected get_info
all_designs find -module *
all_inputs find -ports -input
all_inputs_not_clock find -ports -no_clocks
all_outputs find -ports -output
allocate_budget do_time_budget
all_registers find -instance -registers
analyze read_verilog, read_vhdl
balance_buffer Not needed
balance_registers No equivalent
break break

catch (Tcl command) catch (Tcl command)
cd cd
change_link do_rebind
change_names do_change_names
characterize do_derive_context
check_design check_netlist or check_timing
check_timing check_timing
compare_design No equivalent
compare_fsm No equivalent
compile do_optimize
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May 2001 16 Product Version 4.0.8
compile -incremental do_xform_optimize_slack
compile_fix_multiple_port_
net
do_xform_fix_multiport_nets
set_global fix_multiport_nets
compile -map_effort high do_optimize -effort high
compile -only_design_rules do_xform_fix_design_rule_violations
connect_net Contact your Cadence AE for set of equivalents.
continue continue
copy_design do_copy_module
create_bus Contact your Cadence AE for set of equivalents.
create_cell Contact your Cadence AE for set of equivalents.
create_clock set_clock
create_clock
clksourcelist
set_clock_root
create_design Contact your Cadence AE for set of equivalents.

create_net Contact your Cadence AE for set of equivalents.
create_port Contact your Cadence AE for set of equivalents.
current_design set_top_timing_module
set_current_module
current_instance set_current_instance
define_design_lib set_vhdl_library
define_name_rules set_global dcn_{ bus | inst | module
| net | port |}
derive_clocks Tcl script
derive_timing_constraints No equivalent
disconnect_net delete_object
drive_of get_cell_drive
echo puts
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 2 of 11)
dc_shell ac_shell
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May 2001 17 Product Version 4.0.8
elaborate do_build_generic
exit exit
extract Verilog source code pragmas
filter get_info
find find
find (cell, name) find -instance
find (lib_cell, name) find -cellref
find (library, name) find -techlib
find (net, name) find -net
find (pin, name) find -pin
find (port, name) find -port
for for

foreach foreach
get_attribute get_info
get_cells find -instance
get_lib_cells find -cellref
get_libs find -techlib
get_nets find -net
get_pins find -pin
get_ports find -port
get_unix_variable $env(name)
group create_hierarchy or do_extract
group_path Not needed
group_variable Not needed
help help
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 3 of 11)
dc_shell ac_shell
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May 2001 18 Product Version 4.0.8
history history
if if
include source
link do_link
do_build_generic
list list
list_designs get_names […]
list_instances get_names [find -techlib]
list_libs No equivalent
load_of get_cell_pin_load
minimize_fsm Verilog source code pragmas
propagate_constraints No equivalent

pwd pwd
quit quit
read_db read_adb
read_edif read_edif
read -f db read_adb
read -f vhdl read_vhdl
read_verilog read_verilog
do_build_generic
read_lib read_alf
read_sdf read_sdf
read_timing read_sdf
read_vhdl read_vhdl
reduce_fsm Verilog source code pragmas
regexp (Built-in Tcl command) regexp (Built-in Tcl command)
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 4 of 11)
dc_shell ac_shell
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May 2001 19 Product Version 4.0.8
remove_attribute remove_assertions
remove_bus delete_object [find -bus
name
]
remove_cache Not needed
remove_cell delete_object [find -cell
name
]
remove_clock remove_assertions
remove_constraint remove_assertions
remove_design do_remove_design

remove_input_delay remove_assertions
remove_net delete_object [find -net
name
]
remove_output_delay remove_assertions
remove_pads delete_object [find -instance
name
]
remove_port delete_object [find -port
name
]
remove_unconnected_ports No equivalent
remove_variable No equivalent
rename_design do_change_name
reoptimize_design do_xform_optimize_slack
replace_synthetic No equivalent
report_area report_area
report_annotated_check report_annotations
report_attribute get_info
report_bus No equivalent
report_cache Not needed
report_cell report_area -cell
report_clock report_clocks
report_compile_options No equivalent
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 5 of 11)
dc_shell ac_shell
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report_constraint report_timing or

report_design_rule_violations
report_delay_calculation report_cell_instance_timing
report_design No equivalent
report_fsm report_fsm
report_hierarchy report_hierarchy
report_lib report_library
report_multicycles No equivalent
report_name_rules get_global dcn_{ bus | inst | module
| net | port |}
report_names No equivalent
report_net report_net
report_path_group Not needed
report_port report_ports
report_reference report_area
report_resource_estimates No equivalent
report_resources No equivalent
report_routability No equivalent
report_synlib No equivalent
report_timing report_timing
report_timing_requirements No equivalent
report_transitive_fanin report_fanin
report_transitive_fanout report_fanout
report_wire_load report_area -summary
reset_compare_design_script No equivalent
reset_design No equivalent
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 6 of 11)
dc_shell ac_shell
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reset_path No equivalent
set_annotated_check read_sdf
set_annotated_delay read_sdf
set_attribute set_attribute
set_balance_registers No equivalent
set_boundary_optimization set_port_property (for constant propagation
only)
set_case_analysis set_constant_for_timing
set_clock_gating_check set_global clock_gating_to_be_
checked
set_clock_latency set_clock_insertion_delay
set_clock_skew set_clock_insertion_delay
set_clock_uncertainty
set_clock_skew -ideal |
propagated
set_clock_propagation -ideal |
propagated
set_clock_transition set_slew_time -clock
clockname
-pos | neg
set_clock_uncertainty set_clock_uncertainty
set_compare_design_script No equivalent
set_critical_range do_optimize -critical_ratio or
do_optimize -critical_offset
set_disable_timing set_disable_timing or
set_disable_cell_timing
set_dont_touch
instance
set_dont_modify [find -inst
instance

]
set_dont_touch
module
set_dont_modify [find -module
module
]
set_dont_touch
net
set_dont_modify [ find -net
net
]
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 7 of 11)
dc_shell ac_shell
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set_dont_touch set_cell_property dont_modify true
set_dont_touch_network set_dont_modify -network -hier
set_dont_use set_cell_property dont_utilize true
set_drive set_drive_resistance
set_driving_cell set_drive_cell
set_equal No equivalent
set_false_path set_false_path
set_fanout_load set_fanout_load
set_fix_hold do_timing_correction -fix_hold or
do_xform_fix_hold
set_flatten do_optimize -flatten on
set_fsm_encoding Verilog source code pragmas, VHDL attributes
and pragmas
set_fsm_encoding_style Verilog source code pragmas, VHDL attributes

and pragmas
set_fsm_minimize Verilog source code pragmas, VHDL attributes
and pragmas
set_fsm_order Verilog source code pragmas, VHDL attributes
and pragmas
set_fsm_preserve_state Verilog source code pragmas, VHDL attributes
and pragmas
set_fsm_state_vector Verilog source code pragmas, VHDL attributes
and pragmas
set_impl_priority No equivalent
set_implementation set_global acl_default_arch
set_input_delay set_input_delay
set_input_transition set_slew_time
set_load set_port_capacitance
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 8 of 11)
dc_shell ac_shell
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set_load -pin_load set_port_capacitance
set_load -fanout_number set_num_external_sinks
set_local_link_library Not needed
set_logic_one set_logic1
set_logic_zero set_logic0
set_map_only No equivalent
set_max_area No equivalent
set_max_capacitance set_global capacitance_limit
set_port_capacitance_limit
set_max_delay set_path_delay -late
set_max_fanout set_global fanout_load_limit

set_fanout_load_limit
set_max_time_borrow No equivalent
set_max_transition set_global slew_time_limit
set_slew_time_limit
set_min_capacitance No equivalent
set_min_delay set_path_delay -early
set_min_fanout No equivalent
set_min_porosity No equivalent
set_min_transition No equivalent
set_minimize_tree_delay No equivalent
set_model_drive Not needed
set_model_load Not needed
set_model_map_effort Not needed
set_model_scale Not needed
set_multicycle_path N -setup set_cycle_addition N-1 -late
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 9 of 11)
dc_shell ac_shell
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set_multicycle_path N -hold set_cycle_addition N -early
set_operating_conditions set_operating_conditions
set_opposite No equivalent
set_output_delay set_external_delay
set_port_fanout_number set_num_external_sinks
set_prefer Not needed
set_propagated_clock set_clock_propagation propagated
set_register_type Not needed
set_resistance set_wire_resistance
set_resource_allocation No equivalent

set_resource_implementation No equivalent
set_share_cse No equivalent
set_structure no do_xform_propagate_constants
do_xform_map -hierarchical
do_optimize
set_timing_disable_internal_
inout_cell_paths
set_global bidi_io_arc
set_timing_ranges Not needed
set_true_delay_case_analysis No equivalent
set_unconnected set_unconnected
set_ungroup do_dissolve_hierarchy
set_unix_variable No equivalent
set_wire_load set_wire_load
set_wire_load_mode set_wire_load_mode
set_wire_load_model set_wire_load
wireload
set_wire_load -port_list set_port_wire_load
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 10 of 11)
dc_shell ac_shell
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set_wire_load_selection_
group
set_wire_load_selection_table
simplify_constants do_xform_propagate_constants
sh exec
syntax_check No equivalent
target_library = set_global target_technology

techlib
translate No equivalent
unalias unalias
ungroup do_dissolve_hierarchy
uniquify do_uniquely_instantiate
update_lib read_library_update
update_script Not needed
update_timing Not needed
while while
write -f verilog write_verilog
write -f db write_adb
write_compare_design_script No equivalent
write_lib libcompile
libname.lib libname.alf
(Unix command)
write_script write_assertions
write_constraints write_constraints
write_timing write_sdf
write -f vhdl write_vhdl
Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 11 of 11)
dc_shell ac_shell