Circuit design with HDL Chapter 4 Structural modeling pdf

CHAPTER 4: STRUCTURAL MODELING


Lecturer: Ho Ngoc Diem
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NATIONAL UNIVERSITY OF HO CHI MINH CITY
UNIVERSITY OF INFORMATION TECHNOLOGY
FACULTY OF COMPUTER ENGINEERING
Agenda
 Chapter 1: Introduction
 Chapter 2: Modules and hierarchical structure
 Chapter 3: Fundamental concepts
 Chapter 4: Structural modeling (Gate & Switch-level modeling)
 Chapter 5: Dataflow modeling (Expression)
 Chapter 6: Behavioral modeling
 Chapter 7: Tasks and Functions
 Chapter 8: State machines
 Chapter 9: Testbench and verification
 Chapter 10: VHDL introduction

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Content
Chapter 4:
A – Overview
 What is structural modeling
 Primitive gates
 Switches
 User-defined primitives
B – Examples
 Combinational Circuit
 Sequential Circuit

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A – Overview
Primitive Gates, Switches, User-defined primitives
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Verilog model for hardware design
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Verilog design
Gate/Switch level modeling Behavioral modeling Dataflow modeling
- Primitive switch, gate
- User defined primitive
-Continuous assignment
(assign)
- Expression (operators)
 There are different ways of modeling a hardware design. Choose an
appropriate model to design Combinational or Sequential Circuit.
 Some books do not classify Dataflow modeling as a separate modeling
type.

RTL Design
- Procedural assignment
- initial, always block
- Conditional statement…
Structural model
 When Verilog was first developed (1984) most logic simulators
operated on netlists
 Netlist: a list of gates and show how they are connected
together

 A natural representation of a digital logic circuit
 Not the most convenient approach to express the test benches
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Structural model
 Structural
- Explicit structure of the circuit
- How a module is composed as an interconnection of more primitive
modules or components
- E.g. Each logic gate initially instantiated and connected to others
 In Verilog, a structural model consists of:
- List of connected components
- Like schematics, but using text: netlist
- Boring when write, and hard to decode
- Essential without integrated design tools
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Structural model
 Structural Models are built from gate primitives,
switches, and other modules
 Describe the logic circuit using logic gates
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 12 primitive logic gates predefined in the Verilog HDL






 Advantanges:
 Gates provide a much closer one-to-one mapping
between the actual circuit and the model.

There is no continuous assignment equivalent to the
bidirectional transfer gate.

Primitive gates
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And/Or/Nand/Nor/Xor/Xnor
One scalar output
Multiple scalar inputs
The first terminal in the list of
gate terminals is an output and
the other terminals are inputs
wire OUT, IN1, IN2; // basic gate instantiations.
and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);
xor x1(OUT, IN1, IN2);
xnor nx1(OUT, IN1, IN2);
// More than two inputs; 3 input nand gate
nand na1_3inp(OUT, IN1, IN2, IN3);
// gate instantiation without instance name
and (OUT, IN1, IN2); // legal gate instantiation
Verilog automatically instantiates
the appropriate gate.
Terminal list
Primitive gates
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Buf/Not Gates
One scalar input
One or more scalar outputs

The last terminal in the port list
is connected to the input
// basic gate instantiations.
buf b1(OUT1, IN);
not n1(OUT1, IN);
// More than two outputs
buf b1_2out(OUT1, OUT2, IN);
// gate instantiation without instance name
not (OUT1, IN); // legal gate instantiation
Primitive gates
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Bufif/notif
Gates with an additional control signal on buf and not gates
bufif1 b1 (out, in, ctrl); bufif0 b0 (out, in, ctrl); notif1 n1 (out, in, ctrl); notif0 n0 (out, in, ctrl);
Primitive gates
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Propagate only if control signal is asserted.
Propagate z if their control signal is de-asserted
 Array of Instances
wire [7:0] OUT, IN1, IN2;
nand n_gate[7:0](OUT, IN1, IN2);
// This is equivalent to the following 8 instantiations
nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);

The instances differ from each other only
by the index of the vector to which they
are connected
Primitive gates
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 Example: Gate-level multiplexer
4-to-1 Multiplexer
// Module 4-to-1 multiplexer.
// Port list is taken exactly from the I/Odiagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
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Primitive gates
 Example: Gate-level multiplexer
// Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;
// Gate instantiations
// Create s1n and s0n signals.
not (s1n, s1);
not (s0n, s0);
// 3-input and gates instantiated
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
// 4-input or gate instantiated

or (out, y0, y1, y2, y3);
endmodule
Logic Diagram for 4-to-1 Multiplexer
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Primitive gates
Switches
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 There are two kinds of switch:
* MOS switches :
cmos, nmos, pmos, rcmos, rnmos, rpmos
* Bidirectional pass switches:
tran, rtran, tranif1, rtranif1, tranif0, rtranif0

 Advantages:

- Gates provide a much closer one-to-one mapping between the
actual circuit and the model.
- There is no continuous assignment equivalent to the
bidirectional transfer gate.

MOS switches: nmos, pmos, rnoms, rpmos
Unidirectional channel for data, similar to bufif gate


CONTROL
when “off”
nmos
rnmos
nmos
when “on”

rnmos
when “on”
R
R
pmos
rpmos
pmos
when “on”
rpmos
when “on”
R
CONTROL
DATA
DATA
Ex: pmos p1 (out, data, control)
Ex: nmos n1 (out, data, control)
Switches
R
when “off”
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MOS Switches: cmos, rcmos
R
R
cmos
when on
rcmos
when on
cmos (out, in, n_control, p_control)
in
out

p_control
n_control
Switches
when “off”
cmos
rcmos
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Switches
 tranif0, tranif1, rtranif0, rtranif1: block signal when turn off,
pass signal when turn on

 tran, rtran: always pass signal

 Terminals be scalar nets or bit-select of vector nets


Ex: tranif0 (inout1, inout2, control)
Ex: tran (inout1, inout2)
Bidirectional pass switches
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R
R
tran rtran
R
R
tranif0 rtranif0
R
R
tranif1 rtranif1

tranif0 , rtranif0
tranif1, rtranif1
tran, rtran
inout1
inout2
inout1
inout2
inout1
inout2
control
control
Switches
Bidirectional pass switches
Switches
 Ref “Verilog digital system design”, Zainalabedin Navabi for
design examples at switch level
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Strength modeling
 Allows specification of drive strength for primitive gate outputs
and nets.
 Gate output or net signal strength values are specified in a set of
parenthesis that include a strength value for logic 0 and one for
logic 1.
 Drive strengths for logic 0 (strength0):
supply0, strong0, pull0, weak0, highz0
 Drive strengths for logic 1 (strength1):
supply1, strong1, pull1, weak1, highz1
 Charge strengths, representing the strength of a capacitive net:
large, medium, small

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Drive strength values of primitive gate outputs
Strength modeling
Ex:
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Strength values of nets

Strength modeling
Strength0
Strength1
Drive strength
Charge strength
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The stronger signal shall dominate all the
weaker drivers and determine the result.
Strength level
Strength modeling
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