Bản vẽ mạch điện full máy tính dell inspriron 1415 e4b5a compal LA
Bạn đang xem bản rút gọn của tài liệu. Xem và tải ngay bản đầy đủ của tài liệu tại đây (1.59 MB, 56 trang )
5
4
3
2
1
PROJECT :ZAVA1/ZAVC1
PCB NO : DA60018A000 LA-B016P-R1.0
D
B
F
D
_
C
@
4
2
0
1
D
C
S
K
Schematic Document
r
fo
Intel Shark Bay ULT
UMA / DIS AMD 25W/S3+DDR3x4
B
t
n
e
d
i
f
n
o
C
A
l
ia
2014-10-20
B
Rev: 1.0
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2018/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Cover Page
Document Number
Rev
1.0
LA-B016P
Friday, October 24, 2014
Sheet
1
1
of
56
5
4
3
2
1
D
128M*16 32bit
VRAM
DDR 3 *2
PEG 2.0 x4
1
5
~
7
4
e
g
a
P
Memory Bus (DDR3L)
3
5
~
2
5
e
g
a
P
VRAM 128M*16 32bit
DDR 3 *2
AMD 25W
S3-64 23x23
Dual Channel
8
1
,
7
1
e
g
a
P
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.35V DDR3L 1600 MHz
DDI
USB 3.0
0
2
e
g
a
P
Intel
Broadwell ULT-U
Processor
BGA 1168
Port 1
USB2.0
Port 2
Port 1
C
Port 2
PCI-E
Port 0
Touch Screen
Card Reader
RTS5170
Port 5
Port 6
C
USB 2.0 Conn. 3
B
Digital Mic.
Headphone Jack /
Mic. Jack combo
2
2
e
g
a
P
Audio Codec
ALC3234
LPC Bus
I2C
33MHz
ENE KBC
KB9012
PS/2
Touch Pad
7
2
e
g
a
P
Int.KBD
0
3
e
g
a
P
A
Digital Camera
(With Digital MIC)
USB 3.0 Conn. 2
Int. Speaker R / L
9
e
g
a
P
8MB
Port 7
HD Audio
SPI
7
2
e
g
a
P
e
d
i
f
n
o
C
NGFF 2230
WiFi/WiGi/BT4.0
USB 3.0 Conn. 1
4
1
~
4
e
g
a
P
t
n
SPI ROM
l
ia
SATA3.0
SATA Rediver
B
r
fo
Port 4
5
2
e
g
a
P
1
2
e
g
a
P
2
3
e
g
a
P
SATA HDD Conn.
S
K
Ethernet
RTL8106E
6
2
e
g
a
P
NGFF 2230
WiFi/WiGi
/BT4.0
1
3
e
g
a
P
Port 3
1
3
e
g
a
P
x1
Port 6
6
2
e
g
a
P
x1
@
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2018/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
4
2
e
g
a
P
B
F
D
_
Port 0
4
2
e
g
a
P
HDMI Conn.
8GB Max
4
2
e
g
a
P
eDP
1
3
e
g
a
P
eDP Conn.
DDRIII-DIMM X2
4
2
0
1
D
3
2
Block Diagram
Document Number
Rev
1.0
LA-B016P
Friday, October 24, 2014
Sheet
1
2
of
56
5
D
4
3
2
1
Compal Confidential
Project: ZAVA1/ZAVC1
File Name : LA-B016P
B
F
D
_
C
USB
FFC
16 pin
CardReader Slot
CardReader/B
B
t
n
FFC
e
d
i
f
n
o
C
A
8 pin
l
ia
r
fo
@
RJ45
S
K
HDMI
USB
USB
Audio Jack
B
M/B
LED/B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
2018/03/31
Deciphered Date
Title
Date:
4
D
C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2
0
1
3
2
MB & DB Ass'y
Document Number
Rev
1.0
LA-B016P
Friday, October 24, 2014
Sheet
1
3
of
56
5
4
3
2
1
Board ID Table for AD channel
Vcc
Ra
Board ID
D
C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
3.3V +/- 1%
100K +/- 1%
Rb
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
NC
V AD_BID typ
0.000V
0.354V
0.430V
0.550V
0.702V
0.819V
0.992V
1.185V
1.414V
1.650V
1.865V
2.031V
2.200V
2.329V
2.408V
2.533V
2.677V
2.800V
2.912V
3.300V
V AD_BID min
0.000V
0.347V
0.423V
0.541V
0.691V
0.807V
0.978V
1.169V
1.398V
1.634V
1.849V
2.015V
2.185V
2.316V
2.395V
2.521V
2.667V
2.791V
2.905V
3.000V
V AD_BID max
0.300V
0.360V
0.438V
0.559V
0.713V
0.831V
1.006V
1.200V
1.430V
1.667V
1.881V
2.046V
2.215V
2.343V
2.421V
2.544V
2.687V
2.808V
2.919V
3.300V
EC
0x00
0x0C
0x1D
0x27
0x31
0x3C
0x47
0x55
0x65
0x77
0x88
0x97
0xA4
0xAE
0xB8
0xC1
0xCA
0xD4
0xDD
0xE7
AD3
- 0x0B
- 0x1C
- 0x26
- 0x30
- 0x3B
- 0x46
- 0x54
- 0x64
- 0x76
- 0x87
- 0x96
- 0xA3
- 0xAD
- 0xB7
- 0xC0
- 0xC9
- 0xD3
- 0xDC
- 0xE6
- 0xFF
USB3.0
EC_SMB_CK1
EC_SMB_DA1
KB9012
EC_SMB_CK2
EC_SMB_DA2
KB9012
SMBCLK
SMBDATA
ULT
SML0CLK
SML0DATA
ULT
SML1CLK
SML1DATA
ULT
BATT
V
Charger
VGA
DIMM
XDP
Thermal Sensor
FFS
V
V
V
V V
V
t
n
e
d
i
f
n
o
C
Symbol Note :
l
ia
: means Digital Ground
: means Analog Ground
A
Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
B
F
D
_
DIS(JET) DIS(Topaz)
UMA
Pre-SSI
Pre-SSI
Pre-SSI
SSI
SSI
SSI
PT
PT
PT
ST
ST
ST
1.0
1.0
1.0
S
K
r
fo
Link
B
Port2
USB connector 2
Port4
SMBUS Control Table
SOURCE
USB connector 1
Port3
BDW 3D BOARD ID Table
ULT
@
USB connector 1
Port1
USB connector 2
Port2
USB connector 3 (D/B)
Port3
C
Port4
MINI Card (WLAN)
Port5
Touch Screen Panel
Port6
Card Reader
Port7
Camera
PCI EXPRESS
Lane 1
Lane 2
Lane 3
10/100 LAN
Lane 4
MINI Card (WLAN)
Lane 5
PEG (AMD JET/TOBAZ)
B
CLOCK SIGNAL
Lane 6
CLKOUT_PCIE0
SATA
CLKOUT_PCIE1
SATA0
CLKOUT_PCIE2
10/100 LAN
CLKOUT_PCIE3
MINI Card (WLAN)
CLKOUT_PCIE4
dGPU
HDD
SATA1
SATA2
SATA3
A
CLKOUT_PCIE5
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
2018/03/31
Deciphered Date
Title
Date:
4
D
USB2.0
Port0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2
0
1
Port1
3
2
Notes
Document Number
Rev
1.0
LA-B016P
Friday, October 24, 2014
Sheet
1
4
of
56
5
4
3
2.2K
SMBUS Address [0x9a]
2.2K
D
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
2
1
10K
+3.3V_ALW_PCH
+3VS
10K
N-MOS
N-MOS
DDR_XDP_WLAN_TP_SMBCLK
202
DDR_XDP_WLAN_TP_SMBDAT
200
DIMM1
1K
202
+3.3V_ALW_PCH
1K
BDW
AN1
SML0CLK
AK1
SML0DATA
200
0 ohm
0 ohm
2.2K
2.2K
AN1
SML1_SMBCLK
AK1
SML1_SMBDATA
N-MOS
EC_SMB_CK2
2.2K
79
EC_SMB_CK2
80
EC_SMB_DA2
+3VALW
2.2K
KBC
KB9012A4
B
77
EC_SMB_CK1
78
EC_SMB_DA1
t
n
e
d
i
f
n
o
C
A
51
S
K
r
fo
XDP1
@
4
2
0
1
SMBUS Address [A4]
SMBUS Address [TBD]
C
2.2K
+3VS_VGA
2.2K
N-MOS
N-MOS
VGA_SMB_CK2
T4
VGA_SMB_DA2
T3
UV28
GPU
SMBUS Address [0xXX]
+3VALW
l
ia
2.2K
53
DDR_XDP_SMBDAT_R1
B
F
D
_
EC_SMB_DA2
2.2K
C
DDR_XDP_SMBCLK_R1
+3.3V_ALW_PCH
N-MOS
DIMM2
0 ohm
0 ohm
SCL
11
SDA
10
100 ohm
3
100 ohm
1
PU701
PD1
POWER
Charger
SMBUS Address [0x12]
4
BAT_ALERT
3
6
BATT_PRS
5
PBATT
B
BATT SMBUS Address [0x16]
CONN
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2018/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
D
SMBUS Address [A0]
3
2
SMBUS connection
Document Number
Rev
1.0
LA-B016P
Friday, October 24, 2014
Sheet
1
5
of
56
5
4
3
2
1
i3-4020U-15W-GT2-MP
UC1
D
I3R1@
UC1
I3R3@
CL8064701552800 QEZ5 D0 1.8G
CL8064701478202 SR16Q C1 1.7G A31!
SA00007MG0L
SA00006SX2L TBD
<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>
i5-4210U-15W-GT2-MP
UC1
I5R1@
UC1
I5R3@
CL8064701477802 QEAK D0 1.7G
CL8064701477702 SR170 C1 1.6G A31!
SA00007LO0L
SA00006SM3L TBD
UC1
C54
C55
B58
C58
B55
A55
A57
B57
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
i7-4510U-15W-GT2-MP
UC1
UC1
Broadwell
I7R3@
UC1
CL8064701477301 QEAF D0 2G BGA
CL8064701477202 SR16Z C1 1.8G A31!
SA00007M70L
SA00006SL2L TBD
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
C51
C50
C53
B54
C49
B50
A53
B53
QG21@
CL8065801674128 QG21 C0 1.2G
I7R1@
HASWELL_MCP_E
UC1A
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
EDP_TX0#
EDP_TX0
EDP_TX1#
EDP_TX1
COMPENSATION PU FOR eDP
A45
B45
D20
A43
EDP_AUX#
EDP_AUX
UC1
2
EDP_BIA_PWM
QG22@
SA00007OT0L
B
F
D
_
SYS_RESET#
SYS_RESET#
1
2
1
2
H_CATERR#
49.9_0402_1%
H_PROCHOT#
62_0402_5%
H_CPUPWRGD
HASWELL_MCP_E
1
UC1B
RC66
10K_0402_5%
1
CC27
100P_0402_50V8J
@EMI@
<30>
H_CATERR#
PECI_EC
PECI_EC
D61
K61
N62
PROC_DETECT
CATERR
PECI
MISC
2
2
r
fo
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
JTAG
ESD solution
<30,34>
B
@
CL8064701614813 QFSY C0 1.6G CL8065801675027 QG22 C0 1.2G
C
RC60
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115
H_PROCHOT#
1
RC67
2
H_PROCHOT#_R
56_0402_5%
K63
H_CPUPWRGD
C61
H_PROCHOT#
1
DDR3 COMPENSATION SIGNALS
200_0402_1%
2
1 RC68
SM_RCOMP0
120_0402_1%
2
1 RC69
SM_RCOMP1
100_0402_1%
2
1 RC70
SM_RCOMP2
2
@EMI@
CC42
22P_0402_50V8J
<17>
e
d
i
f
n
o
C
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
DDR3_DRAMRST#_CPU
1
CC35
@ESD@
0.047U_0402_16V4Z
PROCPWRGD
t
n
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3_DRAMRST#_CPU
<17>
DDR_PG_CTRL
AU60
AV60
AU61
AV15
AV61
l
ia
PROCHOT
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
@
THERMAL
PWR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DDR3
RC71
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
Rev1p2
1 OF 19
+1.05VS_PCH
1
24.9_0402_1%~D
<10,31>
@
RC72
0_0402_5%
@
SA00007AM0L
@ RC58
+VCCIOA_OUT
<31>
<31>
2
EDP_COMP
EDP_DISP_UTIL 1
S
K
J62
K62
E60
E61
E59
F63
F62
XDP_TCK
XDP_TMS
@
XDP_TRST#
XDP_TDI
@
XDP_TDO
J60
H60
H61
H62
K59
H63
K60
J61
XDP_OBS0_R
XDP_OBS1_R
@
@
@
@
@
@
4
2
0
1
D
C47
C46
A49
B49
SA00007OS0L
QFSY@
<31>
<31>
<31>
<31>
SYS_RESET#
2
1
C
<10>
+3VS
RC362
1K_0402_1%
1
2
CC17
0.1U_0402_10V7K
+1.05VS_PCH
T123
1
R3
T122
2 PCH_JTAG_RST#
0_0402_5%
PCH_JTAG_RST#
<8>
XDP_TDO
XDP_TCK
XDP_TRST#
RC141
1
@
2 0_0402_1%
T111
T112
T113
T114
T115
T116
1
2
3
4
8
7
6
5
B
RP45
51_8P4R_5%
PU/PD for JTAG signals
Rev1p2
2 OF 19
2
Place CC35
on BOT
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
MCP(1,2/19) eDP,XDP,MISC
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
6
of
56
5
4
3
2
1
Interleaved Memory
AP33
AR32
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
AY34
AW34
AU34
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
AU35
AV35
AY41
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
B
Rev1p2
t
n
1
e
d
i
f
n
o
C
RC14
1.82K_0402_1%
2
+SM_VREF_CA
1
1
2
RC17
2.2_0402_1%
2
1
2
<17>
DDR_B_DQS#[0..1]
<18>
DDR_A_DQS#[2..3]
<17>
DDR_B_DQS#[2..3]
<18>
DDR_A_DQS[0..1]
<17>
DDR_B_DQS[0..1]
<18>
DDR_A_DQS[2..3]
<17>
r
fo
<18>
DDR_B_D[48..63]
SB_CS#0
SB_CS#1
@
DDR CHANNEL B
AY49
AU50
AW49
AV50
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AM32
AK32
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AM35
AK35
AM33
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
AL35
AM36
AU49
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
<18>
<18>
<18>
<18>
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<18>
<18>
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<18>
<18>
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
<18>
<18>
<18>
DDR_B_BS0
<18>
DDR_B_BS1
<18>
DDR_B_BS2
<18>
DDR_B_MA[0..15]
<18>
C
DDR_A_DQS#4
DDR_A_DQS#5
DDR_B_DQS#4
DDR_B_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_B_DQS#6
DDR_B_DQS#7
DDR_A_DQS#[4..5]
<17>
DDR_B_DQS#[4..5]
<18>
DDR_A_DQS#[6..7]
<17>
DDR_B_DQS#[6..7]
DDR_A_DQS4
DDR_A_DQS5
DDR_B_DQS4
DDR_B_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_B_DQS6
DDR_B_DQS7
<18>
DDR_A_DQS[4..5]
<17>
DDR_B_DQS[4..5]
<18>
DDR_A_DQS[6..7]
<17>
DDR_B_DQS[6..7]
<18>
Rev1p2
@
+1.35V
+1.35V
RC15
1.82K_0402_1%
+SM_VREF_DQ1
1
+SM_VREF_DQ0_DIMM1
RC16
1.82K_0402_1%
2
1
1
RC18
2.2_0402_1%
RC21
1.82K_0402_1%
2
CC9
0.022U_0402_16V7K
1
RC19
2.2_0402_1%
RC22
1.82K_0402_1%
change 22nF
RC24
24.9_0402_1%~D
+SM_VREF_DQ0
2
2
CC10
0.022U_0402_16V7K
change 22nF
RC25
24.9_0402_1%~D
2
2
confirm by intel request PDG P141
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
Date:
4
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
B
4 OF 19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
D
AL32
SB_ODT0
B
F
D
_
DDR_A_D[48..63]
S
K
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
change 22nF
RC23
24.9_0402_1%~D
DDR_A_DQS#[0..1]
DDR_B_DQS[2..3]
1
RC20
1.82K_0402_1%
A
DDR_A_DQS0
DDR_A_DQS1
DDR_B_DQS0
DDR_B_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_B_DQS2
DDR_B_DQS3
DDR_B_D[32..47]
<17>
<18>
l
ia
CC8
0.022U_0402_16V7K
<18>
<17>
DDR_A_DQS#0
DDR_A_DQS#1
DDR_B_DQS#0
DDR_B_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_B_DQS#2
DDR_B_DQS#3
+SM_VREF_DQ1_DIMM2
<17>
<17>
<17>
DDR_A_BS0
<17>
DDR_A_BS1
<17>
DDR_A_BS2
<17>
DDR_A_MA[0..15]
AP49
AR51
AP51
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
+SM_VREF_CA_DIMM
<17>
<17>
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
+1.35V
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
2
SA_BA0
SA_BA1
SA_BA2
@
<17>
<17>
4
2
0
1
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
AM38
AN38
AK38
AL38
1
SA_RAS
SA_WE
SA_CAS
3 OF 19
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP32
SA_ODT0
DDR CHANNEL A
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
1
SA_CS#0
SA_CS#1
AU43
AW43
AY42
AY43
<17>
<17>
<17>
<17>
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
2
DDR_B_D[16..31]
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
1
<18>
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
2
DDR_A_D[16..31]
C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AU37
AV37
AW36
AY36
1
DDR_B_D[0..15]
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
HASWELL_MCP_E
UC1D
DDR_A_D[32..47]
1
<17>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
2
<18>
DDR_A_D[0..15]
1
<17>
<17>
HASWELL_MCP_E
2
UC1C
D
3
2
MCP(3,4/19) DDR3
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
7
of
56
5
4
3
2
1
1
+RTCVCC
RTC Battery
RC1
330K_0402_1%
PCH_INTVRMEN
2
1
1
+3VS
2
2
+CHGRTC
2
3
RC2
330K_0402_1%
JP12
1
1
+3VLP
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
1
For GCLK
<19>
CC26
1U_0603_10V6K
PCH_RTCX1
PCH_RTCX1
CC1 XTAL@
1
2
1M_0402_5%
1
1
RC5
RC6
2
2
20K_0402_5%
20K_0402_5%
2
1
1
1
2
<22>
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
1
RC8
ME_EN
2
PCH_AZ_SDOUT
1K_0402_5%
CMOS place near DIMM
<6>
PCH_JTAG_RST#
T175
@
SRTCRST#
PCH_RTCRST#
6
@
D
G
2
3
G
5
RTC_DIS
D
<30>
1
S
@
DMN66D0LDW-7_SOT363-6
QC2B
t
n
S
1
4
DMN66D0LDW-7_SOT363-6
QC2A
CMOS_CLR1
RC368
100K_0402_5%
@
l
ia
2
e
d
i
f
n
o
C
Shunt
Open
ME_CLR1
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
S
K
r
fo
PCH_JTAG_RST#
PCH_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
RTC discharge by EC
B
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
CC3
1U_0402_6.3V6K
PCH_AZ_CODEC_SDIN0
<30>
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
2
@
CMOS1 SHORT PADS~D
1
2
1U_0402_6.3V6K
CC4
AW5
AY5
AU6
AV7
AV6
AU7
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD
AUDIO
SATA
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
JTAG
J5
H5
B15
A15
Shunt
Clear ME RTC Registers
Open
Keep ME RTC Registers
<32>
<32>
<32>
<32>
SATA HDD
C
J6
H6
B14
C15
PCH Rx side need use strap pin to update PCIE +/+3VS
F5
E5
C17
D17
RC107
10K_0402_5%
V1
U1
V6
AC1
EC_SMI#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
A12
L11
K10
C12
U3
SATA_IREF
RC126
1
SATA_RCOMP
SATA_ACT#
RC131
1
EC_SMI#
<30>
+1.05VS_ASATA3PLL
ODD_DETECT#
SATA_ACT#
@
2 0_0603_1%
2 3.01K_0402_1%
<25>
within 500 mils
SATA Impedance Compensation
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
reference FFRD sch 0.5
Rev1p2
5 OF 19
B
@
+3VS
HDA for Codec
Clear CMOS
TPM setting
SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C
SATA_PTX_DRX_N0_C
SATA_PTX_DRX_P0_C
J8
H8
A17
B17
CMOS setting
Keep CMOS
@
2
+RTCVCC
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
2
RC7
HASWELL_MCP_E
UC1E
1
CC2 XTAL@
15P_0402_50V8J
1
2
1
B
F
D
_
1
XTAL@
RC4
10M_0402_5%
YC1
32.768KHZ_12.5PF_Q13FC1350000
2
2
XTAL@
PCH_AZ_SDOUT
1K_0402_5%
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
PCH_RTCX1
1
15P_0402_50V8J
D
FLASH DESCRIPTOR SECURITY OVERRIDE
2
C
2
@ RC3
JUMP_43X39
+RTCVCC
W=20mils
1
JUMP_43X39
W=20mils
DC1
BAT54CW_SOT323-3
1
1
@
W=20mils
2
1
2
JP14
2
+RTCVCC
RC10
1K_0402_5%
+CHGRTC
4
2
0
1
2
+RTCBATT
D
<22>
PCH_AZ_CODEC_SDOUT
<22>
PCH_AZ_CODEC_SYNC
<22>
<22>
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_BITCLK
EMI@ R2356
1
2 33_0402_5% PCH_AZ_SDOUT
EMI@ R2357
1
2 33_0402_5% PCH_AZ_SYNC
EMI@ R2358
1
2 33_0402_5% PCH_AZ_RST#
EMI@ R2359
1
2 33_0402_5% PCH_AZ_BITCLK
ODD_DETECT#
PCH_GPIO35
PCH_GPIO37
1
2
3
4
8
7
6
5
RP37
10K_8P4R_5%
1 @EMI@
CC5
27P_0402_50V8J
2
+1.05VS_PCH
1
2
3
4
8
7
6
5
EMI depop location
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
RP48
51_8P4R_5%
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
MCP(5/19) RTC,SATA,HDA,JTAG
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
8
of
56
5
4
3
2
1
DE7
2
RB751V-40_SOD323-2
2
RC370
@
PCH_GPIO60
1
1
FW_UPDATE
0_0402_5%
FW_UPDATE
<30,46>
4
2
0
1
MEM Bus : DDR/XDP/WLAN/TP
+3VALW_PCH
+3VS
1
1
2
3
4
8
7
6
5
PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP#
PCH_SPI_HOLD#
C-LINK
R2334 1
R2335 1
2 1K_0402_1%
2 1K_0402_1%
2
4
@
QC1A
DMN66D0LDW-7_SOT363-6
B
F
D
_
Rev1p2
7 OF 19
3
MEM_SMBDATA
T97
T98
T99
15_8P4R_5%
+3VALW_PCH
2
2
@
@
@
1
QC1B
DMN66D0LDW-7_SOT363-6
5
AF2
AD2
AF4
2
2
SPI
CL_CLK
CL_DATA
CL_RST
6
MEM_SMBCLK
S
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_WP1#
PCH_SPI_HOLD1#
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
G
RP39
2
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_HOT#
SML1_SMBCLK
SML1_SMBDATA
@
D
R2332
10K_0402_5%
S
PCH_SPI_CLK
PCH_SPI_CS0#
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
D
EMI@
R2333
2 15_0402_1%
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SMBUS
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
LPC
D
@EMI@
C2326
68P_0402_50V8J
1
1
LAD0
LAD1
LAD2
LAD3
LFRAME
R2331
10K_0402_5%
G
EMI
PCH_SPI_CLK_R
AU14
AW12
AY12
AW11
AV12
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
+3VS
HASWELL_MCP_E
UC1G
<30>
LPC_LAD0
<30>
LPC_LAD1
<30>
LPC_LAD2
<30>
LPC_LAD3
<30>
LPC_LFRAME#
R2330
10K_0402_5%
1
R2329
10K_0402_5%
1
1
D
DDR_XDP_WLAN_TP_SMBCLK
<17,18,32>
DDR_XDP_WLAN_TP_SMBDAT
<17,18,32>
SML1 Bus : EC/Sensors
U2302
+3VALW_PCH
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
8
7
6
5
PCH_SPI_HOLD1#
PCH_SPI_CLK_R
PCH_SPI_MOSI_1
S
K
2.2K_0804_8P4R_5%
64M EN25Q64-104HIP SOP 8P
RP49
r
fo
SML0CLK
SML0DATA
@
1
2
3
4
8
7
6
5
QH1B
1
SML1_SMBCLK
6
EC_SMB_CK2
<30,33,48>
EC_SMB_DA2
<30,33,48>
5
8
7
6
5
DMN66D0LDW-7_SOT363-6
G
U2302
1
2
3
4
1
2
3
4
4
SML1_SMBDATA
3
D
RP40
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
S
SPI ROM ( 8MByte )
RC373
2
D
10K_0402_5%
1
PCH_GPIO60
C2327
0.1U_0402_10V7K
1
2
G
+3VALW_PCH
SA000039A30
2
WINBOND
64M W25Q64FVSSIQ SOIC 8P
PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_WP1#
C
+3VALW_PCH
S
C
QH1A
DMN66D0LDW-7_SOT363-6
For GCLK
1K_0804_8P4R_5%
e
d
i
f
n
o
C
10/100 LAN ------->
<21>
<21>
<21>
WLAN(Mini Card)--->
<26>
<26>
<47>
<47>
<48>
dGPU--->
@ R2452
1
CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
CLK_PEG_VGA#
CLK_PEG_VGA
PEG_CLKREQ#
2
1
3
S
WLAN_CLKREQ#
D
<26>
WLAN_CLKREQ#_R
2
G
Q2409
B41
A41
Y5
C41
B42
AD1
B38
C37
N1
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#_R
A39
B39
U5
CLK_PEG_VGA#
CLK_PEG_VGA
B37
A37
T2
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLOCK
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
XTAL24_IN
XTAL24_OUT
K21
M21
C26
CLK_BIASREF
C35
C34
AK8
AL8
AN15
AP15
SWAP_1
SWAP_2
3
4
XTAL@
CC7
15P_0402_50V8J
2
1
RC13
XTAL@
3.01K_0402_1%
2
+1.05VS_AXCK_LCPLL
RP41 10K_8P4R_5%
1
8
SWAP_2
2
7
SWAP_1
3
6
4
5
1
CLKOUT_LPC0
2
R2336
1 EMI@
22_0402_5%
CLK_PCI_LPC
<30>
B35
A35
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
6 OF 19
+3VS_WLAN_NGFF +3VS
Rev1p2
@
RP42
1
2
3
4
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
A25
B25
B
XTAL@
YC2
24MHZ_12PF_X3G024000DC1H
1
2
2
HASWELL_MCP_E
UC1F
1
3.3P_0402_50V8C
8
7
6
5
A
10K_8P4R_5%
1
+3VS
C43
C42
U2
CLK_PCIE_LAN#
CLK_PCIE_LAN
0_0402_5%~D
DII-DMN65D8LW-7~D
A
CC6
2
1
t
n
l
ia
XTAL24_IN
XTAL24_IN
RC12
1M_0402_5%
B
<19>
R2453
100K_0402_5%~D
2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
MCP(6,7/19) CLK,SMB,SPI,LPC
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
9
of
56
5
4
3
2
1
PCH_PLTRST#
CC33
+3VALW_PCH
2
ME_SUS_PWR_ACK
10K_0402_5%
2 SUSACK#
10K_0402_5%
2 SUS_STAT#/LPCPD#
10K_0402_5%
@ RC28
1
@ RC29
1
PCH_PLTRST#
+3V_DSW
2
2
RC32
1
RC31
1
RC34
1
RC39
2
RC33
2
PCH_RSMRST#_R
0_0402_5%
2
SUSACK#
0_0402_5%
@
ME_SUS_PWR_ACK_R 1
RC35
@
4
OUT
PLT_RST#
PLT_RST#
UC3
MC74VHC1G08DFT2G_SC70-5
D
<21,26,30,47>
R159
100K_0402_5%
@
DSWODVREN - On Die DSW VR Enable
H：Enable(DEFAULT)
L：Disable
Note: SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit
CAN be NC ,if not support Deep Sx
CLKRUN#
8.2K_0402_5%
RC36
1
PCH_DPWROK
+3VS
1
IN2
3
AC_PRESENT
10K_0402_5%
2 PCH_BATLOW#
8.2K_0402_5%
2 PCIE_WAKE#_R
1K_0402_5%
2 PCH_SLP_WLAN#
10K_0402_5%
IN1
2
1
4
2
0
1
@ CC11
1
2
0.1U_0402_10V7K
1
1
5
RC27
+3VS
2
Place CC33
close to UC3.1 & UC3.2
VCC
1
GND
D
1
ESD@
0.047U_0402_16V4Z
*
B
F
D
_
HASWELL_MCP_E
UC1H
+RTCVCC
DPWROK: Tired toghter with RSMRST#
that do not support Deep Sx
R2337 1
R2338 1
@
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
2 330K_0402_5%
2 330K_0402_5%
LOW = DISABLED
SYSTEM POWER MANAGEMENT
<30>
SYS_PWROK
CC31
C
@ESD@
0.047U_0402_16V4Z
<30>
<30>
1
SUSACK#
SUSACK#
2
Place CC31
on BOT
<30>
<30>
2
1
ACIN
DH1
@ESD@
0.047U_0402_16V4Z
2 0_0402_1%
2 0_0402_1%
PBTN_OUT#
RB751V-40_SOD323-2
PCH_PWROK
CC34
2 0_0402_1%
<30>
1
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
PM_APWROK_R
PCH_PLTRST#
SYS_RESET#
RP50
0_8P4R_5%
1
RC41
@
1
RC42
@
<30>
EC_RSMRST#
ME_SUS_PWR_ACK
<30,34,35,48>
@
<6>
8
7
6
5
SYS_PWROK 1
2
3
4
SYS_PWROK
PCH_PWROK
1
RC37
SIO_SLP_S0#
AK2
AC3
AG2
AY7
AB5
AG7
AW6
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R AV4
AL7
PBTN_OUT#
AJ8
AC_PRESENT
AN4
PCH_BATLOW#
AF3
SIO_SLP_S0#
AM5
PCH_SLP_WLAN#
1
2
1
2
RC73
RC74
1
@
2
RC75
1
2
RC76
1
2
1
2
RC77
RC79
1
2
2
1
@ RC87
DGPU_PWROK
10K_0402_5%
PCH_TP_INT#
10K_0402_5%
EDP_BIA_PWM
10K_0402_5%
TS_RST#
10K_0402_5%
DGPU_HOLD_RST#
10K_0402_5%
FFS_INT1
10K_0402_5%
<31,6>
<30>
l
ia
EDP_BIA_PWM
EDP_BIA_PWM
PANEL_BKLEN
<31>
ENVDD_PCH
<30,42>
DGPU_PWROK
<11,37,41,42,49>
PXS_PWREN
<47>
DGPU_HOLD_RST#
<32>
FFS_INT1
ENVDD_PCH
100K_0402_5%
CODEC_IRQ
1K_0402_1%
t
n
<31>
e
d
i
f
n
o
C
@ RC88
S
K
r
fo
U6
DGPU_PWROK
P4
PXS_PWREN
DGPU_HOLD_RST# N4
N2
FFS_INT1
AD4
T117
@
PCH_TP_INT#
TS_RST#
CODEC_IRQ
B8
A9
C6
U7
L1
L3
R5
L4
DSWODVREN
PCH_DPWROK
PCIE_WAKE#_R
V5
AG4
AE6
AP5
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
AJ6
AT4
AL5
AP4
AJ7
SIO_SLP_S4#
SIO_SLP_S3#
@
T105
@
T107
@
T106
1
SLP_SUS#
<30>
+3VS
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
CPU_DPB_CTRLDAT
CPU_DPB_CTRLCLK
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
DISPLAY
GPIO
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
9 OF 19
B9
C9
D9
D11
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
C5
B6
B5
A6
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
C8
A8
D6
DPB_HPD
DPC_HPD
CPU_EDP_HPD#
Rev1p2
DPC_HPD
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
1
2
3
4
8
7
6
5
RP52
2.2K_8P4R_5%
<20>
<20>
CPU_DPB_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
CPU_DPC_AUX#
1
2
3
4
8
7
6
5
B
RP51
100K_8P4R_5%
DPB_HPD
2
<20>
1
RC84
100K_0402_5%
@
2
3
C
SUSCLK
<26>
SIO_SLP_S5#
<30>
T103 PAD~D@
T104 PAD~D @
SIO_SLP_S4#
<30>
SIO_SLP_S3#
<30>
G
1
<30>
<21,30>
Rev1p2
1
CPU_EDP_HPD#
2
@
RC82
0_0402_1%
1
PCH_TP_INT#
EDP_CPU_HPD
<31>
RC89
100K_0402_5%
S
TP_INT#
D
<27>
PCH_DPWROK
PCIE_WAKE#
2 PCIE_WAKE#
@
RC97
0_0402_5%
2
+3VS
TS_RST#
EDP_BKLCTL
PANEL_BKLEN
ENVDD_PCH
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
AW7
AV5
AJ5
HASWELL_MCP_E
UC1I
@
RC81
0_0402_1%
2
1
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
8 OF 19
@
+3VS
DSWVRMEN
DPWROK
WAKE
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
PCH_BATLOW# Need pull high to VCCDSW3_3
(If no deep Sx , connect to VCCSUS3_3)
2
Place CC34
close to RP50.2&RP50.3
B
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
QC3
2N7002K_SOT23-3
1
RC367
2
0_0402_5%
@
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
MCP(8,9/19) DDI,EDP,GPIO
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
10
of
56
5
4
3
2
1
D
4
2
0
1
+1.05VS_PCH
KB_DET#
0_0402_1%
PCH_GPIO56
PCH_GPIO57
SLATE_MODE_R
WL_OFF#
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
TS_INT#
+3VS
<26>
2
C
1
RC11
DEVSLP0
10K_0402_5%
2
1
SIO_EXT_SCI#
100K_0402_5%
2
1
PCH_GPIO56
100K_0402_5%
RC98
RC9
WL_OFF#
@ T174 PAD~D
@ T124 PAD~D
@ T125 PAD~D
<31>
TS_INT#
PCH_GPIO14
PCH_GPIO25
@ T126 PAD~D
@ T127 PAD~D
PCH_GPIO46
+3V_DSW
PCH_GPIO9
EC_SCI#
DEVSLP0
<30>
EC_SCI#
<32>
DEVSLP0
2
1
RC105
GPIO27
10K_0402_5%
<22>
SIO_EXT_SCI#
HDA_SPKR
HDA_SPKR
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
GPIO
LPIO
10K_0402_5%
Add PU for 3D camera function
2
1
KB_DET#
10K_0402_5%
PCH_GPIO44
10K_0402_5%
SLATE_MODE_R
10K_0402_5%
PCH_AUDIO_EN
10K_0402_5%
RC110
2
1
+3VS
l
ia
@
RC118
1K_0402_5%
2
B
PCH_GPIO66
1
t
n
2
@
RC122
1K_0402_5%
PXS_PWREN
<10,37,41,42,49>
8.2K_8P4R_5%
A
1 0_0402_5%
1 0_0402_5%
@
@
1 0_0402_1%
1 0_0402_1%
2
2
1
2
1
2
1
2
1
2
1
RC102
RC106
RC108
C
RC111
RC115
1
2
3
4
8
7
6
5
I2C1_SDA_TP
I2C1_SCL_TP
<31>
<31>
<27>
<27>
KB_RST# 10K_0402_5% 2
1 RC109
10K_0402_5% 2
1 RC114
TS_INT#
+3VS
+3VALW_PCH
2
10K_0402_5%
BBS_BIT
+3VS
@
RC120
1K_0402_5%
B
@
RC121
1K_0402_5%
RC123
1K_0402_5%
HOST_ALERT1_R_N
HDA_SPKR
GPIO66
GPIO86
GPIO15
BOOT BIOS STRAP BIT BBS
HIGH depop RC288 (DEFAULT)
LOW pop RC288
HIGH
LOW(DEFAULT)
LPC
SPI
GPIO81
TLS CONFIDENTIALITY
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
HIGH
LOW(DEFAULT)
GPIO15 NOT Used
+3VALW_PCH
RC124
10K_0402_5%
RC125
10K_0402_5%
PCH_GPIO46
PCH_GPIO9
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
Date:
4
2
10K_8P4R_5%
I2C1_SDA_PNL
I2C1_SCL_PNL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
1
RP53
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
<46>
1
CAM_DETECT
RE74
@
RC119
10K_0402_5%
TOP-BLOCK SWAP OVERRIDE
+3VALW_PCH
RC365 2
RC366 2
CAM_DETECT
@
@
2
1
ODD_DA#
BT_ON#
WL_OFF#
PXS_PWREN
DIS@
RC99
10K_0402_5%
<32>
2
2
+3VS
SERIRQ
10K_0402_5%
LCD_CBL_DET#
10K_0402_5%
CPPE#
100K_0402_5%
CPUSB#
100K_0402_5%
FFS_INT2
100K_0402_5%
2
1
2
3
4
1
e
d
i
f
n
o
C
RP54
2
+3VS
8
7
6
5
r
fo
FFS_INT2
UMA@
RC100
10K_0402_5%
TOPAZ@
RC113
10K_0402_5%
PAD~D T180 @
PAD~D T181 @
RC363
RC364
+3VS
1
RC116
@
PAD~D T179 @
PCH_GPIO66
CAM_DETECT
1
1
JET@
RC112
10K_0402_5%
PAD~D T177 @
PAD~D T176 @
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
2
1
2
RC104
10 OF 19
1
2
RC103
FFS_INT2
LCD_CBL_DET#
+3VS
2
PCH_GPIO57
B
F
D
_
PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
BBS_BIT
DGPU_PRSNT#
PROJECT_ID
PCH_GPIO89
PCH_GPIO90
CPPE#
CPUSB#
PCH_GPIO93
PCH_GPIO94
+3VS
Rev1p2
1
1
2
RC101
49.9_0402_1%
NONOPAL@
RC139
10K_0402_5%
2
2
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
S
K
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
+3VALW_PCH
RC372
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
1
NON3D@
RC130
10K_0402_5%
<30>
<30>
1
<27>
1
RC38
WAKE_PCH#
CPU/
MISC
@
ESD solution
KB_RST#
SERIRQ
2
BT_ON#
2
@
H_THERMTRIP#
KB_RST#
SERIRQ
PCH_OPI_COMP
1
<30>
<26>
D60
V4
T4
AW15
AF20
AB21
2
@ T182 PAD~D
EC_LID_OUT#
<30>
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
1
@ RC371
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
2
P1
AU2
AM7
PCH_GPIO12
AD6
EC_LID_OUT#
Y1
T3
ODD_DA#
AD5
BT_ON#
AN5
GPIO27
HOST_ALERT1_R_N AD7
AN3
KB_DET#
1
PCH_GPIO57
0_0402_5%
2
2
2
1
1
PCH_GPIO89
1
3D_CAM_EN
3D_CAM_EN
PCH_GPIO85
2
2
PCH_AUDIO_EN
<30,46>
2
R2346
1K_0402_5%
RB751V-40_SOD323-2
OPAL@
RC135
10K_0402_5%
1
1
CC28
100P_0402_50V8J
@ESD@
HASWELL_MCP_E
UC1J
DE5
3D@
RC117
10K_0402_5%
Close to R2346
1
2
+1.05VS_PCH
1
+3VS
1
+3VS
D
3
2
MCP(10/19) GPIO,LPIO,MISC
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
11
of
56
5
4
3
2
1
4
2
0
1
D
HASWELL_MCP_E
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
<47>
<47>
<47>
<47>
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
<47>
<47>
<47>
<47>
C
10/100 LAN
<21>
<21>
<21>
<21>
<26>
<26>
NGFF WLAN
<26>
<26>
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
<47>
<47>
<47>
<47>
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
PCIE_PRX_LANTX_N3
PCIE_PRX_LANTX_P3
PCIE_PTX_LANRX_N3
PCIE_PTX_LANRX_P3
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
F10
E10
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
DIS@ CC18 1
DIS@ CC19 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_P0
F8
E8
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
DIS@ CC20 1
DIS@ CC21 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P1
DIS@ CC22 1
DIS@ CC23 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P2
B21
C21
E6
F6
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
B23
A23
H10
G10
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
C23
C22
DIS@ CC24 1
DIS@ CC25 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P3
G11
F11
PCIE_PRX_LANTX_N3
PCIE_PRX_LANTX_P3
PCIE_PTX_LANRX_N3
PCIE_PTX_LANRX_P3
CC32 1
CC40 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PTX_LANRX_N3_C
PCIE_PTX_LANRX_P3_C
C29
B30
F13
G13
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
B22
A21
CC36 1
CC41 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PTX_WLANRX_N4_C
PCIE_PTX_WLANRX_P4_C
B29
A29
G17
F17
C30
C31
<46>
<46>
<46>
<46>
USB3RN4_3D_CAM
USB3RP4_3D_CAM
USB3TN4_3D_CAM
USB3TP4_3D_CAM
+1.05VS_AUSB3PLL
USB3RN4_3D_CAM
USB3RP4_3D_CAM
F15
G15
USB3TN4_3D_CAM
USB3TP4_3D_CAM
B31
A31
RC91
3.01K_0402_1%
1
2
@ T120PAD~D
@ T121PAD~D
PCH_PCIE_RCOMP
B
t
n
e
d
i
f
n
o
C
A
l
ia
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB
PCIe
S
K
USB3TN2
USB3TP2
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
USBRBIAS
USBRBIAS
RSVD
RSVD
PERN2/USB3RN4
PERP2/USB3RP4
r
fo
E15
E13
A27
B27
USB3TN1
USB3TP1
USB3RN2
USB3RP2
PETN4
PETP4
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
USB20_JUSB1_N0
USB20_JUSB1_P0
AR7
AT7
USB20_JUSB2_N1
USB20_JUSB2_P1
AR8
AP8
USB20_JUSB3_N2
USB20_JUSB3_P2
USB20_JUSB1_N0
USB20_JUSB1_P0
<24>
<24>
USB Conn JUSB1
USB20_JUSB2_N1
USB20_JUSB2_P1
<24>
<24>
USB Conn JUSB2
USB20_JUSB3_N2
USB20_JUSB3_P2
<25>
<25>
USB Conn JUSB3
AR10
AT10
AM15
AL15
USB20_MINI1_N4
USB20_MINI1_P4
AM13
AN13
USB20_TOUCH_N5
USB20_TOUCH_P5
AP11
AN11
USB20_CR_N6
USB20_CR_P6
AR13
AP13
USB20_CAM_N7
USB20_CAM_P7
G20
H20
USB3RN1_JUSB1
USB3RP1_JUSB1
B
F
D
_
USB3RN1
USB3RP1
PERN4
PERP4
AN8
AM8
C33
B34
USB3TN1_JUSB1
USB3TP1_JUSB1
E18
F18
USB3RN2_JUSB2
USB3RP2_JUSB2
B33
A33
USB3TN2_JUSB2
USB3TP2_JUSB2
AJ10
AJ11
AN10
AM10
USBRBIAS
USB20_MINI1_N4
USB20_MINI1_P4
USB20_CR_N6
USB20_CR_P6
<26>
<26>
<31>
<31>
<25>
<25>
Mini Card (WLAN)
Touch screen panel
Card Reader
USB20_CAM_N7
USB20_CAM_P7
<31>
<31>
USB3RN1_JUSB1
USB3RP1_JUSB1
<24>
<24>
Camera
C
USB3TN1_JUSB1
USB3TP1_JUSB1
<24>
<24>
USB3RN2_JUSB2
USB3RP2_JUSB2
<24>
<24>
USB3TN2_JUSB2
USB3TP2_JUSB2
<24>
<24>
USB Conn JUSB1
USB Conn JUSB2
PAD~D T118 @
PAD~D T119 @
RC90
22.6_0402_1%~D
AL3 USB_OC0#
AT1 USB_OC1#
AH2 USB_OC2#
AV3 USB_OC3#
USB_OC0#
USB_OC1#
<24>
<25>
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
Rev1p2
11 OF 19
@
USB20_TOUCH_N5
USB20_TOUCH_P5
1
<47>
<47>
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
2
UC1K
<47>
<47>
@
B
+3VALW_PCH
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
1
2
3
4
8
7
6
5
RP55
10K_8P4R_5%
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
D
3
2
MCP(11/19) PCIE,USB
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
12
of
56
5
4
3
VCCST_PG_EC
C79
ESD@
D
C40
2
2
+1.35V
ESD solution
1
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
2
R286
10K_0402_5%
VCCST_PG_EC
VCCST_PG_EC
Define EC OD pin, need double confirm.
+VCCIO_OUT
2
+CPU_CORE
F59
N58
AC58
VCCSENSE
1
R245 @
0_0603_5%
T38
VR_ON
C80
+VCCIOA_OUT
2
C
VR_SVID_ALRT#
Place C80
close to R250.1
Place the PU
resistors close to CPU
R254
43_0402_1%
2
1
<40>
VR_SVID_CLK
<30,40>
VR_ON
<40>
H_VR_READY
<40>
VR_SVID_DAT
1
RF@
C5212
68P_0402_50V8J
Place the PU
resistors close to CPU
2
1
2
@
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
D
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
C
Rev1p2
R253
INTEL Check list , XDP use only
@
+1.35V
CPU_PWR_DEBUG#
VDDQ DECOUPLING
@
R255
10K_0402_5%
1
2
1
2
1
2
1
2
B
1
2
1
2
1
2
1
2
1
2
1
2
C74
10U_0603_6.3V6M
+1.35V : 470UF/2V/7343 *2 (PWR)
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
2
1
1
12 OF 19
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
C45
10U_0603_6.3V6M
2
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
C42
10U_0603_6.3V6M
1
VCC
RSVD
RSVD
C72
10U_0603_6.3V6M
R2
100_0402_1%
AB57
AD57
AG57
C24
C28
C32
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C41
10U_0603_6.3V6M
CAD Note: PD resistor on HW side
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
C39
10U_0603_6.3V6M
t
n
e
d
i
f
n
o
C
VSSSENSE
@
@
@
@
@
@
@
@
@
@
@
@
@
AC22
AE22
AE23
C38
2.2U_0402_6.3V6M
l
ia
T39
T40
T41
T42
T43
T44
T45
T46
T47
T48
T49
T50
T51
C37
2.2U_0402_6.3V6M
VSSSENSE
CAD Note: PU resistor on HW side
r
fo
@
R253
150_0402_1%
C36
2.2U_0402_6.3V6M
<15,40>
2 R250
2 R251
C35
2.2U_0402_6.3V6M
VCCSENSE
@
@
+CPU_CORE
H_CPU_SVIDDATA
R1
100_0402_1%
<40>
1
1
+1.05VS_PCH
+CPU_CORE
VCCSENSE
0_0402_1%
0_0402_1%
S
K
2
R256
130_0402_1%
+1.05VS_PCH
B
2 R248
H_CPU_SVIDCLK
1
2
@
R257
0_0402_1%
2
1
@
CPU_PWR_DEBUG#
RF
SVID DATA
1
L62
N63
L63
B59
F60
C59
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDATA
VCCST_PG_EC
VR12.5_VR_ON_R
VR_READY_R
H_CPU_SVIDALRT#
+1.05VS_PCH
SVID_DAT need to pull-up double side
( PWR_VR & CPU )
0_0402_1%
RSVD
RSVD
B
F
D
_
2
+1.05VS_PCH
R252
75_0402_5%
<40>
ESD@
0.1U_0402_10V7K
1
SVID ALERT
@
+VCCIO_OUT_R
1
E63
AB23
A59
E20
AD23
AA23
AE59
4
2
0
1
+CPU_CORE
HASWELL_MCP_E
UC1L
22U_0603_6.3V6M
@ESD@
+1.05VS_PCH
Place C79
between R286 and UC1
<30>
1
+1.35V
+CPU_CORE
1
1
220P_0402_50V8J
2
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
MCP(12/19) Power
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
13
of
56
4
3
2
1
+1.05VS_PCH
2 1U_0402_6.3V6K
+
2
+CPU_CORE
22U_0603_6.3V6M
@ESD@
C47
1
2
@ESD@
@ESD@
2
Close to N8
C57 @1
+1.05VS_PCH
1
CD65
330U_D3_2.5VY_R6M
+
CD63
330U_D3_2.5VY_R6M
1
D
+1.05VS_PCH
C46
1
2
22U_0603_6.3V6M
@ESD@
ESD solution
+1.05VS_AUSB3PLL
2
C58
C59
1
1
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
HASWELL_MCP_E
UC1M
+1.05VS_ASATA3PLL
L21
2
C63
C65
K9
L10
M9
N8
P9
B18
B11
+1.05VS_PCH
1
1
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
+1.05VS_PCH
2.2UH_LQM2MPN2R2NG0L_30%
+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL
+1.05VS_APLLOPI
R267
0_0805_1%
1
2
@
C69
2
L31
@
C70
2.2UH_LQM2MPN2R2NG0L_30%
1
@1
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
Y20
AA21
W21
+1.05VS_APLLOPI
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
2
L4 1
2.2UH_LQM2MPN2R2NG0L_30%
C
1
1
C83
C84
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
1
C92
1 RC142
1
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
J13
DCPSUS3
@
AH14
1 RC143 AH13
VCCHDA
DCPSUS2
+3V_DSW
+3VS
AC9
AA9
AH10
V8
W9
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
OPI
+3VS +3VALW_PCH
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
AXALIA/HDA
VRM/USB2/AZALIA
CORE
S
K
GPIO/LCC
+VCCHDA
RC127
1
2 0_0402_5%
+1.05VS_AXCK_DCB
RC128
1
@
2 0_0402_5%
RC129
1
@
2 0_0402_5%
+1.05VS_AXCK_LCPLL
+1.05VS_PCH
+1.05VS_PCH
C77
+VCCHDA
1
2 0.1U_0402_10V7K
Reserve for HDA issue, C77 close to AH14
+3VALW_PCH
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
SDIO/PLSS
r
fo
LPT LP POWER
SUS OSCILLATOR
USB2
13 OF 19
1
1
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
+3V_DSW
C81
1
2 1U_0402_6.3V6K
Close to AH10
+3VALW_PCH
C78
1
2 22U_0603_6.3V6M
Close to AC9/AA9/AE20/AE21
+3VS
C82
1
2 22U_0603_6.3V6M
Close to V8
B
Close to K9,M9
t
n
e
d
i
f
n
o
C
+1.05VS_PCH
C87
1
2 1U_0402_6.3V6K
Close to J17
+1.05VS_PCH
C88
1
2 1U_0402_6.3V6K
Close to R21
C75
2
1 0.1U_0402_10V7K
Close to AH14
+3VALW_PCH
A
l
ia
C50
C53
+1.05VS_PCH
@
1 R264
+3VALW_PCH
2 1U_0402_6.3V6K
+RTCVCC
C52 1
2 0.1U_0402_10V7K
B
F
D
_
USB3
THERMAL SENSOR
+1.5VS
1
+VCCRTCEXT
VCCSPI
@2 1U_0402_6.3V6K
+3VALW_PCH
C51
+3VALW_PCH
SPI
@2 1U_0402_6.3V6K
0_0402_5% 2
C91
1
1
C85
C86
@
+VCCHDA
+1.05VS_PCH
+1.05VS_AXCK_LCPLL
2
L5 1
2.2UH_LQM2MPN2R2NG0L_30%
AH11
AG10
AE7
VCCSUS3_3
VCCRTC
DCPRTC
RTC
+1.05VS_AXCK_DCB
0_0402_5% 2
2
0_0603_1%
mPHY
VCCASW
VCCASW
+1.05VS_PCH
1U_0402_6.3V6K
C54
L11
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
Y8
@
C68 1
2 0.1U_0402_10V7K
AG14
AG13
+1.05VS_PCH
@
J15
K14
K16
U8
T9
C60
C61
C62
1
1
1
2 10U_0603_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
@
C66
C67
1
1
RC137
1
C93
@
1
C73 1
2 22U_0603_6.3V6M
2 1U_0402_6.3V6K
2
1U_0402_6.3V6K
RC136
1
AC20
AG16
AG17
@
+1.05VS_PCH
+1.35V
C43
1
2
22U_0603_6.3V6M
ESD@
+1.5VS
+3VS
ESD solution
+3VS
2
+3V_DSW
C5215
2 0_0402_5%
+1.05VS_PCH
2 1U_0402_6.3V6K
C90 @1
2 47U_0603_2.5V7
CC37 @1
2 47U_0603_2.5V7
CC38 @1
1
Reserve for inrush
current issue
2
0.47U_0402_6.3V6K
@
+1.05VS_PCH
C76 1
1U_0402_6.3V6K
Rev1p2
@
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
C
+1.05VS_PCH
+PCH_VCCDSW
AB8
2
ESD solution
2 0_0402_5% +1.05VS_PCH
2 1U_0402_6.3V6K
@
2 0.1U_0402_10V7K
2
1
22U_0603_6.3V6M
@ESD@
C64
1U_0402_6.3V6K
1
2
+PCH_VCCDSW
C71 1
2
1
D
+1.05VS_PCH
+3VS
C44
1
2
+1.05VS_PCH
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
1
0.1U_0402_10V7K
C55
+RTCVCC
+1.05VS_PCH
4
2
0
1
0.1U_0402_10V7K
C56
5
3
2
MCP(13/19) Power
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
14
of
56
5
4
3
2
1
D
B
UC1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
t
n
e
d
i
f
n
o
C
14 OF 19
Rev1p2
@
A
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
l
ia
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19 Rev1p2 VSS
UC1P
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
B
F
D
_
S
K
r
fo
VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS
@
C
V58
AH46
V23
E62
AH16
VSSSENSE
<13,40>
1
C
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X@
RC163
100_0402_1%
@
2
UC1N
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
4
2
0
1
B
CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU
@
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
D
3
2
MCP(14,15,16/19) VSS
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
15
of
56
5
4
3
2
1
D
HASWELL_MCP_E
UC1Q
AY2
DC_TEST_AY2_AW2
AY3
DC_TEST_AY3_AW3
AY60
DC_TEST_AY60
DC_TEST_AY61_AW61 AY61
DC_TEST_AY62_AW62 AY62
B2
TP_DC_TEST_B2
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
B63
DC_TEST_B62_B63
C1
C2
DC_TEST_C1_C2
@ T166PAD~D
@ T167PAD~D
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
HASWELL_MCP_E
UC1R
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2
A3
A4
DC_TEST_A3_B3
DC_TEST_A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
RSVD
RSVD
RSVD
RSVD
PAD~D T168 @
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AW63
PAD~D T169 @
PAD~D T170 @
PAD~D T171 @
PAD~D T172 @
@
T128 PAD~D
@
T132 PAD~D
@
T134 PAD~D
@
T135 PAD~D
AT2
RSVD_AT2
RSVD_AU44 AU44
RSVD_AV44 AV44
D15
RSVD_D15
@
T138 PAD~D
@
T140 PAD~D
@
T143 PAD~D
RSVD_F22
RSVD_H22
RSVD_J21
F22
H22
J21
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
B
F
D
_
PAD~D T173 @
18 OF 19
@
@
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
4
2
0
1
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
PAD~D
PAD~D
PAD~D
PAD~D
@
T129
@
T130
@
T131
@
T133
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T136
T137
T139
T141
T142
T144
T145
D
@
@
@
@
@
@
@
Rev1p2
@
C
B
AA62
U63
AA61
U62
CFG_RCOMP
V63
A5
@ T159PAD~D
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
t
n
CFG_RCOMP
RSVD
e
d
i
f
n
o
C
@ T161PAD~D
@ T163PAD~D
@ T164PAD~D
@ T165PAD~D
TDI_IREF
E1
D1
J20
H18
B12
RSVD
RSVD
RSVD
RSVD
TD_IREF
19 OF 19
@
2
RC132
1
RC133
A
C63
C62
B43
A51
B51
RSVD
RSVD
VSS
VSS
RSVD
RSVD
L60
N60
W23
Y22
AY15
r
fo
PAD~D T146 @
PAD~D T147 @
PAD~D T148 @
PAD~D T149 @
PAD~D T150 @
l
ia
RSVD_TP
RESERVED
AV63
AU63
CFG STRAPS for CPU
CFG4
1
CFG4
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
S
K
HASWELL_MCP_E
RC138
1K_0402_1%
PAD~D T151 @
PAD~D T152 @
2
UC1S
C
PAD~D T153 @
PAD~D T154 @
B
PAD~D T155 @
PAD~D T156 @
Display Port Presence Strap
PROC_OPI_RCOMP
AV62
D58
PAD~D T157 @
PAD~D T158 @
1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
P22
N21
P20
R20
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
PAD~D T160 @
PAD~D T162 @
Rev1p2
1
CFG_RCOMP
49.9_0402_1%
2 TDI_IREF
8.2K_0402_1%
PROC_OPI_RCOMP 1
49.9_0402_1%
2
RC134
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
MCP(17,18,19/19) CFG,RSVD
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
16
of
56
4
3
2
H=4mm
+DIMM1_VREF_DQ
+1.35V
2-3A to 1 DIMMs/channel
DDR_A_DQS#1
DDR_A_DQS1
<7>
DDR_A_DQS#[0..7]
<7>
DDR_A_D[0..63]
<7>
DDR_A_DQS[0..7]
<7>
DDR_A_MA[0..15]
DDR_A_D10
DDR_A_D11
All VREF traces should
have 10 mil trace width
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMM1
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
+1.35V
2
1
2
CD11
1U_0402_6.3V6K
2
1
CD10
1U_0402_6.3V6K
2
1
CD9
1U_0402_6.3V6K
2
1
CD8
1U_0402_6.3V6K
2
1
CD7
1U_0402_6.3V6K
2
1
CD6
1U_0402_6.3V6K
1
CD5
1U_0402_6.3V6K
2
CD4
1U_0402_6.3V6K
1
C
<7>
DDR_CKE0_DIMMA
DDR_CKE0_DIMMA
<7>
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
+1.35V
2
2
1
2
+
2
<7>
DDR_A_BS0
<7>
<7>
DDR_A_WE#
DDR_A_CAS#
<7>
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_CS1_DIMMA#
DDR_A_D40
DDR_A_D41
B
t
n
+0.675VS
CD29
10U_0603_6.3V6M
CD28
10U_0603_6.3V6M
CD27
0.1U_0402_10V7K
CD26
0.1U_0402_10V7K
2
1
2
1
2
1
2
1
2
RD61
2 10K_0402_5%
1
RD7
2
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
+3VS
10K_0402_5%
+3VS
1
2
@
1
2
CD31
0.1U_0402_10V7K
e
d
i
f
n
o
C
1
CD30
2.2U_0402_6.3V6M
A
CD25
0.1U_0402_10V7K
2
CD24
0.1U_0402_10V7K
1
l
ia
DDR_A_D34
DDR_A_D35
Layout Note:
Place near JDIMM1.203,204
+0.675VS
r
fo
205
207
GND1
BOSS1
GND2
BOSS2
1
2
DDR_A_D12
DDR_A_D13
<18>
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
1
DDR_A_D20
DDR_A_D21
2
DDR_A_D22
DDR_A_D23
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
S
K
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_D38
DDR_A_D39
1
C
M_ODT
CD64 ESD@
0.1U_0402_10V7K
<7>
<7>
+5VALW
2
2
2
+1.35V
QD2
BSS138-G_SOT23-3
<7>
1
3
1
R2348
1
R2349
1
R2350
1
R2352
M_ODT
R2347
220K_0402_5%~D
+SM_VREF_CA_DIMM
1
1
Place CC31
between QD2 and R2349
DDR3L SODIMM ODT GENERATION
<7>
<7>
1
<6>
<7>
DDR_CS0_DIMMA#
M_ODT1
DDR_A_D36
DDR_A_D37
DDR3_DRAMRST#_CPU
@
B
F
D
_
DDR_A_DQS#3
DDR_A_DQS3
2
@
RD5
0_0402_1%
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_A_D28
DDR_A_D29
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1
DDR3_DRAMRST#
@ESD@
CD3
0.1U_0402_10V7K
CD21
DDR_A_DQS#4
DDR_A_DQS4
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
RD3
470_0402_5%
CD22
0.1U_0402_10V7K
DDR_A_D32
DDR_A_D33
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_A_D6
DDR_A_D7
2.2U_0402_6.3V6M
CD15
330U_D3_2.5VY_R6M
2
1
1
CD14
2
1
10U_0603_6.3V6M
CD13
2
1@
10U_0603_6.3V6M
CD20
2
1
10U_0603_6.3V6M
CD19
1
10U_0603_6.3V6M
CD18
1@
10U_0603_6.3V6M
CD12
10U_0603_6.3V6M
CD17
2
10U_0603_6.3V6M
CD16
10U_0603_6.3V6M
1
<7>
<7>
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
D
+1.35V
DDR_A_DQS#0
DDR_A_DQS0
S
DDR_A_D8
DDR_A_D9
DDR_A_D4
DDR_A_D5
D
DDR_A_D2
DDR_A_D3
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
G
2
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
2
1
DDR_A_D0
DDR_A_D1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
2
1
CD2
0.1U_0402_10V7K
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
CD1
2.2U_0402_6.3V6M
@
RD1
0_0402_1%
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
@
RD4
0_0402_1%
2
+SM_VREF_DQ0_DIMM1
2
4
2
0
1
+1.35V
JDIMM1
1
1
@
R2351
2M_0402_5%
0.675V_DDR_VTT_ON
2
M_ODT0
66.5_0402_1%
2
M_ODT1
66.5_0402_1%
2
66.5_0402_1%
2
66.5_0402_1%
0.675V_DDR_VTT_ON
M_ODT2
<18>
M_ODT3
<18>
<39>
1
5
DDR_A_D44
DDR_A_D45
B
DDR_A_DQS#5
DDR_A_DQS5
+1.35V
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
U2303
1
<6>
DDR_PG_CTRL
2
3
DDR_A_D54
DDR_A_D55
NC
VCC
A
Y
5
4
1
@
CD23
0.1U_0402_10V7K
2
0.675V_DDR_VTT_ON
GND
74AUP1G07GW_TSSOP5
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
DDR_XDP_WLAN_TP_SMBDAT
DDR_XDP_WLAN_TP_SMBCLK
<18,32,9>
<18,32,9>
+0.675VS
206
208
BELLW_80001-1021
CONN@
A
+1.35V
CD62
1
2
22U_0603_6.3V6M
ESD@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
ESD solution
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
DDRIII DIMMA
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
17
of
56
5
4
3
2
+DIMM2_VREF_DQ
H=4mm
+1.35V
+1.35V
JDIMM2
+SM_VREF_DQ1_DIMM2
1
2
2
1
2
CD33
0.1U_0402_10V7K
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
1
CD32
2.2U_0402_6.3V6M
@
RD8
0_0402_1%
D
DDR_B_D23
DDR_B_D17
DDR_B_D21
DDR_B_D18
DDR_B_D3
DDR_B_D2
DDR_B_DQS#0
DDR_B_DQS0
<7>
DDR_B_DQS#[0..7]
<7>
DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
All VREF traces should
have 10 mil trace width
<7>
DDR_B_DQS[0..7]
<7>
DDR_B_MA[0..15]
DDR_B_D12
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMM2
DDR_B_D14
DDR_B_D15
DDR_B_D31
DDR_B_D25
DDR_B_D27
DDR_B_D24
+1.35V
2
1
2
CD42
1U_0402_6.3V6K
2
1
CD41
1U_0402_6.3V6K
2
1
CD40
1U_0402_6.3V6K
2
1
CD39
1U_0402_6.3V6K
2
1
CD38
1U_0402_6.3V6K
2
1
CD37
1U_0402_6.3V6K
1
CD36
1U_0402_6.3V6K
2
CD35
1U_0402_6.3V6K
1
C
<7>
DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
<7>
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
+1.35V
<7>
<7>
2
1
2
1
2
1
+
2
CD51
330U_D3_2.5VY_R6M
2
1
CD50
10U_0603_6.3V6M
1
CD49
10U_0603_6.3V6M
2
@
CD48
10U_0603_6.3V6M
2
1
CD47
10U_0603_6.3V6M
1
CD46
10U_0603_6.3V6M
2
@
CD45
10U_0603_6.3V6M
1
CD44
10U_0603_6.3V6M
2
CD43
10U_0603_6.3V6M
1
<7>
<7>
DDR_B_BS0
<7>
<7>
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_DQS#4
DDR_B_DQS4
t
n
+0.675VS
CD59
10U_0603_6.3V6M
CD58
10U_0603_6.3V6M
CD57
0.1U_0402_10V7K
CD56
0.1U_0402_10V7K
2
1
2
1
2
1
2
1
2
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D53
DDR_B_D63
DDR_B_D62
DDR_B_D58
DDR_B_D59
+3VS
2
RD12
+3VS
1
10K_0402_5%
+0.675VS
2
@
1
2
CD61
0.1U_0402_10V7K
1
CD60
2.2U_0402_6.3V6M
e
d
i
f
n
o
C
1
DDR_B_D52
DDR_B_D49
RD13
10K_0402_5%
A
CD55
0.1U_0402_10V7K
2
CD54
0.1U_0402_10V7K
1
l
ia
DDR_B_D43
DDR_B_D42
1
B
DDR_B_D40
DDR_B_D45
2
Layout Note:
Place near JDIMM2.203,204
DDR_B_D36
DDR_B_D38
205
2-3A to 1 DIMMs/channel
DDR_B_D22
DDR_B_D16
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D20
DDR_B_D4
DDR_B_D5
DDR3_DRAMRST#
DDR_B_D6
DDR_B_D7
DDR_B_D13
DDR_B_D9
DDR_B_D11
DDR_B_D10
DDR_B_D30
DDR_B_D26
DDR3_DRAMRST#
2
@ESD@
CD34
0.1U_0402_10V7K
@
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_B_DQS#3
DDR_B_DQS3
B
F
D
_
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G1
G2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D29
DDR_B_D28
DDR_CKE3_DIMMB
<17>
1
DDR_CKE3_DIMMB
4
2
0
1
<7>
C
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
<7>
<7>
<7>
<7>
DDR_CS2_DIMMB#
M_ODT2
<17>
M_ODT3
<7>
<17>
+SM_VREF_CA_DIMM
1
DDR_B_D33
DDR_B_D34
1
DDR_B_D39
DDR_B_D37
2
1
2
2
@
RD10
0_0402_1%
DDR_B_D44
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
B
DDR_B_D47
DDR_B_D46
DDR_B_D51
DDR_B_D55
DDR_B_D48
DDR_B_D54
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D60
DDR_B_D61
DDR_XDP_WLAN_TP_SMBDAT
DDR_XDP_WLAN_TP_SMBCLK
<17,32,9>
<17,32,9>
+0.675VS
206
BELLW_80011-1021
CONN@
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
D
DDR_B_MA15
DDR_B_MA14
CD53
0.1U_0402_10V7K
DDR_B_D32
DDR_B_D35
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CD52
2.2U_0402_6.3V6M
r
fo
DDR_CS3_DIMMB#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
S
K
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
3
2
DDRIII DIMMB
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
18
of
56
5
4
3
2
1
4
2
0
1
D
UG1
GCLK@
UG1
@
SLG3NB3375VTR TQFN 16P CRYSTALSLG3NB3374VTR TQFN 16P CRYSTAL
@
SLG3NB3374V is for DIS by output 24M*1,25M*1, 27M*1, 32K*1
SLG3NB3375V is for UMA by output 24M81, 25M*1, 32K*1
+RTCVCC
+RTCBATT
B
F
D
_
+3VLP
+3VALW
CG4
2
1
RG2 @
0_0402_5%
2
GCLK@
1
0.1U_0402_10V7K
CG3
2
GCLK@
1
0.1U_0402_10V7K
CG2
2
0.1U_0402_10V7K
C
1 GCLK@
CG10
CG5
22U_0805_6.3V6M
2
GCLK@
1
1
2
UG1
GCLK_VRTC
Place close
to UG1.8
10
15
+3VLP
2
+3VALW
2
VBAT
VDD_RTC_OUT
+V3.3A
VDD
GCLK@
1
YG1
15P_0402_50V8J
1
3
CG9
2
GCLK@
1
OSC
OSC
GCLK@
GND
GND
25MHz_B
r
fo
XTAL_IN
XTAL_OUT
SLG3NB274VTR_TQFN16_2X3
2
@
4
25MHZ_10PF_7V25000014
CLK_X2
12P_0402_50V8J
B
t
n
e
d
i
f
n
o
C
A
1
16
25MHz_A
VDDIO_25M_B
l
ia
PCH_RTCX1_R
12
6
LAN_X1_R
5
PCH_X1_R
GND4
CLK_X1
CLK_X2
CLK_X1
CG8
2
VDDIO_25M_A
GND1
GND2
GND3
3
9
CPU_RTC 32.768k(P.8)
Place RG3 close to YC1
0_0402_5%
RG3
1
2
GCLK@
RG5
1
RG6
1
C
GCLK@
2 33_0402_5%
PCH_RTCX1
<8>
1
XTLI_R
GCLK@
2 22_0402_5%
GCLK@
XTAL24_IN
<9>
CPU_CLK 24M(P.9)
Place RG6 close to YC2
RG8
1
2
GCLK@
CG7
5P_0402_50V8C
2
GCLK@
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
Date:
4
<21>
RG3,RG8, RG6 0ohm_0402
for isolated CLK tail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
XTLI
0_0402_5%
LAN 25M(P.21)
Place RG8 close to YL2
17
8
+1.05VS_PCH
27MHz
4
7
13
+LAN_VDD33
VDDIO_27M
RTC_VOUT
S
K
32kHz
11
14
2.2U_0603_6.3V6K
CG6
0.1U_0402_10V7K
1 GCLK@
2
+LAN_VDD33
RG1
330_0402_5%
GCLK@
2
+1.05VS_PCH
1
1
+RTCVCC
RG4
330_0402_5%
@
D
3
2
Green CLK
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
19
of
56
5
4
3
2
1
Place close to JHDMI
D
4
2
0
1
D
<6>
<6>
DDI1_LANE_N1
DDI1_LANE_P1
<6>
<6>
DDI1_LANE_N0
DDI1_LANE_P0
CX12 2
CX13 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TXCN
TMDS_TXCP
CX14 2
CX15 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TX0N
TMDS_TX0P
CX16 2
CX17 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TX1N
TMDS_TX1P
CX18 2
CX19 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TX2N
TMDS_TX2P
4
TMDS_TXCP
4
LX2
3
3
1
FX1
1.5A_6V_1206L150PR~D
TMDS_L_TXCP
EMI@
+3VS
1
DDI1_LANE_N2
DDI1_LANE_P2
2
+5VS
TMDS_TX0N
1
TMDS_TX0P
4
WCM-2012HS-900T_4P
2
1
2
4
3
2
1
4
LX3
3
3
TMDS_L_TX0P
HDMI_HPLUG
EMI@
@
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CPU_DPB_CTRLDAT_R
CPU_DPB_CTRLCLK_R
5
6
7
8
B
F
D
_
TMDS_L_TXCN
1
+3VS
TMDS_TX1N
1
TMDS_TX1P
4
D
1
2
4
LX4
3
3
TMDS_L_TX1N
TMDS_L_TXCP
TMDS_L_TX0N
TMDS_L_TX1P
TMDS_L_TX0P
TMDS_L_TX1N
EMI@
TMDS_L_TX1P
TMDS_L_TX2N
QX3
2N7002K_SOT23-3
G
TMDS_L_TX2P
S
2
3
RX13
100K_0402_5%
LX5
EMI@
S
K
4
TMDS_TX2P
1
TMDS_TX2N
4
3
1
2
3
TMDS_L_TX2P
2
TMDS_L_TX2N
WCM-2012HS-900T_4P
l
ia
D
G
5
S
e
d
i
f
n
o
C
4
3
QX4A
DMN66D0LDW-7_SOT363-6
A
RO0000002HM
@EMI@
CX23
1
2 3.3P_0402_50V8C
@EMI@
CX24
1
2 3.3P_0402_50V8C
TMDS_L_TX0N
@EMI@
CX25
1
2 3.3P_0402_50V8C
TMDS_L_TX0P
@EMI@
CX26
1
2 3.3P_0402_50V8C
TMDS_L_TX1N
@EMI@
CX27
1
2 3.3P_0402_50V8C
TMDS_L_TX1P
@EMI@
CX28
1
2 3.3P_0402_50V8C
TMDS_L_TX2N
@EMI@
CX29
1
2 3.3P_0402_50V8C
TMDS_L_TX2P
@EMI@
CX30
1
2 3.3P_0402_50V8C
Description
HDMI W/Logo:RO0000002HM
B
RX17
2.2K_0402_5%
+3VS
C
QX5
MMBT3904_NL_SOT23-3
CPU_DPB_CTRLDAT_R
D
CPU_DPB_CTRLDAT
S
<10>
<10>
2
B
E
1
2
RX15
150K_0402_5%
DPB_HPD
HDMI_HPLUG
1
2
RX14
100K_0402_5%
CX20
220P_0402_50V8J
@
RX34
20K_0402_5%
A
Compal Secret Data
Security Classification
Issued Date
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
C
1
CPU_DPB_CTRLCLK_R
20
21
22
23
ROYALTY HDMI W/LOGO
Part Number
TMDS_L_TXCP
3
6
46@
1
1
CPU_DPB_CTRLCLK
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
2
2
G
<10>
2
t
n
RX16
2.2K_0402_5%
QX4B
DMN66D0LDW-7_SOT363-6
JHDMI
CONCR_099ATAC19NBLCNF
CONN@
TMDS_L_TXCN
1
+3VS
1
B
2
+5VS
r
fo
CX22
2
2
C
WCM-2012HS-900T_4P
2
1
2
2
1
1
1
2
3
4
RP58
680_8P4R_5%
8
7
6
5
RP59
680_8P4R_5%
1
RX12
10K_0402_5%
TMDS_L_TX0N
2
DDI1_LANE_N3
DDI1_LANE_P3
<6>
<6>
W=40mils
TMDS_L_TXCN
CX21
<6>
<6>
WCM-2012HS-900T_4P
2
1
2
0.1U_0402_16V7K
1
TMDS_TXCN
10U_0603_6.3V6M
+VDISPLAY_VCC
3
2
Compal Electronics, Inc.
HDMI
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
20
of
56
3
+LAN_IO rising time : >1ms and <100ms
W=40mils
JP3
4
5
60mils_3via
@
2
1
W=40mils
2MM
+3VALW
2
UL3
1
OC
4
EN
B
F
D
_
WOL_EN
SY6288C20AAC_SOT23-5
B
CL30, CL31 close to UL1 Pin 17, 18
UL1
+LAN_VDD10
<12>
<12>
CL30 1
CL31 1
PCIE_PRX_LANTX_P3
PCIE_PRX_LANTX_N3
2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C
2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C
17
18
HSOP
HSON
AVDD10
AVDD10
AVDD10
DVDD10
<12>
<12>
13
14
PCIE_PTX_LANRX_P3
PCIE_PTX_LANRX_N3
PCIE_PTX_LANRX_P3
PCIE_PTX_LANRX_N3
<10,26,30,47>
<10,30>
19
PLT_RST#
PCIE_WAKE#
+LAN_VDD33
ISOLATEB
20
PCIE_WAKE#
21
1
RL39
2
10K_0402_5%
26
@
6
7
9
10
C
HSIP
HSIN
PERSTB
ISOLATEB
LANWAKEB
LED1/GPO
NC
NC
NC
NC
VDDREG
REGOUT
S
K
MDIP0
MDIN0
MDIP1
MDIN1
REFCLK_P
REFCLK_N
CLKREQB
CKXTAL1
CKXTAL2
1
2
4
5
+LAN_VDDREG
+LAN_REGOUT
MDI0+
MDI0MDI1+
MDI1-
15
16
12
28
29
XTLO
XTLI
l
ia
LED2
LED0
RSET
GND
t
n
11
32
23
24
25
27
31
33
@
@
RL31 2
r
fo
CLK_PCIE_LAN
CLK_PCIE_LAN#
<9>
<9>
LAN_CLKREQ#
<9>
1
+LAN_VDD33
RL33
1K_0402_5%
e
d
i
f
n
o
C
2
PCIE_WAKE#
2
1
RL34
10K_0402_5%
1
1
2
@
2
1
@1
2
These caps close to UL1: Pin 11,32
+LAN_VDD33 Rising time (10%~90%)要>1mS and <100mS
B
S X'FORM_ NS0015 LF LAN
SP050005Y00
1
2
3
4
5
6
7
8
MDI1MDI1+
MDI0MDI0+
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
MDO1MDO1+
MCT0
MCT0
1
RL19
75_0603_5%
2
MCT1
1
2
RL20
75_0603_5%
MCT1
MDO0MDO0+
1
2
EMI@
CL33
10P_1206_2KV8J
Place close to TCT pin
350UH_LF-H1201P-2
@
CL41
0.01U_0402_16V7K
T94 PAD~D
T95 PAD~D
C
1 2.49K_0402_1%
For GCLK
<19>
JLAN
8
XTLI
XTLI
7
MDO1CL36
1
2
6
5
XTLI
4
YL2
10P_0402_50V8J
1
XTAL@
ISOLATEB
2
2
@
TL2
2
RTL8106E-CG QFN 32P E-LAN CTRL
+3VS
2
@1
2 0_0603_5%
TL2
3
8
30
22
+LAN_VDD33
AVDD33
AVDD33
@1
2
A
4.7U_0603_6.3V6K
3
5
IN
GND
2
1
Place close to each VDD10 pin
0.1U_0402_16V4Z
1
2
10K_0402_5%
OUT
2
1
+LAN_VDDREG
@
RL6 1
10U_0603_6.3V6M
CL14
RL40
4.7U_0603_6.3V6K
CL13
2
0.1U_0402_16V7K
CL12
+3VALW
@
+LAN_VDD33
+3VALW
2
RTL8111GS(SWR mode)
APL3512 PIN 4 tire to VIN
+LAN_VDD33
2
1
1U_0402_6.3V4Z
CL9
RTL8111G(LDO mode)
2
1
0.1U_0402_25V6
CL8
@
CL38
0.1U_0603_25V7K
1
0.1U_0402_25V6
CL7
1
4
2
0
1
1
0.1U_0402_25V6
CL6
2
CL3
0.1U_0402_25V6
2 LAN_L@
0.1U_0402_25V6
CL5
2
2
2
GND
APL3512ABI-TRG_SOT23-5
@
1
CL19
4.7U_0603_6.3V6K
CL4
1
SS
CL15
40mils_2via
1
2
LL1
2.2UH_LQM2MPN2R2NG0L_30%
1
LAN_SW@
1
EN
4
RL27
100K_0402_5%
+LAN_REGOUT
1.5A
1
VOUT
0.1U_0402_10V7K
VIN
3
WOL_EN
WOL_EN
W=40mils
UL2
5
0.1U_0402_10V7K
CL39
1U_0402_6.3V6K
2
1
A
+LAN_VDD10
LAN_SW@
+LAN_VDD33
<30>
2 LAN_L@ 1
RL1
0_0603_5%
+LAN_REGOUT
CL17
2
CL16
1
CL37
1
2
10P_0402_50V8J
RL35
15K_0402_5%
3
OSC
GND
OSC
GND
2
MDO1+
3
4
MDO0-
2
MDO0+
1
25MHZ_10PF_7V25000014
XTLO
PR4PR4+
PR2PR3PR3+
PR2+
PR1PR1+
XTAL@
GND
GND
XTAL@
10
1
+3VS +LAN_VDD33
9
XTAL
CONN@
@
LAN_CLKREQ#
1
RL37
2
10K_0402_5%
@
D
WOL_EN
1
RL38
2
10K_0402_5%
D
Reserve 10K pull LAN_IO
1
2
Compal Secret Data
Security Classification
Issued Date
2014/03/26
Deciphered Date
2015/03/31
Compal Electronics, Inc.
LAN
RTL8106EUS
Size Document Number
Rev
Custom
0.1
LA-B016P
of
Monday, October 20, 2014
21
56
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
5
4
3
1
1
2
27
39
7
0_0402_5%
2
4
@ RA1113
49
@EMI@
CA21
22P_0402_50V8J
RESETB
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
LINE1-VREFO-R
LINE1-VREFO-L
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)
42
43
45
44
SPK-OUT-L+
SPK-OUT-LSPK-OUT-R+
SPK-OUT-R-
37
35
CBP
CBN
1U_0402_6.3V6K 2
PDB
28
12
34
VREF
PCBEEP
CPVEE
LDO1-CAP
LDO2-CAP
LDO3-CAP
DVSS
1
1U_0402_6.3V6K 2
CA23
1 CA25
25
38
AVSS1
AVSS2
S
K
GND
2
1 RA79
1K_0402_1%
1
2
1
3
2
4
6
D
2
G
1
S
@
G
RA7
S
2
10K_0402_5%
QA6A
DMN66D0LDW-7_SOT363-6
t
n
e
d
i
f
n
o
C
1 CA65
0.1U_0402_16V7K
r
fo
2
10K_0402_5%
l
ia
2
1
LA9
2
1
1
LA8
INT-SPK-RINT-SPK-R+
INT-SPK-LINT-SPK-L+
<31>
MIC_IN
2.2K_0402_5%
1
RING2
2.2K_0402_5%
1
4
6
1
RA29
1
RA30
1
2 0_0603_1%
@
2 0_0603_1%
@
RA31
1
RA32
1
2 0_0603_1%
C
@
2 0_0603_1%
@
GNDA
GND
Place on the moat between GND & GNDA.
DA8
EC Beep
<30>
2
BEEP#
1
MCU Beep
<11>
PC_BEEP
3
HDA_SPKR
@
RA19
10K_0402_5%
PC Beep
B
EMI@
EMI@
EMI@
EMI@
LA3
LA4
LA5
LA6
1
1
1
1
2
2
2
2
NBQ160808T-800Y-N 0603
NBQ160808T-800Y-N 0603
NBQ160808T-800Y-N 0603
NBQ160808T-800Y-N 0603
RING2_R
AUD_HP_OUT_L_CN
3
1
JACK_PLUG#
5
JSPK
1
2
3
4
5
6
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-RSpeaker 4 ohm : 40mil
Speaker 8 ohm : 20mil
1
2
1
2
1
2
1
2
ESD@
DA13
1
2
3
4
G1
G2
ACES_50278-00401-001
CONN@
ESD@
DA14
6
AUD_HP_OUT_L_CN
AUD_HP_OUT_R_CN
2
AUD_HP_OUT_R_CN
MIC_IN_R
4
7
1
2
A
2
ESD@
DA12
AZ5123-02S SOT23
2
ESD@
DA10
AZ5125-02S.R7G_SOT23-3
1
CA40 EMI@
1000P_0402_50V7K
2
CA38 EMI@
1000P_0402_50V7K
1
CA33 EMI@
100P_0402_50V8J
4
2 200K_0402_5% JACK_SENSE#
SINGA_2SJ3080-001111F
CONN@
CA39 EMI@
100P_0402_50V8J
2
5
1
2
RA1109
BAT54C-7-F_SOT23-3
RING2_R
@
1
1
close to Codec
MIC_IN_R
3
2
@
2
A_MIC_CLK
@EMI@
CA22
22P_0402_50V8J
RA83
10K_0402_5%
2
RA84
10K_0402_5%
A
40mil
40mil
1
Line-IN-R
2
8.2_0402_1%
RA56
1
2
1
1
3
HPOUT-R
2
LA10 2
2
JHP
EMI@
BLM15PX330SN1D 0402
EMI@
BLM15PX330SN1D 0402
EMI@
CHILISIN NBQ160808T-800Y-N 0603
EMI@
CHILISIN NBQ160808T-800Y-N 0603
1
Line-IN-L
LA7
RING2
+5VS
A_MIC_CLK
1
1
HPOUT-L
MIC_IN
@
RA4
Close to UA1
Pin11,13,14,16
iPhone and Nokia type Combo Jack
RA55
8.2_0402_1%
1
2
LA1 EMI@
1
2
BLM15BB221SN1D_2P
SM01000BV00
need CIS symbol
CA69 @
MIC_IN
D
2
10K_0402_5%
1
@
1
RA1111
0_0603_1%
2
1 CA24
2
2.2U_0603_6.3V6K
RA5
470K_0402_5%
1
2
2
<31>
NC
1
RA81
RA6
+MIC2-VREFO
B
F
D
_
@
1
RA1110
0_0603_1%
RA53
A_MIC_DATA
MIC_CLK_C
+RTCVCC
+3VS
+5VS
2
+5VA
2
3
48
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
SPDIF-OUT/GPIO2
MIC2-VREFO
MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
MIC_CAP
100P_0402_50V8J 2
PCH_AZ_CODEC_RST#
2
2
+5V_PVDD
INT-SPK-L+
INT-SPK-LINT-SPK-R+
INT-SPK-R-
MIC_CLK_C
5
2 0_0402_5%
JACK_PLUG#
MONO-OUT
PC_BEEP
QA6B
DMN66D0LDW-7_SOT363-6
@
Reserve for cancel Delay circutis
ALC3234-CG_MQFN48_6X6
B
1
SDATA-IN
1
2 100K_0402_5%
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
RA9
D
@
QA5A
DMN66D0LDW-7_SOT363-6
2
47
EC_MUTE#
RA12 1
CA62 1
CA63 1
CA64 1
+3VS
JACK_SENSE#
@
CA2
2 10U_0603_6.3V6M
2
3
+A_VCC
EC_MUTE#
HPOUT-L
HPOUT-R
2 100K_0402_5%
@
CA1
10U_0603_6.3V6M
2 0_0402_5%
AZ5125-02S.R7G_SOT23-3
20
32
33
RA13 1
1
2
@
JACK_SENSE#
+CODEC_AVDD2
RA8
1
29
17
18
19
13
14
15
+1.5VS
3
16
+MIC2-VREFO
RING2
MIC_IN
2
1
MIC1-L
10U_0603_6.3V6M CA74
+MIC2-VREFO
@EMI@
RA1112
0_0402_5%
2
@
RA2
100K_0402_5%
3
HP/LINE1 JD(JD1)
MIC2/LINE2 JD(JD2)
SPDIFO/FRONT JD(JD3)/GPIO3
SYNC
+3VS
AZ5125-02S.R7G_SOT23-3
21
22
30
31
23
24
SDATA-OUT
CPVDD
2
PCH_AZ_CODEC_RST#
JACK_PLUG#
1
11
@
QA5B
DMN66D0LDW-7_SOT363-6
1
2
2
@
RA3
10K_0402_5% 1
1
Reserve for HDA issue
1000P_0402_50V7K
8
36
41
46
CPVDD
PVDD1
PVDD2
BCLK
+A_VCC
1
4
2
0
1
@
RA1
100K_0402_5%
DVDD-IO
1000P_0402_50V7K
EMI@ CA32
2
22_0402_5%
+CODEC_AVDD2
CA61
4.7U_0603_6.3V6K
2
1000P_0402_50V7K
EMI@ CA31
10
1
RA130
26
40
AVDD1
AVDD2
EMI@ CA29
PCH_AZ_CODEC_SDIN0
DVDD
1000P_0402_50V7K
EMI@ CA30
PCH_AZ_CODEC_SYNC
<8>
LINE1-R
LINE1-L
Line1-VREFO-R
Line1-VREFO-L
PCH_AZ_CODEC_BITCLK
Line-IN-L
Line-IN-R
G
<8>
<30>
2
1K_0402_1%
2
1K_0402_1%
S
5
2
0_0402_5%
1
RA80
1
RA82
D
PCH_AZ_CODEC_SDOUT
1
RA11
2
+3VS
G
2
<8>
+RTCVCC
2
+3VS
S
9
6
2
0_0402_5%
LINE1-L
CA67 1
4.7U_0603_6.3V6K
LINE1-R
CA68 1
4.7U_0603_6.3V6K
JACK_PLUG Delay circutis
RA166
4.7K_0402_5%
D
1
UA1
1
CA60
0.1U_0402_16V7K
PCH_AZ_CODEC_BITCLK
1
RA10
2
CA55
4.7U_0603_6.3V6K
1
<8>
+3VALW
2
CA56
0.1U_0402_16V7K
1
CA53
4.7U_0603_6.3V6K
CPVDD
CA59
4.7U_0603_6.3V6K
2
C
2
2
1
1
5
+3VS
<8>
1
1
CA54
0.1U_0402_16V7K
2
2
2
CA71
4.7U_0603_6.3V6K
1
CA51
0.1U_0402_16V7K
CA59 CA60 close
to UA1 pin9
1
CA57
4.7U_0603_6.3V6K
CA58
0.1U_0402_16V7K
D
2
Line1-VREFO-L
Line1-VREFO-R
+5V_PVDD
RA165
4.7K_0402_5%
1
+3VS
1
+5V_PVDD
1
+5VA
1
1
CA71, CA51 place close to Pin 26
CA57,CA58 close
to UA1 pin1
2
CA53, CA55 change Value
from 10U_0603_6.3V6M~D to
4.7U_0603_6.3V6K
1
5
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3
2
Audio Codec ALC3234
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
22
of
56
5
4
3
2
1
D
B
F
D
_
C
B
t
n
e
d
i
f
n
o
C
A
l
ia
@
4
2
0
1
C
S
K
r
fo
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
D
3
2
Reserved Page
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
23
of
56
5
4
3
2
1
USB connector1
USB20 port0
USB30 port1
+5VALW
USB3RN1_JUSB1
2
USB3RN1_JUSB1_R
1
2
CI12
4.7U_0805_10V4Z
1
1
2
2
CI14
2.0A
0.1U_0402_16V7K
D
+5V_USB_PWR1
USB3RP1_JUSB1
3
1
2
3
4
USB3RP1_JUSB1_R
S COM FI_ CHILISIN CMMI21T-670Y-N
USB_EN#
1
CI13
@
LI3
<12>
USB3TN1_JUSB1
USB3TN1_JUSB1 2
CI3
1 USB3TN1_JUSB1_C
0.1U_0402_10V7K
1
<12>
USB3TP1_JUSB1
USB3TP1_JUSB1 2
CI4
1 USB3TP1_JUSB1_C
0.1U_0402_10V7K
4
EMI@
2
USB3TN1_JUSB1_R
3
USB3TP1_JUSB1_R
4
2
GND
EN
3
<12>
USB20_JUSB1_P0
C
4
USB20_JUSB1_P0
2
2
2
2
USB3RN1_JUSB1_R
USB3RP1_JUSB1_R
@
ESD@
DI1
USB20_JUSB1_N0_R
3
4
3
WCM-2012HS-900T_4P
2
B
F
D
_
USB_OC0#
EMI@
LI2
1
220U_6.3V_M
1
OUT
IN
SY6288D20AAC_SOT23-5
1
0.1U_0402_16V7K
1
1
2
3
4
5
6
7
8
9
USB20_JUSB1_N0_R
USB20_JUSB1_P0_R
USB3TN1_JUSB1_R
USB3TP1_JUSB1_R
DI2
OCB
USB20_JUSB1_N0
1
+
CI1
+5V_USB_PWR1
5
USB20_JUSB1_N0
CI15
UI5
USB_EN#
<12>
1
AP2301MPG-13_MSOP8
2
+5VALW
S COM FI_ CHILISIN CMMI21T-670Y-N
4
2
0
1
D
JUSB1
USB_OC0#
1
0.1U_0402_16V7K
2
+5V_USB_PWR1
80mil
CI2
0.1U_0402_16V7K
USB_EN#
VOUT
VOUT
VOUT
FLG
8
7
6
5
CI40
10U_0603_6.3V6M
<25,30>
GND
VIN
VIN
EN
9
<12>
4
USB3RP1_JUSB1
EPAD
UI3
3
1
USB3RN1_JUSB1
47U_0805_6.3V4Z
2
<12>
EMI@
USB3RN1_JUSB1_R
1
10
USB3RN1_JUSB1_R
USB3RP1_JUSB1_R
2
9
USB3RP1_JUSB1_R
USB3TN1_JUSB1_R
4
7
USB3TN1_JUSB1_R
USB3TP1_JUSB1_R
5
6
USB3TP1_JUSB1_R
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
GND
GND
GND
GND
10
11
12
13
TAITW_PUBAU6-09FLBS1NN4H0
CONN@
L30ESDL5V0C3-2_SOT23-3
ESD@
1
CI18
LI1
C
3
USB20_JUSB1_P0_R
8
IP4292CZ10-TBR_XSON10_2.5X1~D
+5VALW
3
USB3RP2_JUSB2_R
B
1 USB3TN2_JUSB2_C
0.1U_0402_10V7K
1
2
USB3TP2_JUSB2
USB3TP2_JUSB2 2
CI11
1 USB3TP2_JUSB2_C
0.1U_0402_10V7K
4
3
S COM FI_ CHILISIN CMMI21T-670Y-N
EMI@
LI5
<12>
USB20_JUSB2_N1
<12>
USB20_JUSB2_P1
USB20_JUSB2_P1
A
4
1
2
2
3
4
3
WCM-2012HS-900T_4P
USB3TN2_JUSB2_R
r
fo
2.0A
0.1U_0402_16V7K
+5V_USB_PWR2
UI2
1
2
3
4
1
GND
VIN
VIN
EN
CI26
@
2
8
7
6
5
VOUT
VOUT
VOUT
FLG
80mil
+5V_USB_PWR2
USB_OC0#
1
USB_OC0#
CI17
1
AP2301MPG-13_MSOP8
2
B
JUSB2
<12>
CI8
0.1U_0402_16V7K
220U_6.3V_M
1
+
2
2
1
2
CI9
0.1U_0402_16V7K
USB3TN2_JUSB2 2
CI10
1
CI7
CI43
10U_0603_6.3V6M
EMI@
USB3TN2_JUSB2
USB20_JUSB2_N1
2
0.1U_0402_16V7K
<12>
t
n
e
d
i
f
n
o
C
LI6
1
USB_EN#
S COM FI_ CHILISIN CMMI21T-670Y-N
<12>
l
ia
2
USB3RN2_JUSB2_R
USB3RP2_JUSB2_R
USB3TN2_JUSB2_R
USB3TP2_JUSB2_R
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
GND
GND
GND
GND
10
11
12
13
TAITW_PUBAU6-09FLBS1NN4H0
CONN@
DI5
USB3TP2_JUSB2_R
L30ESDL5V0C3-2_SOT23-3
+5V_USB_PWR2
+5VALW
ESD@
UI6
5
USB_EN#
4
OUT
IN
GND
EN
OCB
1
2
3
USB_OC0#
ESD@
DI4
SY6288D20AAC_SOT23-5
USB3RN2_JUSB2_R
1
10
USB3RN2_JUSB2_R
USB3RP2_JUSB2_R
2
9
USB3RP2_JUSB2_R
USB3TN2_JUSB2_R
4
7
USB3TN2_JUSB2_R
USB3TP2_JUSB2_R
5
6
USB3TP2_JUSB2_R
USB20_JUSB2_N1_R
USB20_JUSB2_P1_R
3
8
A
IP4292CZ10-TBR_XSON10_2.5X1~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
1
2
3
4
5
6
7
8
9
USB20_JUSB2_N1_R
USB20_JUSB2_P1_R
3
USB3RP2_JUSB2
4
1
2
USB3RP2_JUSB2
USB3RN2_JUSB2_R
USB connector2
USB20 port0
USB30 port1
1
<12>
USB3RN2_JUSB2
2
EPAD
<12>
4.7U_0805_10V4Z
EMI@
1
9
CI6
LI4
USB3RN2_JUSB2
S
K
4
3
2
USB3.0
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
1
Sheet
24
of
56
5
4
3
2
1
+5VALW
CI44
4.7U_0805_10V4Z
1
2
4
2
0
1
IO to MB CONN
Substitute:SP01001FS00
D
1
2
CI45
JIO
2.0A
0.1U_0402_16V7K
+5V_USB_PWR3
+5V_USB_PWR3
USB_EN#
1
C
CI46
@
0.1U_0402_16V7K
2
GND
VIN
VIN
EN
9
USB_EN#
1
2
3
4
EPAD
UI4
<24,30>
8
7
6
5
VOUT
VOUT
VOUT
FLG
80mil
+3VS
USB_OC1#
1
USB_OC1#
2
B
F
D
_
0.1U_0402_16V7K
+5V_USB_PWR3
USB_EN#
4
OUT
IN
GND
EN
OCB
1
2
3
USB_OC1#
SY6288D20AAC_SOT23-5
B
<12>
<12>
t
n
5
e
d
i
f
n
o
C
4
<12>
<12>
l
ia
USB20_JUSB3_P2
USB20_JUSB3_N2
r
fo
USB20_CR_P6
USB20_CR_N6
4
1
1
USB20_JUSB3_P2_R
USB20_JUSB3_N2_R
17
18
1
2
2
1
2
2
C
GND
GND
+5VS
+5VALW
LED/B TO M/B
SP01001A900
USB20_JUSB3_P2_R
B
JLED
USB20_JUSB3_N2_R
<30>
<30>
WCM-2012HS-900T_4P
3
4
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ACES_51524-0160N-001
CONN@
+3VALW_EC
WCM-2012HS-900T_4P
3
4
3
LI7
EMI@
4
@
USB20_CR_P6_R
USB20_CR_N6_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S
K
UI7
5
<12>
CI47
AP2301MPG-13_MSOP8
+5VALW
A
D
LID_SW#
BATT_LOW_LED#
BATT_CHG_LED#
SATA_ACT#
<30>
LID_SW#
BATT_LOW_LED#
BATT_CHG_LED#
<8>
SATA_ACT#
USB20_CR_P6_R
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
G1
G2
9
10
ACES_51524-0080N-001
CONN@
USB20_CR_N6_R
LI8
EMI@
A
Compal Secret Data
Security Classification
Issued Date
2014/03/26
Deciphered Date
2015/03/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3
2
IO/B, LED/B
Document Number
Rev
0.1
LA-B016P
Monday, October 20, 2014
Sheet
1
25
of
56
