The complete verilog book

THE COMPLETE VERILOG BOOK
THE COMPLETE VERILOG BOOK
by
Vivek Sagdeo
Sun Micro Systems, Inc.
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-47658-4
Print ISBN: 0-7923-8188-2
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©1998 Kluwer Academic Publishers
A
ll rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
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Created in the United States of America
Visit Kluwer Online at:
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ordrecht
CD-ROM available only in print edition.
To
My Parents,
Sons-Parth and Nakul,
Anjali,
Friends
LIST OF FIGURES
8
14
14

15
17
25
45
64
68
82
86
91
93
93
94
94
95
136
217
222
223
230
245
246
247
248
248
291
313
317
Figure 1-1.
Figure 1-2.
Figure 1-3.

Figure 1-4.
Figure 1-5.
Figure 2-1.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 6-1.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 14-1.
Figure 16-1.
Figure 17-1.
Block Diagram of a System with Processor, Main Memory, and Cache
Bottom-up Methodology and Verilog Language Features Support
Top-Down Methodology and Equivalent Verilog Language

Features Support
Typical Design Flow with Verilog
Verilog Keywords
Tables of Net Types and Resolution Functions
Tables of Operators in Verilog Used for Evaluating Expressions
Schematics for the Adder in Example 3-28
Top Level Block Diagram of r4200
UltraSPARC-IIi Block Diagram
Schematics for Example 4-1
Network Data Structure for the andor Verilog Model in Example 4-1
Schedule of Events for a Verilog Model
Algorithm for Verilog Model Execution
Algorithm for Processing an Event
Order of Events at a Time and Event Structure Diagrams
Algorithm for Scheduling an Event
Tables for
Each Built-in Gate in Verilog
State Diagram for Cache Controller with Write-Back Policy
Block Diagram for the Cache Controller with Write-Back Policy
Containing Dirty Bits
State Transition Diagram for the Cache Controller with
Write-Back Policy
Block Diagram for a Cache System
Typical Design Flow with Verilog Including Synthesis
Logic Synthesis Components of Verilog Based Synthesis
Components of Behavioral Synthesis with Verilog
Traditional View (Class A or Mealy Machine) of a Sequential Design
Modern View (Class A – Sagdeo Machine) of a Sequential Design
Sharings Adders Amongst Different Operations in Example 14-1
C Interface Components for Verilog HDL

Schematics for a Static RAM Cell with Bidirectionals and Strengths
PREFACE
The Verilog hardware description language (HDL) provides the ability to
describe digital and analog systems. This ability spans the range from
descriptions that express conceptual and architectural design to detailed
descriptions of implementations in gates and transistors. Verilog was
developed originally at Gateway Design Automation Corporation during the
mid-eighties. Tools to verify designs expressed in Verilog were implemented
at the same time and marketed. Now Verilog is an open standard of IEEE
with the number 1364. Verilog HDL is now used universally for digital
designs in ASIC, FPGA, microprocessor, DSP and many other kinds of
design-centers and is supported by most of the EDA companies. The
research and education that is conducted in many universities is also using
Verilog. This book introduces the Verilog hardware description language and
describes it in a comprehensive manner.
Verilog HDL was originally developed and specified with the intent of use
with a simulator. Semantics of the language had not been fully described
until now. In this book, each feature of the language is described using
semantic introduction, syntax and examples. Chapter 4 leads to the full
semantics of the language by providing definitions of terms, and explaining
data structures and algorithms.
The book is written with the approach that Verilog is not only a simulation
or synthesis language, or a formal method of describing design, but a
complete language addressing all of
these aspects. This book covers many
aspects of Verilog HDL that are essential parts of any design process. It has
the view of original development, and also encompasses changes and
additions in subsequent revisions. The book starts with a tutorial
introduction in chapter 1, then explains the data types of Verilog HDL in
chapter 2. Today´s object-oriented world knows that the language-constructs

and data-types are equally important parts of a programming language.
Chapter 3 explains the three views of a design object: behavioral, RTL and
structural. Each view is then described in detail, including the semantic
introduction, example and syntax for each feature, in chapters 3, 5 and 6.
Verilog takes the divide and conquer approach to the language design by
separating various types of constructs using different syntax and semantics.
The syntax and semantics include features to describe design using the three
levels of abstractions, features for simulation control and debug, preprocessor
features, timing descriptions, programming language interface and
miscellaneous system tasks and functions.
System tasks and functions that are useful for non-design descriptions, such
as input-output, are described in chapters 8 and 10. The preprocessor enables
one to define text substitutions and to include files, which are defined in
chapter 9. The building of systems using all features is explained in chapter
11. Synthesis is an essential part of today´s design process, and Verilog HDL
usage for synthesis requires special language understanding. The
understanding needed is provided in chapters 11 to 13. Timing descriptions
form a separate class of features in Verilog and are described in chapter 15.
Chapter 17 describes how programming language interface (PLI) provides
access to Verilog data structures and simulation information via common
data definitions and routines. Standard Delay Format, which is discussed in
chapter 18, extends capabilities of timing descriptions of specific blocks in
Verilog, and is used in ASIC designs extensively. Chapter 19 enunciates the
analog extensions to Verilog in the form of Verilog-A and Verilog-MS.
Simulation speed is an important part of Verilog HDL usage, and a large part
of the design cycle is spent in design verification and simulation. Some
techniques to enhance this speed are discussed in chapter 20.
The book keeps the reader abreast of current developments in the Verilog
world, such as Verilog-A, cycle simulation, SDF, DCL and uses IEEE 1364
syntax.

I hope that this book will be useful to all of those who are new to Verilog
HDL, to those who want to learn additional facets, and to those who would
like a reference book during the development of a hardware design or
software tool with Verilog HDL. I wish for you to design and implement
some interesting designs of ASICs, FPGAs, microprocessors, caches,
memories, boards, systems and/or tools like simulators, synthesizers, timing
analyzers, formal verifiers with Verilog HDL, and to have a lot of fun doing
so.
Vivek Sagdeo
ACKNOWLEDGEMENTS
A book of this size takes many different things to come together . I would like to
acknowledge Carl Harris of Kluwer for encouragement and for facilitating the creation of
manuscript. Jackie Denfeld handled the creation of final manuscript in a short time well. Tedd
Corman provided the editorial review and my experience of working with him in the past on
simulation and HDLs has been valuable. Satish Soman provided feedback from the design
perspective. UC Berkeley extension provided the teaching environment for me that has added
the academic dimension to this book. Dr Richard Tsina, Joan Siau and Roxanne Giovanetti
from UCB deserve mention for their support. Students of the class “Digital Design of Verilog
HDL” from UCB and PerformancAE kept the book-writing interesting and live. My
coworkers from SUN microsystems have been very cooperative and accomodating and have
really good insight into digital design and microprocessors.
While working at Gateway Design where Verilog was designed and implemented, a terrific
team was in place. Prabhu Goel, Barry Rosales, Manoj Gandhi, Phil Moorby, Ronna Alintuck
and many from Marketing and Sales made this work on Verilog and well-rounded.
Over the several years, experiences of working at Gateway(Cadence), Viewlogic, Silicon
Graphics, Meta Software, Philips Semi and SUN Microsystems and IEEE 1364 have provided
the background to cover many aspects of Verilog including language, digital and analog,
system and microprocessors and have given a perspective that has made this work possible.
I acknowledge all those whose names can’t be mentioned for lack of space but have been part
of various projects with me.

DISCLAIMER
This DISK (CD ROM) is distributed by Kluwer Academic
Publishers with *ABSOLUTELY NO SUPPORT* and *NO
WARRANTY* from Kluwer Academic Publishers.
Use or reproduction of the information provided on this DISK (CD
ROM) for commercial gain is strictly prohibited. Explicit
permission is given for the reproduction and use of this
information in an instructional setting provided proper reference is
given to the original source.
Kluwer Academic Publishers shall not be liable for damage in
connection with, or arising out of, the furnishing, performance or
use of this DISK (CD ROM).
TABLE OF CONTENTS
1. INTRODUCTION TO VERILOG HDL
1
1.1
1.2
1.3
1.4
1.5
1
1
2
2
2
7
8
Language Motivation
1.1.1
1.1.2

1.1.3
Language Design
Verilog World
Accessory Specifications
Tutorial Via Examples
1.2.1
1.2.2
1.2.3
1.2.4
Counter Design
Factorial Generator
System Design with Processor, Memory, and Cache
Cache System - Behavioral Model
Overview of Verilog HDL
1.3.1
1.3.2
1.3.3
1.3.4
Correspondence To Digital Hardware
Typical Design Flow with Verilog
List of Keywords
Comment Syntax
Syntax Conventions
Exercises
2. DATA TYPES IN VERILOG
2.1
2.2
2.3
Overview
Value Systems

Data Declarations
2.3.1
2.3.2
2.3.3
Introduction
Examples
Syntax
2.4
2.5
2.6
Reg Declaration
2.4.1
2.4.2
2.4.3
Introduction
Examples
Syntax
Net Declaration
2.5.1
2.5.2
2.5.3
Introduction
Syntax
Examples
Port Types
2.6.1
2.6.2
2.6.3
Introduction
Examples

Syntax
2.7
Aggregates – 1 and 2 Dimensional Arrays (Vectors and Memories)
2.7.1
2.7.2
2.7.3
Introduction
Examples
Syntax
10
13
13
15
17
17
18
19
21
21
21
22
22
23
23
23
23
24
24
24
24

28
29
29
29
30
30
31
31
31
32
1
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
32
32
32
33
33
33
33
33
33
33

33
34
34
34
34
34
35
35
35
35
35
Delays on Nets
2.8.1
2.8.2
2.8.3
Introduction
Examples
Syntax
Integer and Time
2.9.1
2.9.2
2.9.3
Introduction
Examples
Syntax
Real Declaration
2.10.1
2.10.2
2.10.3
Introduction

Example
Syntax
Event Declaration
Parameter Declarations
Examples
Syntax
Hierarchical Names
2.15.1
2.15.2
2.15.3
Introduction
Examples
Syntax
Exercises
3. ABSTRACTION LEVELS IN VERILOG: BEHAVIORAL, RTL,
AND STRUCTURAL
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.1.1
3.1.2
3.1.3
3.2.1
3.2.2
3.2.3
3.3.1

3.3.2
3.3.3
3.3.4
3.4.1
3.5.1
3.5.2
3.5.3
3.6.1
3.6.2
3.6.3
3.7.1
3.7.2
37
37
37
37
38
39
39
39
40
40
40
41
43
43
43
43
43
43

45
50
51
51
51
53
55
55
55
OVERVIEW
Introduction
Examples
Syntax
Behavioral Abstractions In Verilog
Introduction
Examples
Syntax
Register Transfer Level Abstractions in Verilog
Introduction
Example
Syntax
RTL Descriptions – Other Definitions
Expressions
Overview
Operators in Expressions
Introduction
Examples and Explanations
Operators in Expressions – Syntax
Operands in Expressions
Introduction

Examples and Explanations
Syntax of Operands in Expressions
Special Considerations in Expressions
Constant-Valued Expressions
Operators on Reals
3.7.3
3.7.4
3.7.5
3.7.6
3.8
3.9
3.10
Operator Precedence
Examples of Various Operator Usage
Comparisons With X's and Z’s
Expression Bit Lengths
Syntax for Expressions
Example of Register Transfer Level of Abstraction
Structural Descriptions In Verilog
3.10.1
3.10.2
3.10.3
Structural Constructs – Overview
Structural Constructs - Module Definitions
Structural Constructs – Module Instantiation
3.11 Exercises
4. SEMANTIC MODEL FOR VERILOG HDL
55
56
56

57
57
59
63
63
64
67
83
85
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Introduction
Example
Simulation with Full Analysis
Log of a Typical Simulator
Log of an Ideal Simulator
Analysis and Concepts in Event-Driven Simulation in Verilog
Internal Data Structure Representation
Update and Evaluate Events
Order of Execution of Events in Verilog
Algorithm for Event-Driven Model for Verilog HDL
4.10.1

4.10.2
Definitions
Algorithm
85
86
87
87
88
90
90
90
91
92
92
93
95
95
96
98
4.11
4.12
Highlights of the Algorithm – Concurrent Processes and
Event Cancelations
4.11.1
4.11.2
Concurrent Processes
Event Cancelations
Exercises
5. BEHAVIORAL MODELING
99

99
99
5.1
5.2
5.3
5.4
Overview of Behavioral Modeling
5.1.1
5.1.2
5.1.3
Introduction
Examples
Syntax
Procedural Assignments
5.2.1
5.2.2
5.2.3
5.2.4
Overview
Blocking (Immediate) Procedural Assignments
Non-Blocking Procedural Assignments
Examples Comparing Blocking and Non-Blocking Assignments
Conditional Statement
100
100
101
101
101
102
104

107
107
107
107
107
108
108
108
108
5.3.1
5.3.2
5.3.3
5.3.4
Overview
Examples
Syntax
Special Considerations
Case Statement
54.1
5.4.2
5.4.3
Overview
Examples
Syntax
5.4.4
5.4.5
5.5
5.6
5.7
5.8

5.9
5.10
5.11
5.12
5.13
5.14
5.15
Don't Cares and Case Statements – Casex and Casez
Examples Comparing Case, Casex, and Casez
Loops
5.5.1
5.5.2
5.5.3
Overview
Examples
Syntax
Begin-End Blocks
5.6.1
5.6.2
5.6.3
Introduction
Example
Syntax
Wait Statements
5.7.1
5.7.2
5.7.3
Introduction
Example
Syntax

Event and Delay Controls
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.8.6
Overview
Event Declarations
Multi-Event Event – Event OR
Event Usage
Event Generalization
Generalized Event Transitions
Fork-Join Blocks
5.9.1
5.9.2
5.9.3
5.9.4
Introduction
Examples
Syntax
Special Considerations – Modeling Pipelines
Functions and Tasks
5.10.1
5.10.2
Functions
Tasks
Task Disabling
5.11.1
5.11.2

5.11.3
Introduction
Examples
Syntax
Assign-Deassign Statements
5.12.1
5.12.2
5.12.3
Introduction
Example
Syntax
Force-Release Statements
5.13.1
5.13.2
5.13.3
Introduction
Examples
Syntax
A Behavioral Modeling Example – An Essential Microprocessor
Exercises
6. RTL AND STRUCTURAL MODELING
6.1
6.2
Introduction
Gates
6.2.1
6.2.2
6.2.3
Introduction
Example

List of Gates and Their Functions
109
109
111
111
111
112
112
112
113
113
113
113
113
113
114
114
114
115
115
116
116
117
117
117
118
118
119
119
121

122
122
122
123
123
123
123
124
124
124
124
125
125
132
135
135
135
135
136
136
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.2.4
Syntax for Gates and Switch Declarations

136
138
138
138
138
138
139
139
141
141
141
142
142
142
143
143
143
144
145
145
146
146
146
Switches
6.3.1
6.3.2
Introduction
Syntax
User-Defined Primitives
6.4.1

6.4.2
6.4.3
Introduction
Examples
Syntax
Combinational UDPs
6.5.1
6.5.2
6.5.3
Introduction
Example
Syntax
Level-Sensitive Sequential UDP
6.6.1
6.6.2
6.6.3
Introduction
Example
Syntax
Edge Sensitive Sequential UDPs
Mixed Level and Edge Sensitive Sequential UDPs
UDP Instances
6.9.1
6.9.2
6.9.3
Introduction
Example
Syntax for Primitive Instance
Exercises
7. MIXED STRUCTURAL, RTL, AND BEHAVIORAL DESIGN

7.1
7.2
7.3
7.4
7.5
7.6
151
151
151
152
153
154
154
Introduction
Examples and Scenarios: 1 – Comparing Structural Adder Design
with Behavioral Model
Examples and Scenarios: 2 – System Modeling
Examples and Scenarios: 3 – Adding Behavioral Code to a
Design for Checking
Examples and Scenarios: 4 – Design Cycle and Project Planning
Flexibility
Exercises
8. SYSTEM TASKS AND FUNCTIONS
155
155
156
156
156
157
158

158
159
160
160
160
160
161
8.1
8.2
8.3
8.4
Introduction
Display System Tasks
8.2.1
8.2.2
8.2.3
Overview
Examples
Syntax and Format Details
Monitor System Tasks
8.3.1
8.3.2
8.3.3
Overview
Examples
Syntax
File Management
8.4.1
8.4.2
8.4.3

Overview
Examples
Syntax
8.5
8.6
8.7
8.8
8.9
161
161
161
162
162
162
162
162
163
163
163
165
165
File Input Into Memories
8.5.1
8.5.2
8.5.3
Overview
Example
Syntax
Simulation Time Functions
Simulation Control Tasks

8.7.1
8.7.2
Overview
Examples
Waveform Interface (VCD Files)
8.8.1
8.8.2
8.8.3
Overview
Examples
Syntax
Exercises
9. COMPILER DIRECTIVES
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Introduction
'include
9.2.1
9.2.2
9.2.3
Introduction
Example
Syntax
`define and `undef

9.3.1
9.3.2
9.3.3
Introduction
Examples
Syntax
`ifdef, `else, `endif
9.4.1
9.4.2
Example
Syntax
`default_nettype
9.5.1
9.5.2
Example
Syntax
`timescale
9.6.1
9.6.2
Example
Syntax
`resetall
Exercises
167
167
168
168
168
168
168

168
168
169
169
169
170
170
170
170
170
170
171
171
171
10. INTERACTIVE SIMULATION AND DEBUGGING
10.1
10.2
10.3
10.4
10.5
Introduction
System Tasks and Functions
10.2.1
10.2.2
Previously Covered
Additional Tasks
Commands
Browser Tools
Code Coverage
11.

SYSTEM EXAMPLES
11.1
11.2
11.3
11.4
Introduction
Example 1: 8085 Based System: Sio85.V
Example 2: R4200
Example 3: Cache Design
173
173
173
173
174
174
174
174
177
177
177
183
215
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.6
215
217

222
230
236
242
Cache System: Architecture with State Diagram
Cache System: Behavioral Model with Write-Through Policy
Cache System: Behavioral Model Modified for Write-Back Policy
Cache System: Implementation: Write-Through Policy
Memory Model with Bus Cycle Timing and with Timing Checks
Exercises
12. SYNTHESIS WITH VERILOG
243
12.1
12.2
12.3
12.4
12.5
Logic Synthesis and Behavioral Synthesis
Design Flow with Synthesis
12.2.1 Typical Design Flow with Verilog
Logic Synthesis View
Examples
Exercises
13. VERILOG SUBSET FOR LOGIC SYNTHESIS
243
243
243
247
249
253

255
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.11.1
13.12
13.13
13.14
13.15
13.16
13.17
13.18
13.19
13.20
13.21
13.22
13.23
14. SPECIAL CONSIDERATIONS IN SYNTHESIZING VERILOG
14.1
14.1.1
14. 1.2
14. 1.3

14. 1.4
14. 1.5
14. 1.6
Introduction
Structural Descriptions – Modules
Declarations – Overview
Module Items – Overview
Synthesizing Net Types
Continuous Assignments
Module Instantiations – Parametrized Designs
Structural Descriptions – Gate-Level Modeling
Expressions
Behavioral Modeling for Synthesis
Function Declarations
Data Declarations in Functions – Reg, Input, Memory, Parameter,
and Integers
Behavioral Statements Support for Logic Synthesis – Overview
Procedural Assignments
if Statement
Conditional Assignments
Case Statements
For Loops
Forever Loops
Disable Statements
Task Statements
Always Blocks
Incomplete Event (Sensitivity) Specification
Exercises
255
256

257
257
257
258
258
259
261
262
264
264
265
266
267
268
268
270
272
272
273
274
276
277
279
Inferring Registers
279
279
279
281
282
283

286
Introduction
Latch Inference
Simple Flip-Flop Inference
Modeling Flip-Flops with Resets
Synthesis Checks During Register Inference
Bus Latch
14.2
14.3
14.4
14.5
Multiplexers
287
287
287
288
288
289
290
290
290
292
292
293
293
Three-State Inference
14.3.1
14.3.2
14.3.3
14.3.4

Modeling a Tri-State Gate for Synthesis
Modeling Two Three-State Gates
Registered or Latched Three-State
Three-State with Registered Enable
Designs via Resource Sharing
14.4.1
14.4.2
Introduction
Sharable Resources
Control Flow and Data Flow with Sharing
14.5.1
14.5.2
14.5.3
Data Flow Conflicts
Resource Area
Resource Sharing Methods
15. SPECIFY BLOCKS — TIMING DESCRIPTIONS
295
15.1
15.2
15.3
15.4
Overview
295
295
296
296
297
297
297

298
298
298
298
299
300
300
300
301
301
303
303
304
305
305
305
305
Example
Specify Blocks – Syntax
Timing Checks in Specify Blocks
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
$Setup Timing Check
$Hold

$Width
$Period
$Skew
$Recovery
$Setuphold
Example of Timing Checks
15.5
Module Path (Delay) Declarations
15.5.1
15.5.2
15.5.3
15.5.4
15.5.5
15.5.6
Introduction
Simple Paths
Edge-Sensitive Paths
State-Dependent Paths
Edge-Sensitive State-Dependent Paths
State-Dependent Paths – ifnone Condition
15.6
15.7
15.8
15.9
15.10
Delay Specifications
Mixing Distributed and Specified Delays
Multi-Driver Nets
Pulse Specification
Exercises

16. PROGRAMMING LANGUAGE INTERFACE
307
16.1
16.2
16.3
16.4
16.5
16.6
Overview and Examples
307
308
308
309
309
309
310
311
312
PLI Origin and Use
PLI Function Types
PLI Interface Classes
Interface Definitions
16.5.1
16.5.2
16.5.3
veriuser.h
acc_user.h
vpi_user.h
User Tasks and Functions
16.7

16.8
16.9
16.10
16.11
16.12
Steps Involved in Defining User Tasks/Functions
312
313
313
313
313
313
C Interface Components
Verilog Callbacks – Utility Routines
Verilog Callbacks – Access Routines
Verilog Callbacks – VPI Routines
Exercises
17. STRENGTH MODELING WITH TRANSISTORS
315
17.1
17.2
17.3
17.4
17.5
Overview
315
316
317
319
319

319
320
320
Modeling with Unidirectional Switches – Example
Modeling with Bidirectionals and Strengths – Example
Strength-Levels in Verilog
17.4.1
17.4.2
17.4.3
Overview
Examples of Strength Algebra
Strength Specifications On Gates
Exercises
18.
STANDARD DELAY FORMAT
18.1
18.2
Introduction
SDF Description
18.2.1
18.2.2
18.2.3
Introduction
Syntax
Example
18.3
Header
18.3.1
18.3.2
Introduction

Syntax
18.4
18.5
Header SubParts
Cell Entry
18.5.1
18.5.2
The CELLTYPE entry
The Cell Instance Entry
18.6
Timing Specifications
18.6.1
18.6.2
18.6.3
18.6.4
Delay Type – Absolute
The INCREMENT keyword
The PATHPULSE Entry
The PATHPULSEPERCENT Entry
18.7
Delay Definitions
18.7.1
18.7.2
18.7.3
18.7.4
18.7.5
18.7.6
18.7.7
18.7.8
The Delay Data

Delay Value
The IOPATH Entry
Conditionals
The RETAIN Entry
The PORT Entry
The INTERCONNECT Entry
The DEVICE Entry
Timing Check Entries
The SETUP Entry
The HOLD Entry
The SETUPHOLD Entry
The RECOVERY Entry
The REMOVAL Entry
18.8
18.8.1
18.8.2
18.8.3
18.8.4
18.8.5
321
321
324
324
324
325
325
325
325
325
328

329
329
330
331
331
332
333
333
334
335
336
337
338
339
339
340
341
344
344
345
345
346
18.8.6
18.8.7
18.8.8
18.8.9
18.8.10
The RECREM Construct
The SKEW Entry
The WIDTH Entry

The PERIOD Entry
The NOCHANGE Entry
18.9
Timing Environment and Constraints
18.9.1
18.9.2
18.9.3
18.9.4
18.9.5
The PATHCONSTRAINT Entry
The PERIODCONSTRAINT Construct
The SUM Entry
The DIFF Constraint
The SKEWCONSTRAINT Entry
18.10
Timing Environment – Information Entries
18.10.1
18.10.2
18.10.3
18.10.4
The ARRIVAL Construct
The DEPARTURE Construct
The SLACK Construct
The WAVEFORM Construct
18.11
18.12
SDF File Examples
Delay Model
18.12.1
18.12.2

18.12.3
Introduction
The List of Delay Models
Rules for the Delay Model
18.13
18.14
DCL – New Emerging Standard
OMI Standard
19.
VERILOG-A AND VERILOG-MS
19.1 Analog Module
19.1.1
19.1.2
19.1.3
Introduction
Examples
Syntax
19.2
Analog Data Declarations
19.2.1
19.2.2
19.2.3
Introduction
Examples
Syntax
19.3 Analog Behavioral Descriptions
19.3.1
19.3.2
19.3.3
Introduction

Examples
Syntax
19.4
19.5
Expressions in Analog Assignments
Mixed Signal Designs in Verilog
20.
SIMULATION SPEEDUP TECHNIQUES
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
Cycle-Based Simulation
2-State Versus 4-State Simulations
Compiled, Native Code, and Interpretive Simulations
Parallel Processors and Multi-Threaded Simulators
Usage of Caches and Other Memory to Achieve Speedup
Distributed Simulations Over a Network of Workstations
C Code Versus HDL Code
File Management in Simulation
347
347
348
348
349
350

350
351
352
352
353
353
354
354
355
357
359
360
360
361
361
362
363
365
365
365
365
366
366
366
366
366
367
367
367
367

368
368
371
371
372
372
372
373
373
373
374
A.
FORMAL SYNTAX DEFINITION FOR VERILOG HDL
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
B.
VERILOG SUBSET FOR LOGIC SYNTHESIS
B.1
B.2
B.3
Introduction
Syntax for Verilog for Logic Synthesis
Ignored Constructs for Logic Synthesis

B.3.1
B.3.2
B.4
B.4.1
B.5
Source Text
Declarations
Primitive Instances
Module Instantiations
UDP Declaration and Instantiation
Behavioral Statements
Specify Section
Expressions
General
Compiler Directives
Verilog System Functions
Unsupported Verilog Language Constructs
Unsupported Definitions and Declarations
Verilog Keywords Set for Logic Synthesis
C.
PROGRAMMING LANGUAGE INTERFACE (PLI), HEADER FILE –
veriuser.h
D.
PROGRAMMING LANGUAGE INTERFACE (PLI) HEADER FILE –
acc_user.h
E.
PROGRAMMING LANGUAGE INTERFACE (PLI), HEADER FILE –
vpi_user.h
F.
FORMAL SYNTAX DEFINITION OF SDF

G.
LIST OF EXAMPLES
H.
REFERENCES
INDEX
375
376
377
379
380
381
383
385
390
392
395
395
395
403
403
403
403
403
404
407
419
431
445
451
457

459
1
INTRODUCTION TO VERILOG HDL
1.1 Language Motivation
1.1.1 Language Design
The complexity of hardware design has grown exponentially in the last decade. The
exponential growth is fueled by new advances in design technology as well as the
advances in fabrication technology. The usage of hardware description language to
model, simulate, synthesize, analyze, and test the design has been a cornerstone of
this rapid development. Verilog is the first hardware description language that was
designed to be the language of choice in this domain. It is designed to enable
descriptions of complex and large designs in a precise and succinct manner. It can
facilitate descriptions of advances in architectures of design such as pipelining, cache
management, branch predictions. A smooth top-down design flow is possible with
Verilog based designs. It is also designed to facilitate new ECAD technologies such
as synthesis and formal verification and simulation. It was designed to unify design
process (including behavioral, rtl, gates, stimulus, switches, user-interface, test-
benches, and unified interactive and batch modes). It is designed to leverage
advances in software development for hardware design.
1.1.2 Verilog World
Verilog HDL has been successfully applied in all the major accomplishments in the
field of digital design in the last decade. It is a language that is today IEEE standard
1364, is open and has activities under Open Verilog International umbrella, has
annual International Verilog Conference (IVC) and is used in a vast majority of
electronics and computer industry projects as well as research in academics in areas
such as formal verification and behavioral synthesis. It also has spawned an industry
2
Chapter 1
of CAD tool vendors and consulting/support experts creating a movement to
participate in the world of electronics today.

1.1.3 Accessory Specifications
Verilog's accessory specifications such as the Programming Language Interface and
the Standard Delay Format (SDF) enable a highly productive design management
environment. Verilog HDL is a powerful tool to add to the repertoire of anybody
involved with designing circuits in digital and now analog domains.
1.2 Tutorial Via Examples
In the following pages of Chapter 1, we will take examples of circuits and see their
Verilog descriptions. This will give us a quick tour of the hardware description
language which is explained fully in the following chapters along with the digital
design techniques developed with Verilog.
1.2.1
Counter Design
Traditionally a counter is designed with flip-flops and gates. The flip-flops in turn
are designed with gates. To test the counter we connect clock and reset signals.
Verilog retains the capability of describing structural level descriptions, as shown
below, and adds the register transfer level and the behavioral capabilities over
traditional methods of design. These abstraction capabilities can be seen in the
following models and in comparing the traditional methods versus the Verilog
approach.
Example 1-1 describes the gate-level description of a D edge-triggered flip-flop.
The schematics are shown in Example 1-3.
module d_edge_ff_gates(q, qBar, preset, clear, clock, d);
inout q, qBar;
input clock, d, preset, clear;
nand #1 nl (ol, preset, o4, o2),
n2 (o2, clear, clock, ol),
n3 (o3, clock, o2, o4),
n4 (o4, d, o3, clear),
n5 (q, preset, o2, qBar),
n6 (qBar, q, o3, clear);

endmodule
Example 1-1.
A gate-level description of edge-sensitive d flip-flop.
module counter(q, clock, preset, clear);
output [3:0] q;
input clock, preset, clear;
d_edge_ff_gates dffl(q[0], qBar0, preset, clear, clock, qBar0),
dff2(q[l], qBarl, preset, clear, qBar0, qBarl),
INTRODUCTION TO VERILOG HDL
3
dff3(q
[2], qBar2, preset, clear, qBarl, qBar2),
dff4(q[3], qBar3, preset, clear, qBar2, qBar3);
// initial $monitor("Internal counter signals qb0=%d qbl=%d qb2=%d qb3=%d",
// qBar0, qBar1, qBar2, qBar3);
endmodule
Example 1-2.
A 4-bit counter built using instances of d flip-flop defined in
Figure 1-1.
Example 1-3
.
Schematics for dff in 1-1.
Example 1-4.
Schematic for counter in 1-2.
4
Chapter 1
The description in Example 1-1 begins with the word “module” and ends with the
word “endmodule”. The interface to the module is described in the same line as
module name “d_edge_ff_gates”. The direction of each port in the interface list is
described in the following lines beginning with the words like “inout” and “input”.

The “nand” statement has six instances of nand gates with names nl through n6.
The interface list on each line enclosed in parentheses. The first identifier describes
the output and the subsequent identifiers describe the inputs of each nand gate. Thus,
ol through o4 and q and qBar are outputs of the gates nl through n6; preset, clear,
clock and data are inputs along with ol-o4, q and qBar which are in the feedback
loop. The “#” symbol indicates delay on the gate which is a unit delay (1 unit) in this
case.
Example 1-2 builds a 4-bit counter built with d flip-flops defined in Example 1-1.
The flip-flop was built using predefined nand gate while the counter is built
hierarchically using a module defined earlier. Again, the definition of this block is
enclosed between the keywords “module” and “endmodule” and the interface list is
described at the top of the module. The four flip-flops are instantiated using the
name of the module “d_edge_ff_gates” followed by names (dffl-dff4) and the
connection list.
The definition of the counter output q specifies the 4-bit output by using [3:0]
expression. This indicates the size of this bit-vector of size 4 and indices from 3
down to 0. Verilog supports single-bit quantities or scalars and multi-bit or vectors.
Bits in Vectors are addressed using brackets, as in q[0] indicating bit 0 is vector q.
module counter_behav(q, clock, preset, clear);
output [3:0] q;
reg
[3:0]
q;
input clock, preset, clear;
always @(posedge clock)
begin
if( (preset = = 1) && (clear = = 1))
q =q + l;
else
if ((preset = = 0) && (clear = = 1))

q = 4'bllll;
else
q = 0;
end
endmodule
Example 1-5
.
Behavioral description of the same counter as in 1-2.
In the Example 1-5, the same counter is described at a higher level of abstraction,
known as behavioral level. Here there are no flip-flops or gates, but an always block,
that is sensitive to “posedge”, a positive or rising clock edge. Inside this block, we
see that the count increments by one (“q=q+l”) when preset and clear are inactive
INTRODUCTION TO VERILOG HDL
5
(both 1). The preset and clear actions are modeled in the next two statements
whereby q is set to 4’b1111 or 0 under right combinations for preset and clear values.
The always block executes as a loop with ‘@’ symbol indicating a wait on the
event described in the expression that follows; in this case the ‘posedge clock’ or
rising edge of clock. Another name used for such a loop is ‘process’. In a
synchronous system, several processes that execute based on clock-edges and resets
can describe the synchronous behavior fully.
module test_counter;
reg preset, clear, clock, data;
wire [3:0] q;
counter ci(q, clock, preset, clear);
counter_behav ci(q, clock, preset, clear);
initial
begin
clock = 0;
forever #50 clock = ~clock;

end
initial
begin
$monitor("time=%d preset=%d clear=%d clock=%d q[0]=%d q[l]=%d
q[2]=%dq[3]=%d",
$time, preset, clear, clock, q[0], q[l], q[2], q[3]);
preset = 0;
clear = 1;
#200
/* preset = 1;
clear = 0;
*/ #200
preset = 1;
clear = 1;
#200 ;
#200
data = 0;
#1600
$finish;
end
endmodule
Example 1-6.
A test module for testing the two descriptions of counter and
their equivalence.
Here, in Example 1-6, a test-bench is built by instantiating the two modules and
with two initial blocks. The 'counter' module, with gate-level description, and
counter-behav, with behavioral description, are connected to the same inputs, and
their outputs are connected together. The first initial block generates clock. The
second initial block generates stimulus. It also monitors changes in inputs or outputs