VLSI Combinational Circuit Design

9/25/13
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VLSI Combinational Circuit Design
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Hanoi University of Science and Technology
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SSI, MSI and LSI
“off-the-shelf” parts
VLSI Application-specific
integrated circuit (ASIC)
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An example of the “off-the-shelf” parts design
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Designing with “off-the-shelf” parts
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VLSI ASIC design
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Full-custom design (1)
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Full-custom design (2)
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Semi-custom design
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Standard cell based design (1)
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Basic process standard cell based design
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[,"-S,"&$!&;1".4:0($%,()',)& Synthesis
Translate HDL descriptions into logic gate networks in a particular library
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•  Logic optimization transforms current gate-level
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suitable for technology mapping.
•  Technology mapping transforms the gate-level
network into a netlist of gates (from library) which

minimizes total cost.
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CMOS AND-OR-Invert Gate*
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Netlist of gates (from library)
which minimizes total cost.
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Original netlist
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Netlist of gates (from library)
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Original netlist
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Sea of gates
Cell
I/O buffer
Fixed transistor
layer
Customized
metal layer for

connecting gate
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+ A gate array or uncommitted logic array (ULA) circuit is prefabricated
with a number of unconnected logic gates (cells).
+ CMOS transistors with fixed length and width are placed at regular
predefined positions and manufactured on a wafer, usually called a
master slice ( sea of gates).
+ Creation of a circuit with a specified function is accomplished by
adding a final surface layer or layers of metal interconnects to the chips
on the master slice late in the manufacturing process, joining these
elements to allow the function of the chip to be customized as desired
 reducing the designing time
 reducing the mask costs
+ Disadvantages
- slow clock speed
- wasted chip area
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Based on programmable devices:
The interconnection layers are personalized by electronic means for a
specific application. This work usually can be done by end-users.
F0 = A’B’+ AC’
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F3 = AC + B
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+ Fuse
+ Antifuse
+ Switch
+ Volatile
+ Non-volatile
+ One Time Programmable
+ Reprogrammable (Memory-based)
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•  Simple Programmable Logic Device:
+ Programmable read only memory (PROM)
+ Field Programmable logic array (FPLA or PLA)
+ Programmable array logic (PAL)
+ Generic array logic (GAL)
•  Complex programmable logic device (CPLD)
•  Field programmable gate array (FPGA)
•  Field programmable interconnect (FPIC)
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AND
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Product
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Sum
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Feedback terms
Inputs
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