vlsi design course lecture notes ch6

ECE 410, Prof. A. Mason Lecture Notes 6.1
Intrinsic Silicon Properties
• Read textbook, section 3.2.1, 3.2.2, 3.2.3
• Intrinsic Semiconductors
– undoped (i.e., not n+ or p+) silicon has
intrinsic
charge
carriers
– electron-hole pairs are created by thermal energy
– intrinsic carrier concentration ≡ n
i
= 1.45x10
10
cm
-3
,
at room temp.
– function of temperature:
increase or decrease with temp?
– n = p = n
i
, in intrinsic (undoped) material
•n ≡ number of electrons, p ≡ number of holes
– mass-action law, np = n
i
2
• applies to undoped and doped material
ECE 410, Prof. A. Mason Lecture Notes 6.2
Extrinsic Silicon Properties
•doping, adding dopants to modify material properties
– n-type = n+, add elements with extra an electron

• (arsenic, As, or phosphorus, P), Group V elements
•n
n
≡ concentration of electrons in n-type material
•n
n
= N
d
cm
-3
, N
d
≡ concentration of donor atoms
•p
n
≡ concentration of holes in n-type material
•N
d
p
n
= n
i
2
, using mass-action law
– always a lot more n than p in n-type material
– p-type = p+, add elements with an extra hole
• (boron, B)
•p
p
≡ concentration of holes in p-type material

•p
p
= N
a
cm
-3
, N
a
≡ concentration of acceptor atoms
•n
p
≡ concentration of electrons in p-type material
•N
a
n
p
= n
i
2
, using mass-action law
– always a lot more p than n in p-type material
–if both N
d
and N
a
present, n
n
= N
d
-N

a
, p
p
=N
a
-N
d
do example on board
n
i
2
= 2.1x10
20
n+/p+ defines region
as heavily doped,
typically ≈ 10
16
-10
18
cm
-3
less highly doped regions
generally labeled n/p
(without the +)
P
P
+
+
-
group V

element
ion
electro
n
n-type Donor
free
carrier
B
B
+
+
-
group III
element
hole
p-type Acceptor
ion
free
carrie
r
ECE 410, Prof. A. Mason Lecture Notes 6.3
Conduction in Semiconductors
• doping provides free charge carriers, alters conductivity
• conductivity, σ, in semic. w/ carrier densities n and p
– σ = q(μ
n
n + μ
p
p), q ≡ electron charge, q = 1.6x10
-19

[Coulombs]
• μ≡mobility [cm
2
/V-sec], μ
n
≅ 1360, μ
p
≅ 480 (typical values)
• in n-type region, n
n
>> p
n
– σ≈qμ
n
n
n
• in p-type region, p
p
>> n
p
– σ≈qμ
p
n
p
• resistivity, ρ = 1/σ
• resistance of an n+ or p+ region
–R = ρ
l ,
A =
wt

• drift current (flow of charge carriers in presence of an electric field, E
x
)
– n/p drift current density: Jxn = σ
n
E
x
= qμ
n
n
n
E
x
, Jxp = σ
p
E
x
= qμ
p
p
p
E
x
– total drift current density in x direction Jx = q(μ
n
n + μ
p
p) E
x
= σ E

x
mobility = average velocity per
unit electric field
μ
n
> μ
p
electrons more mobile than holes
⇒conductivity of n+ > p+
l
t
w
A
Mobility often
assumed constant
but is a function of
Temperature and Doping
Concentration
ECE 410, Prof. A. Mason Lecture Notes 6.4
pn Junctions: Intro
• What is a pn Junction?
– interface of p-type and
n-type semiconductor
– junction of two materials forms a diode
• In the Beginning…
– ionization of dopants
at material interface
• Diffusion -movement of charge to regions of lower concentration
– free carries diffuse out
– leave behind immobile ions

– region become depleted of
free carriers
– ions establish an electric field
• acts against diffusion
donor ion and electron free carrier
acceptor ion and hole free carrier
p-type
hole diffusion
hole current
electron diffusion
electron current
N acceptors/cm
A
3
N donors/cm
D
3
n-type
-
+
-
+
-
+
-
+
-
+
-
+

-
+
-
+
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
E
depletion region
immobile acceptor ions
(negative-charge)

immobile donor ions
(positive-charge)
electric field
x
p
W
x
n
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
p-type
N acceptors/cm
A
3
N donors/cm
D

3
n-type
p-type Si wafer
pn diode
junction
depletion region
boundaries
dielectric
insulato
(oxide)
contact
to p-side
contact
to n-side
p+
n+
n “well”
r
p-type n-type
ECE 410, Prof. A. Mason Lecture Notes 6.5
pn Junctions: Equilibrium Conditions
• Depletion Region
– area at pn interface
void of free charges
– charge neutrality
• must have equal charge on both sides
•q A x
p
N
A

= q A x
n
N
D
, A=junction area; x
p
, x
n
depth into p/n side
• ⇒ x
p
N
A
= x
n
N
D
• depletion region will extend further into the more lightly doped side
of the junction
• Built-in Potential
– diffusion of carriers leaves behind immobile charged ions
– ions create an electric field which generates a built-in potential
•where V
T
= kT/q = 26mV at room temperature
E
depletion region
immobile acceptor ions
(negative-charge)
immobile donor ions

(positive-charge)
electric field
x
p
W
x
n
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
p-type
N acceptors/cm
A
3
N donors/cm
D
3

n-type
N
A
N
D
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=Ψ
2
0
ln
i
DA
T
n
NN
V
ECE 410, Prof. A. Mason Lecture Notes 6.6
pn Junctions: Depletion Width
• Depletion Width
use Poisson’s equation & charge neutrality
–W = x
p
+ x

n
•where V
R
is applied reverse bias
• One-sided Step Junction
–if N
A
>>N
D
(p+n diode)
• most of junction on n-side
–if N
D
>>N
A
(n+p diode)
• most of junction on p-side
E
depletion region
immobile acceptor ions
(negative-charge)
immobile donor ions
(positive-charge)
electric field
x
p
W
x
n
-

-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
p-type
N acceptors/cm
A
3
N donors/cm
D
3
n-type
N
A
N
D
⎟
⎟
⎠

⎞
⎜
⎜
⎝
⎛
=Ψ
2
0
ln
i
DA
T
n
NN
V
()
()
2
1
0
2
⎥
⎦
⎤
⎢
⎣
⎡
+
+Ψ
=

ADA
DR
p
NNqN
NV
x
ε
()
()
2
1
0
2
⎥
⎦
⎤
⎢
⎣
⎡
+
+Ψ
=
ADD
AR
n
NNqN
NV
x
ε
()

2
1
0
2
⎥
⎦
⎤
⎢
⎣
⎡
+
+Ψ
=
AD
AD
R
NN
NN
q
V
W
ε
()
2
1
0
2
⎥
⎦
⎤

⎢
⎣
⎡
+Ψ
=≅
A
R
p
qN
V
xW
ε
()
2
1
0
2
⎥
⎦
⎤
⎢
⎣
⎡
+Ψ
=≅
D
R
n
qN
V

xW
ε
ε is the permittivity of Si
ε = 1.04x10
-12
F/cm
ε = K
S
ε
0
, where ε
0
= 8.85x10
-14
F/cm
and K
S
= 11.8 is the relative permittivity of silicon
ECE 410, Prof. A. Mason Lecture Notes 6.7
pn Junctions - Depletion Capacitance
• Free carriers are separated by the depletion layer
• Separation of charge creates junction capacitance
–Cj = εA/d ⇒ (d = depletion width, W)
– A is complex to calculate in semiconductor diodes
• consists of both bottom of the well and side-wall areas
– Cj is a strong function of biasing
• must be re-calculated if
bias conditions change
– CMOS doping is not linear/constant
• graded junction approximation

• Junction Breakdown
– if reverse bias is too high (typically > 30V) can get strong reverse current flow
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+Ψ
⎥
⎦
⎤
⎢
⎣
⎡
+
=
R
DA
DA
j
V
NN
NNq
AC
0
2

1
1
2
ε
ε is the permittivity of Si
ε = 11.8⋅ε
0
= 1.04x10
-12
F/cm
V
R
= applied reverse bias
⎟
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎜
⎝
⎛
Ψ
+
=

0
1
R
jo
j
V
C
C
()
2
1
0
2
⎥
⎦
⎤
⎢
⎣
⎡
+Ψ
=
DA
DA
jo
NN
NNq
AC
ε
⎟
⎟

⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎜
⎝
⎛
Ψ
+
=
3
0
1
R
jo
j
V
C
C
ECE 410, Prof. A. Mason Lecture Notes 6.8
• Forward Bias; V
D
> Ψ
0
– acts against built-in potential

– depletion width reduced
– diffusion currents increase with V
D
• minority carrier diffusion
• Reverse Bias; V
R
= -V
D
> 0
– acts to support built-in potential
– depletion width increased
– electric field increased
– small drift current flows
• considered leakage
• small until V
R
is too high and breakdown occurs
Diode Biasing and Current Flow
+ V -
D
V
D
V
f
+ V -
D
I
D
I
D

I
D
p
n
(
)
1−=
TD
VV
SD
eII
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+∝
AD
S
NN
AI
11
ECE 410, Prof. A. Mason Lecture Notes 6.9
MOSFET Capacitor
• MOSFETs move charge from drain to source underneath the gate,
if a conductive channel exists under the gate
• Understanding how and why the conductive channel is produced is

important
• MOSFET capacitor models the gate/oxide/substrate region
– source and drain are ignored
– substrate changes with applied gate voltage
•Consider an nMOS device
– Accumulation, V
G
< 0, (-)ve charge on gate
• induces (+)ve charge in substrate
• (+)ve charge accumulate from substrate holes (h+)
– Depletion, V
G
> 0 but small
• creates depletion region in substrate
• (-)ve charge but no free carriers
– Inversion, V
G
> 0 but larger
• further depletion requires high energy
• (-)ve charge pulled from Ground
• electron (e-) free carriers in channel
Si substrate = bulk
gate oxide
G
G
S
D
B
B
gate

channel
=
p-type Si substrate
depletion layer
depletion layer
Accumulation
Depletion
Inversion
p-type Si substrate
p-type Si substrate
V < 0
G
V > 0
G
V >> 0
G
BB
B
+ + + + + + +
+ + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + +
- - - - - - -
- - - - - - -
- - - - - - -
- - - - - - - - - -
ECE 410, Prof. A. Mason Lecture Notes 6.10
Capacitance in MOSFET Capacitor
• In Accumulation
– Gate capacitance = Oxide capacitance

– Cox = ε
ox
/t
ox
[F/cm
2
]
• In Depletion
– Gate capacitance has 2 components
– 1) oxide capacitance
– 2) depletion capacitance of the substrate depletion region
•Cdep= ε
si
/x
d
, x
d
= depth of depletion region into substrate
– Cgate = Cox (in series with) Cdep = Cox Cdep / (Cox+Cdep) < Cox
• C’s in series add like R’s in parallel
• In Inversion
– free carries at the surface
– Cgate = Cox
Cgate
V
G
Cox
inversion
depletion
accumulation

Cox
Cdep
ECE 410, Prof. A. Mason Lecture Notes 6.11
Inversion Operation
• MOSFET “off” unless in inversion
– look more deeply at inversion operation
• Define some stuff
– Qs = total charge in substrate
–V
G
= applied gate voltage
– Vox = voltage drop across oxide
– φ
s
= potential at silicon/oxide interface (relative to substrate-ground)
–Qs = -Cox V
G
–V
G
= Vox + φ
s
• During Inversion (for nMOS)
–V
G
> 0 applied to gate
– Vox drops across oxide (assume linear)
– φ
s
drops across the silicon substrate, most near the surface
ECE 410, Prof. A. Mason Lecture Notes 6.12

Surface Charge
•Q
B
= bulk charge, ion charge in depletion region under
the gate
–Q
B
= - q N
A
x
d
, x
d
= depletion depth
–Q
B
= - (2q ε
Si
N
A
φ
s
)
1/2
= f(V
G
)
– charge per unit area
• Qe = charge due to free electrons at substrate surface
•Qs = Q

B
+ Qe < 0 (negative charge for nMOS)
2
1
2
⎥
⎦
⎤
⎢
⎣
⎡
=
A
s
d
qN
x
εφ
depletion
region
Q
B
, bulk
charge
electron
layer, Qe
ECE 410, Prof. A. Mason Lecture Notes 6.13
Surface Charge vs. Gate Voltage
• Surface Charge vs. Gate Voltage
–V

G
< Vtn, substrate charge is all bulk charge, Qs = Q
B
–V
G
= Vtn, depletion region stops growing
•x
d
at max., further increase of V
G
will NOT increase x
d
•Q
B
at max.
–V
G
> Vtn, substrate charge has both components, Qs = Q
B
+ Qe
•since Q
B
is maxed, further increases in V
G
must increase Qe
• increasing Qe give more free carriers thus less resistance
• Threshold Voltage
– Vtn defined as gate voltage where Qe starts to form
–Qe= -Cox (V
G

-Vtn)
– Vtn is gate voltage required to
• overcome material difference between silicon and oxide
• establish depletion region in channel to max value/size
ECE 410, Prof. A. Mason Lecture Notes 6.14
Overview of MOSFET Current
• Gate current
– gate is essentially a capacitor ⇒ no current through gate
– gate is a control node
•V
G
< Vtn, device is off
•V
G
> Vtn, device is on and performance is a function of V
GS
and V
DS
• Drain Current (current from drain to source), I
D
– Source = source/supply of electrons (nMOS) or holes (pMOS)
– Drain = drain/sink of electrons (nMOS) or holes (pMOS)
–V
DS
establishes an E-field across (horizontally) the channel
• free charge in an E-field will create a drain-source current
•is I
D
drift or diffusion current?
• MOSFET I-V Characteristics

nMOS
drain @ (+)ve potential
Electron Flow
Current Flow
source @ ground
Charge Flow
Current Flow
↑ V
GS
V
DS
= V
GS
-Vtn
ECE 410, Prof. A. Mason Lecture Notes 6.15
Channel Charge and Current
• Threshold Voltage = Vtn, Vtp
– amount of voltage required on the gate to turn tx on
– gate voltage > Vtn/p will induce charge in the channel
•nMOS Channel Charge
–Qc = -C
G
(V
G
-Vtn), from Q=CV, (-) because channel holds electrons
•nMOS Channel Current (linear model:)
–I = |Qc| / t
t
, where t
t

=
transit time
, average time to cross channel
•t
t
= channel length / (average velocity) = L /
v
• average drift velocity in channel due to electric field
E
Æ
v
= μ
n
E
• assuming constant field in channel due to V
DS
Æ
E
= V
DS
/ L
• Æ
–I = μ
n
Cox (W/L) (V
G
-Vtn) V
DS
: linear model, assumes constant charge in channel
similar analysis applies for pMOS, see textbook

L
L
V
QcI
DS
n
μ
=
)(|| VtnVCoxWLQcCoxWLC
GG
−
=
⇒
=
assumes channel charge is
constant from source to drain
ECE 410, Prof. A. Mason Lecture Notes 6.16
Transconductance and Channel Resistance
•nMOSChannel Charge: Qc = -C
G
(V
G
-Vtn)
•nMOSlinear model Channel Current:
–I = μ
n
Cox(W/L)(V
G
-Vtn) V
DS

• assumes constant charge in channel, valid only for very small V
DS
•nMOSProcess Transconductance
–k’
n
= μ
n
Cox [A/V
2
] ⇒ I = k’
n
(W/L) (V
G
-Vtn) V
DS
•nMOSDevice Transconductance
– β
n
= μ
n
Cox (W/L) [A/V
2
] ⇒ I = β
n
(V
G
-Vtn) V
DS
– constant for set transistor size and process
•nMOSChannel Resistance

– channel current between Drain and Source
– channel resistance = V
DS
/ I
DS
–Rn= 1/( β
n
(V
G
-Vtn) )
•pMOS: k’p = μ
p
Cox, β
p
= μ
p
Cox (W/L)
similar analysis
applies for pMOS,
see textbook
)(
1
tnGSoxn
n
VV
L
W
C
R
−

=
μ
()
tpSGoxp
p
VV
L
W
C
R
−
=
μ
1
ECE 410, Prof. A. Mason Lecture Notes 6.17
nMOS Current vs.Voltage
• Cutoff Region
–V
GS
< Vtn
⇒ I
D
= 0
•Linear Region
–V
GS
> Vth, V
DS
> 0 but very small
• Qe = -Cox (V

GS
-Vtn)
•I
D
= μ
n
Qe (W/L) V
DS
⇒ I
D
= μ
n
Cox (W/L) (V
GS
-Vtn) V
DS
• Triode Region
–V
GS
> Vth, 0 < V
DS
< V
GS
-Vth
• surface potential, φ
s
, at drain now f(V
GS
-V
DS

=V
GD
) ⇒ less charge near drain
• assume channel charge varies linearly from drain to source
– at source: Qe = -Cox (V
GS
-Vtn), at drain: Qe = 0
⇒
∫
=
D
V
ID
yVyQI
0
)()(
δα
[
]
2
)(2
2
DSDStGS
OXn
D
VVVV
L
W
C
I −−=

μ
General Integral for expressing ID
• channel charge = f(y)
• channel voltage = f(y)
• y is direction from drain to source
↑ V
GS
V
DS
= V
GS
-Vtn
ECE 410, Prof. A. Mason Lecture Notes 6.18
nMOS Current vs.Voltage
• Saturation Region (Active Region)
–V
GS
> Vtn, V
DS
> V
GS
-Vtn
• surface potential at drain, φ
sd
= V
GS
-Vtn-V
DS
•when V
DS

= V
GS
-Vtn, φ
sd
= 0 ⇒ channel not inverted at the drain
– channel is said to be pinched off
• during pinch off, further increase in V
DS
will not increase I
D
–define saturation voltage, Vsat, when V
DS
= V
GS
-Vtn
• current is saturated, no longer increases
• substitute Vsat=V
GS
-Vtn for V
DS
into triode equation
⇒
2
)(
2
tGS
OXn
D
VV
L

W
C
I −=
μ
square law
equation
[
]
2
)(2
2
DSDStGS
OXn
D
VVVV
L
W
C
I −−=
μ
ECE 410, Prof. A. Mason Lecture Notes 6.19
Other Stuff
• Transconductance
– process transconductance, k’ = μ
n
Cox
• constant for a given fabrication process
–device transconductance, β
n
= k’ W/L

• Surface Mobility
– mobility at the surface is lower than mobility deep inside silicon
– for current, I
D
, calculation, typical μ
n
= 500-580 cm
2
/V-sec
• Effective Channel Length
– effective channel length reduced by
• lateral diffusion under the gate
• depletion spreading from drain-substrate junction
dD
XLdrawnLLeff
−
−
= 2)(
()()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−−
=
A

tGDs
d
qN
VVV
X
ε
2
G
S
L (drawn)
Leff
L
D
x
d
~x
d
D
ECE 410, Prof. A. Mason Lecture Notes 6.20
Second Order Effects
• Channel Length Modulation
– Square Law Equation predicts I
D
is constant with V
DS
–However, I
D
actually increases slightly with V
DS
•due to effective channel getting shorter as V

DS
increases
• effect called channel length modulation
– Channel Length Modulation factor, λ
• models change in channel length with V
DS
– Corrected I
D
equation
•Veff= V
GS
-Vtn
• Body Effect
– so far we have assumed that substrate and source are grounded
– if source not at ground, source-to-bulk voltage exists, V
SB
> 0
–V
SB
> 0 will increase the threshold voltage, Vtn = f(V
SB
)
– called Body Effect, or Body-Bias Effect
(
)
)(1)(
2
2
effDStGS
OXn

D
VVVV
L
W
C
I −+−=
λ
μ
ECE 410, Prof. A. Mason Lecture Notes 6.21
pMOS Equations
• Analysis of nMOS applies to pMOS with
following modifications
–physical
• change all n-tpye regions to p-type
• change all p-type regions to n-type
– substrate is n-type (nWell)
• channel charge is positive (holes) and (+)ve charged ions
– equations
•change V
GS
to V
SG
(V
SG
typically = VDD - V
G
)
•change V
DS
to V

SD
(V
SD
typically = VDD - V
D
)
• change Vtn to |Vtp|
– pMOS threshold is negative, nearly same magnitude as nMOS
–other factors
• lower surface mobility, typical value, μ
p
= 220 cm
2
/V-sec
•body effect, change V
SB
to V
BS
ECE 410, Prof. A. Mason Lecture Notes 6.22
Transistor Sizing
•Channel Resistance
“ON” resistance of transistors
–Rn= 1/(μ
n
Cox (W/L) (V
GS
-Vtn) )
–Rp= 1/(μ
p
Cox (W/L) (V

SG
-|Vtp|) )
• Cox = ε
ox
/t
ox
[F/cm
2
], process constant
• Channel Resistance Analysis
–R ∝ 1/W (increasing W decreases R & increases Current)
– R varies with Gate Voltage, see plot above
– If Wn = Wp, then Rn < Rp
•since μ
n
> μ
p
• assuming Vtn ~ |Vtp|
– to match resistance, Rn = Rp
• adjust Wn/Wp to balance for μ
n
> μ
p
V
G
VDD-|V
tp
|V
tn
Rn

Rp
ECE 410, Prof. A. Mason Lecture Notes 6.23
Transistor Sizing
•Channel Resistances
–Rn= 1/(μ
n
Cox (W/L) (V
G
-Vtn) )
–Rp= 1/(μ
p
Cox (W/L) (V
G
-|Vtp|) )
–Rn/Rp= μ
n
/μ
p
• if Vtn = |Vtp|, (W/L)
n
= (W/L)
p
• Matching Channel Resistance
– there are performance advantage to setting Rn = Rp
• discussed in Chapter 7
– to set Rn = Rp
• define mobility ratio, r = μ
n
/μ
p

•(W/L)
p
= r (W/L)
n
–pMOSmust be larger than nMOS for same resistance/current
•Negative Impact
– ⇒ C
Gp
= r C
Gn
larger gate = higher capacitance
How does this impact
circuit performance?
ECE 410, Prof. A. Mason Lecture Notes 6.24
MOSFET RC Model
•Modeling MOSFET resistance and capacitance is very
important for transient characteristics of the device
• RC Model
• Drain-Source (channel) Resistance, Rn
–Rn= V
DS
/ I
D
• function of bias voltages
– point (a), linear region
•Rn= 1/[β
n
(V
GS
-Vtn)]

– point (b), triode region
•Rn= 2/{β
n
[2(V
GS
-Vtn)-V
DS
]}
– point (c), saturation region
•Rn= 2V
DS
/ [β
n
(V
GS
-Vtn)
2
]
– general model equation
•Rn= 1/[β
n
(V
DD
-Vtn)]
time constant
at drain, τ
D
τ
D
= C

D
Rn
ECE 410, Prof. A. Mason Lecture Notes 6.25
MOSFET Capacitances -Preview
• Need to find C
S
and C
D
•MOSFET Small
Signal model
– Model Capacitances
• Cgs
• Cgd
•Cgb
• Cdb
• Csb
•no Csd!
• MOSFET Physical
Capacitances
– layer overlap
– pn junction
+
v
-
gs
v
s
i
s
v

g
v
d
i
d
gv
mb sb
gv
mgs
r
o
C
gs
C
gb
C
sb
C
db
C
gd
Gate
Drain
Source
Body (Bulk)