dynamic reconfiguration architectures and algorithms (series in computer science)

Dynamic Reconfiguration
Architectures and Algorithms
SERIES IN COMPUTER SCIENCE
Series Editor: Rami G. Melhem
University of Pittsburgh
Pittsburgh, Pennsylvania
DYNAMIC RECONFIGURATION
Architectures and Algorithms
Ramachandran Vaidyanathan and Jerry L. Trahan
ENGINEERING ELECTRONIC NEGOTIATIONS
A Guide to Electronic Negotiation Technologies for the Design and
Implementation of Next-Generation Electronic Markets—Future
Silkroads of eCommerce
Michael Ströbel
HIERARCHICAL SCHEDULING IN PARALLEL AND CLUSTER
SYSTEMS
Sivarama Dandamudi
MOBILE IP
Present State and Future
Abdul Sakib Mondal
OBJECT-ORIENTED DISCRETE-EVENT SIMULATION WITH JAVA
A Practical Introduction
José M. Garrido
A PARALLEL ALGORITHM SYNTHESIS PROCEDURE FOR HIGH-
PERFORMANCE COMPUTER ARCHITECTURES
Ian N. Dunn and Gerard G. L. Meyer
PERFORMANCE MODELING OF OPERATING SYSTEMS USING
OBJECT-ORIENTED SIMULATION
A Practical Introduction
José M. Garrido

POWER AWARE COMPUTING
Edited by Robert Graybill and Rami Melhem
THE STRUCTURAL THEORY OF PROBABILITY
New Ideas from Computer Science on the Ancient Problem of
Probability Interpretation
Paolo Rocchi
Dynamic Reconfiguration
Architectures and Algorithms
Ramachandran Vaidyanathan
and
Jerry L. Trahan
Louisiana State University
Baton Rouge, Louisiana
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Contents
List of Figures
xiii
Preface
xix
Part I Basics
1.
PRINCIPLES AND ISSUES
3
1.1
Illustrative Examples
4
1.2
The R-Mesh at a Glance
9
1.3
Importan
t
Issues
11
Problems
13
Bibliographic Notes
14
2.
THE RECONFIGURABLE MESH: A PRIMER
17
2.1

The Reconfigurable Mesh
17
2.1.1
The (Two-Dimensional) R-Mesh
18
2.2
Expressing R-Mesh Algorithms
22
2.3
Fundamental Algorithmic Techniques
23
2.3.1
Data Movement
24
2.3.2
Efficiency Acceleration—Adding Bits
27
2.3.3
Neighbor Localization—Chain Sorting
33
2.3.4
Sub-R-Mesh Generation—Maximum Finding
40
2.3.5
Distance Embedding—List Ranking
43
2.3.6
Connectivity Embedding— Connectivity
46
2.3.7

Function Decomposition—Adding N Numbers
49
2.4
Why an R-Mesh?
58
Problems
58
Bibliographic Notes
68
viii
DYNAMIC RECONFIGURATION
3.
MODELS OF RECONFIGURATION
71
3.1
The Reconfigurable Mesh—A Second Coat
71
3.1.1
Restricte
d
Bus Structure
72
3.1.2
Wor
d
Size
75
3.1.3
Accessin
g

Buses
77
3.1.4
Highe
r
Dimensions
79
3.1.5
One-Wa
y
Streets
86
3.2
Mor
e
Ways to Reconfigure
90
3.2.1
Reconfigurable Network
91
3.2.2
Reconfigurabl
e
Multiple Bus Machine
91
3.2.3
Optica
l
Models
92

3.2.4
Reconfiguratio
n
in FPGAs
96
3.3
Ho
w
Powerful Is Reconfiguration?
98
Problem
s
100
Bibliographi
c
Notes
110
Part II Algorithms
4.
ARITHMETIC ON THE R-MESH
117
4.1
Starter Set
117
4.1.1
Conversio
n
among Number Formats
118
4.1.2

Floatin
g
Point Numbers
119
4.1.3
Maximum/Minimu
m
120
4.2
The Foundation
122
4.2.1
Additio
n
123
4.2.2
Multiplicatio
n
134
4.2.3
Divisio
n
139
4.3
Multiplying Matrices
139
4.3.1
Matrix-Vecto
r
Multiplication

140
4.3.2
Matri
x
Multiplication
142
4.3.3
Spars
e
Matrix Multiplication
143
Problem
s
146
Bibliographi
c
Notes
149
5.
SORTING AND SELECTION
153
5.1
Sortin
g
on an R-Mesh
154
5.2
A Sub-Optimal Sorting Algorithm
155
5.3

An Optimal Sorting Algorithm
156
Contents
ix
5.3.1
Constant Time Sorting
156
5.3.2
Area-Time Tradeoffs
158
5.3.3
Sorting on Three-Dimensional R-Meshes
159
5.4
Selection on an R-Mesh
162
5.4.1 Indexing Schemes
162
5.4.2
An Outline of the Selection Algorithm
163
5.4.3
The Selection Algorithm
165
5.4.4
The Sorted Sample Algorithm
167
5.4.5
Complexity Analysis
171

Problems
173
Bibliographic Notes
176
6.
GRAPH ALGORITHMS
179
6.1
Graph Representations
180
6.2
Algorithms for Trees
180
6.2.1
Euler Tour
181
6.2.2
Euler Tour Applications
182
6.2.3
Tree Reconstruction
186
6.3
Algorithms for Graphs
192
6.3.1
Minimum Spanning Tree
192
6.3.2
Connectivity Related Problems

193
6.4
Algorithms for Directed Graphs
198
6.4.1
The Algebraic Path Problem Approach
198
6.4.2
Directed Acyclic Graphs
202
6.5
Efficient List Ranking
206
6.5.1
The Deterministic Method
207
6.5.2
The Randomized Approach
212
Problems
218
Bibliographic Notes
229
7.
COMPUTATIONAL GEOMETRY & IMAGE PROCESSING
231
7.1
Computational Geometry
232
7.1.1

Convex Hull
232
7.1.2
Convex Polygon Problems
244
7.1.3
Nearest Neighbors
249
7.1.4
Voronoi Diagrams
250
7.1.5
Euclidean Minimum Spanning Tree
253
7.1.6
Triangulation
254
x
DYNAMIC RECONFIGURATION
7.2
Image Processing
254
7.2.1
Basics
255
7.2.2
Histogram
257
7.2.3
Quadtree

261
7.2.4
Moments
267
7.2.5
Image Transforms
269
Problems
269
Bibliographic Notes
272
Part III Simulations and Complexity
8.
MODEL AND ALGORITHMIC SCALABILITY
277
8.1
Scaling Simulation on a Smaller Model Instance
278
8.1.1
Scaling the HVR-Mesh
281
8.1.2
Scaling the LR-Mesh
283
8.1.3
Scaling the FR-Mesh
289
8.1.4
Scaling the R-Mesh
294

8.2
Self-Simulation on a Larger Model Instance
298
8.3
Scaling Algorithms
299
8.3.1
Degree of Scalability
300
8.3.2
Matrix Multiplication
301
8.3.3
Matrix-Vector Multiplication
302
Problems
307
Bibliographic Notes
310
9.
COMPUTATIONAL COMPLEXITY OF
RECONFIGURATION
313
9.1
Mapping Higher Dimensions to Two Dimensions
314
9.1.1
Lower Bound on Mapping
315
9.1.2

Mapping Dimensions to Two Dimensions
315
9.1.3
Separation of the One-Dimensional R-Mesh from
Higher Dimensional R-Meshes
320
9.2
Simulations between Bit and Word Models
320
9.3
Relations to the PRAM
322
9.4
Loosen Up—Polynomially Bounded Models
326
9.5
Segmenting and Fusing Buses
326
9.5.1
The Reconfigurable Multiple Bus Machine
327
9.5.2
Relative Power of Polynomially Bounded Models
329
Contents
xi
9.5.3
Relating the B-RMBM and the PRAM
332
9.5.4

Relating the S-RMBM, HVR-Mesh, and PRAM
333
9.5.5
Relating the F-RMBM, E-RMBM, and R-Mesh
336
9.6
Relations to Turing Machines and Circuits: Hierarchy
340
9.6.1
Turing Machine Definitions
340
9.6.2
Circuit Definitions
340
9.6.3
Complexity Classes
341
9.6.4
Relations to Turing Machines
342
9.6.5
Relations to Circuits
346
Problems
348
Bibliographic Notes
351
Part IV Other Reconfigurable Architectures
10.
OPTICAL RECONFIGURABLE MODELS

357
10.1
Models, Models Everywhere
358
10.1.1
The LARPBS Model
360
10.1.2 Other Models
364
10.2
Basic Algorithmic Techniques
368
10.2.1 Permutation Routing
369
10.2.2 Binary Prefix Sums
369
10.3 Algorithms for Optical Models
374
10.3.1
Basic Results
374
10.3.2
Sorting and Selection
377
10.3.3
Multiple Addition
383
10.3.4
Matrix Multiplication
383

10.3.5
387
10.4
Complexity of Optical Models
394
10.4.1
Simulating PRAMs
395
10.4.2
Equivalence of One-Dimensional Models
396
10.4.3
Relating the PR-Mesh and the LR-Mesh
399
10.4.4
Relating Two-Dimensional Optical Models
403
Problems
408
Bibliographic Notes
412
11.
RUN-TIME RECONFIGURATION
417
11.1 FPGA Background
419
11.1.1
FPGA Structure
419
xii

DYNAMIC RECONFIGURATION
11.1.2
FPGA System Model
422
11.2
Run-Time Reconfiguration Concepts and Examples
424
11.2.1
Basic Concepts
424
11.2.2
Examples: Specific Problems
428
11.2.3
Examples: Generic Problems
434
11.3 Hardware Operating System
438
11.3.1
Dynamic Instruction Set Computer
439
11.3.2
RAGE
440
11.3.3
Configuration Controllers
441
11.3.4
Task Compaction
442

11.4
Alternative Implementations
445
11.4.1
Early Configurable Computing Machines
446
11.4.2
Other Directions in RTR
447
11.5
Designing Implementable R-Mesh Algorithms
450
11.5.1
Bus Delay
451
11.5.2
An LR-Mesh Implementation
455
11.5.3 Retooling Algorithms for the Bends-Cost Measure
458
Problems
461
References
471
Index
499
List of Figures
1.1
An N-processor segmentable bus.
5

1.2
Bus structure for a binary tree algorithm.
6
1.3
Bus structure for finding the OR.
6
1.4
Example of a one-dimensional R-Mesh.
9
1.5
Example of a two-dimensional R-Mesh.
10
1.6
Example of computing on the R-Mesh.
10
2.1
A reconfigurable linear array.
17
2.2
An example of an R-Mesh.
19
2.3
Port partitions of an R-Mesh.
20
2.4
An R-Mesh bus configuration and graph.
20
2.5
Broadcasting on an R-Mesh.
25

2.6
Permutation routing.
27
2.7
Adding bits.
28
2.8
addition on an R-Mesh.
29
2.9
Examples of and
31
2.10
Neighbor localization example.
34
2.11
Chain sorting.
36
2.12
Concatenating lists in chain sorting.
39
2.13
Maximum finding example.
42
2.14
List ranking strategy.
45
2.15
Illustration of the connectivity algorithm.
48

2.16
Adding a distributed unary integer to 1-bit numbers.
51
2.17
Dividing a distributed unary integer by 2.
52
2.18
Illustration of terms for adding integers.
53
2.19
Module for carry generation.
55
xiv
DYNAMIC RECONFIGURATION
2.20
Cascading modules
56
2.21
Labeled binary trees.
59
2.22
Finite automaton for Algorithm 2.3.
62
2.23
Finite automaton for Problem 2.21(a).
62
3.1
R-Meshes with restricted bus structures.
73
3.2

A three-dimensional R-Mesh.
80
3.3
Indexing ports for priority resolution.
81
3.4
A priority resolution example.
85
3.5
Directedness in buses.
87
3.6
The directed R-Mesh.
88
3.7
Reachability on a directed R-Mesh.
89
3.8
The Reconfigurable Multiple Bus Machine (RMBM).
92
3.9
Structure of an optical model.
93
3.10
Optical pipelining.
94
3.11
Coincident pulse addressing.
95
3.12

Structure of a typical FPGA.
96
3.13
Powers of conventional and reconfigurable models.
98
3.14
A 3 × 5 RMESH.
101
3.15
A 3-port shift switch.
105
3.16
Exclusive OR with shift switches.
106
3.17
A P × B Distributed Memory Bus Computer.
107
4.1
Example representations of for
119
4.2
Partitioning an R × C R-Mesh
121
4.3
Input arrangement in an R × C R-Mesh
123
4.4
Example of R-Mesh adding two 8-bit numbers.
124
4.5

Sample h-slice and v-slice.
126
4.6
Multiplication on the bit-model R-Mesh.
135
4.7
Slices of a three-dimensional R-Mesh.
141
4.8
Example sparse matrix and data movement.
144
5.1
Transposin
g
and untransposing for columnsort.
156
5.2
Shifting and unshifting for columnsort.
157
5.3
A columnsorting network.
158
5.4
Components of columnsort on a three-dimensional
R-Mesh.
161
5.5
Indexing examples for R-Mesh processors.
163
5.6

Merge tree for a sorted sample.
168
5.7
Merge tree for a sub-R-Mesh of Algorithm 5.2.
170
xv
List of Figures
5.8
Proximity indexing.
175
6.1
Euler tour of a tree.
181
6.2
Preorder-inorder traversal.
187
6.3
Merging preorder and inorder traversals.
188
6.4
Finding distances in a directed graph.
204
6.5
List ranking with a balanced subset.
213
6.6
Embedding a list in an N × N R-Mesh.
214
6.7
An Euler path as a list of vertex copies.

220
7.1
Convex hull of a set of planar points.
232
7.2
Example of supporting line for two convex hulls.
233
7.3
Partitioning a set of points using four extreme points.
235
7.4
Angles among points and the
236
7.5
Points in labeled with
237
7.6
Illustration of contact points and upper hull tangent.
238
7.7
Proximity order for an 8 × 8 array.
239
7.8
Upper, lower, and crossing common tangents.
246
7.9
Supporting lines for polygons and samples.
248
7.10
Example Voronoi diagram.

251
7.11
Connected components of an image.
255
7.12
Gray values in sub-R-Meshes before a merge.
258
7.13
Quadtree representation.
260
7.14
An example to illustrate quadtree construction.
261
7.15
Determining block size of a quadtree.
263
7.16
Marking active processors of a quadtree.
266
8.1
Contraction, windows, and folds mappings.
280
8.2
Lower bound using contraction mapping.
283
8.3
Multiple disjoint segments of one bus in a window.
286
8.4
Entering segment with an awakening partner.

286
8.5
Dual bus structure of mimicking that of
287
8.6
Linear connected components (LCC) example.
288
8.7
Slices and windows of simulated FR-Mesh.
291
8.8
Illustration of horizontal prefix assimilation.
292
8.9
Linear configurations and squad configurations.
296
8.10
LR-Mesh simulating an R-Mesh (Steps 1–3).
297
8.11
Non-linear and terminal configurations.
298
8.12
Orthogonal scaling multiple addition.
304
xvi
DYNAMIC RECONFIGURATION
8.13
Slices of a three-dimensional R-Mesh.
306

8.14
Example bus configuration for Problem 8.7.
307
9.1
A layout for a 5 × 3 × 4 R-Mesh.
317
9.2
Block simulating a R-Mesh processor.
319
9.3
The structure of the RMBM.
328
9.4
Relative powers of PRAM, RMBM, and R-Mesh.
331
9.5
Example simulation of S-RMBM by HVR-Mesh.
334
9.6
Simulation of an F-RMBM on an R-Mesh.
337
9.7
Simulation of atomic segments by an F-RMBM.
339
9.8
Reconfigurable model classes and TM space classes.
342
9.9
Reconfigurable model classes and circuit classes.
343

10.1
Structure of an LARPBS.
359
10.2
A six processor LARPBS with two subarrays.
361
10.3
Select and reference frames for LARPBS example.
363
10.4
Linear Array Processors with Pipelined Buses.
364
10.5
Structure of a POB.
365
10.6
Select and reference frames for POB example.
365
10.7
Structure of an LAROB.
366
10.8
First phase of LARPBS prefix sums algorithm.
370
10.9
A prefix sums example on the LARPBS.
371
10.10
Slices of a three-dimensional R-Mesh.
385

10.11
Balancing writers phase for
392
10.12
Blocks for an LR-Mesh simulation of a PR-Mesh.
402
10.13
APPBS processor with switches.
404
10.14
PR-Mesh processors simulating an APPBS processor.
405
10.15
APPBS processors simulating an LR-Mesh processor.
407
11.1
Generic structure of an FPGA.
420
11.2
A logic cell in the Xilinx Virtex family of FPGAs.
421
11.3
Hybrid System Architecture Model (HySAM).
423
11.4
KCM multiplying 8-bit inputs using 4-bit LUTs.
425
11.5
LUT entries in a KCM for
426

11.6
Example of reconfiguring while executing.
427
11.7
Morphing Pipeline A into Pipeline B.
427
11.8
Basic flow of data in an FIR filter.
429
11.9
Using KCMs for nonadaptive filter coefficients.
429
11.10
Using KCMs in an adaptive FIR filter.
430
List of Figures
xvii
11.11
Feedforward neural network for backpropagation.
431
11.12
Sizes and times for phases of RTR motion estimator.
434
11.13
Conventional and domain-specific mapping approaches.
437
11.14
Structure of the reconfigurable hardware of DISC.
440
11.15

Relations among system components in RAGE.
441
11.16
Example of fragmentation on an FPGA.
443
11.17
One-dimensional, order-preserving compaction.
444
11.18
Visibility graph for Figure 11.16(b).
445
11.19
Programmable active memories (PAM) structure.
447
11.20
Garp structure.
449
11.21
An illustration of bus delay measures.
454
11.22
Structure of a 4 × 4 HVR-Mesh implementation.
456
11.23
Processor switches in an LR-Mesh implementation.
457
11.24
A bus delay example for the LR-Mesh implementation.
457
11.25

Adding bits with bounded-bends buses.
460
11.26
Resource requirements for Problem 11.15.
465
11.27
Configuration times for Problem 11.15.
465
11.28
Tasks for Problem 11.21.
467
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Preface
Computing with dynamic reconfiguration has developed into a ma-
ture area, with a rich collection of techniques, results, and algorithms.
A dynamically reconfigurable architecture (or simply a reconfigurable
architecture) typically consists of a large number of computing elements
connected by a reconfigurable communication medium. By dynamically
restructuring connections between the computing elements, these archi-
tectures admit extremely fast solutions to several computational prob-
lems. The interaction between computation and the communication
medium permits novel techniques not possible on a fixed-connection net-
work.
This book spans the large body of work on dynamically reconfig-
urable architectures and algorithms. It is not an exhaustive collection of
results in this area, rather, it provides a comprehensive view of dynamic
reconfiguration by emphasizing fundamental techniques, issues, and al-
gorithms. The presentation includes a wide repertoire of topics, starting
from a historical perspective on early reconfigurable systems, ranging
across a wide variety of results and techniques for reconfigurable mod-

els, examining more recent developments such as optical models and
run-time reconfiguration (RTR), and finally touching on an approach to
implementing a dynamically reconfigurable model.
Researchers have developed algorithms on a number of reconfigurable
architectures, generally similar, though differing in details. One aim of
this book is to present these algorithms in the setting of a single com-
putational platform, the reconfigurable mesh (R-Mesh). The R-Mesh
possesses the basic features of a majority of other architectures and is
sufficient to run most algorithms. This structure can help the reader
relate results and understand techniques without the haze of details on
just what is and is not allowed from one model to the next.
xx
DYNAMIC RECONFIGURATION
For algorithms that require additional features beyond those of the
R-Mesh, we highlight the features and reasons for their use. For exam-
ple, having directional buses permits an R-Mesh to solve the directed
graph reachability problem in constant time, which is not known to be
(and not likely to be) possible for an R-Mesh with undirected buses. In
describing this algorithm, we pinpoint just where directed buses permit
the algorithm to succeed and undirected buses would fail.
Although most of the book uses the R-Mesh as the primary vehicle
of expression, a substantial portion deals with the relationships between
the R-Mesh and other models of computation, both reconfigurable and
traditional (Chapters 9 and 10). The simulations integral to developing
these relationships also provide generic methods to translate algorithms
between models.
The book is addressed to researchers, graduate students, and sys-
tem designers. To the researcher, it offers an extensive digest of topics
ranging from basic techniques and algorithms to theoretical limits of
computing on reconfigurable architectures. To the system designer, it

provides a comprehensive reference to tools and techniques in the area.
In particular, Part IV of the book deals with optical models and Field
Programmable Gate Arrays (FPGAs), providing a bridge between the-
ory and practice.
The book contains over 380 problems, ranging in difficulty from those
meant to reinforce concepts to those meant to fill gaps in the presentation
to challenging questions meant to provoke further thought. The book
features a list of figures, a rich set of bibliographic notes at the end of
each chapter, and an extensive bibliography. The book also includes a
comprehensive index with topics listed under multiple categories. For
topics spanning several pages, page numbers of key ideas are in bold.
Organization of Book
The book comprises four parts. Part I (Chapters 1–3) provides a
first look at reconfiguration. It includes introductory material, describ-
ing the overall nature of reconfiguration, various models and architec-
tures, important issues, and fundamental algorithmic techniques. Part II
(Chapters 4–7) deals with algorithms on reconfigurable architectures for
a variety of problems. Part III (Chapters 8 and 9) describes self and
mutual simulations for several reconfigurable models, placing their com-
putational capabilities relative to traditional parallel models of compu-
tation and complexity classes. Part IV (Chapters 10 and 11) touches on
capturing, in the models themselves, the effect of practical constraints,
providing a bridge between theory and practice. Each chapter is rea-
PREFACE
xxi
sonably self-contained and includes a set of exercises and bibliographic
notes.
The presentation in this book is suitable for a graduate level course
and only presupposes basic ideas in parallel computing. Such a course
could include (in addition to Chapters 1–3), Chapters 4–8 (for an em-

phasis on algorithms), Chapters 4–6, 8, 9 (for a more theoretical flavor),
portions of Chapters 4–6 along with Chapters 8, 10, 11 (to stress aspects
with more bearing on implementability). This book could also serve as
a companion text to most graduate courses on parallel computing.
Chapter 1: Principles and Issues
This chapter introduces the idea of dynamic reconfiguration and re-
views important considerations in reconfigurable architectures. It
provides a first look at the R-Mesh, the model used for most of the
book.
Chapter 2: The Reconfigurable Mesh: A Primer
This chapter details the R-Mesh model and uses it to describe sev-
eral techniques commonly employed in algorithms for reconfigurable
architectures. It also develops a palette of fundamental algorithms
that find use as building blocks in subsequent chapters.
Chapter 3: Models of Reconfiguration
This chapter provides an overview of other models of reconfiguration
with examples of their use. These models include restrictions and en-
hancements of the R-Mesh, other bus-based models, optical models,
and field programmable gate arrays. It describes relationships among
these models based on considerations of computing power and imple-
mentability.
Chapter 4: Arithmetic on the R-Mesh
Unlike conventional computing platforms, resource bounds for even
simple arithmetic operations on reconfigurable architectures depend
on the size and representations of the inputs. This chapter addresses
these issues and describes algorithms for a variety of problems, in-
cluding techniques for fast addition, multiplication, and matrix mul-
tiplication.
Chapter 5: Sorting and Selection
This chapter deals with problems on totally ordered sets and includes

techniques for selection, area-optimal sorting, and speed-efficiency
trade-offs.
Chapter 6: Graph Algorithms
Methods for embedding graphs in reconfigurable models are described
xxii
DYNAMIC RECONFIGURATION
in the context of list ranking and graph connectivity. Along with
other techniques such as tree traversal, rooting, and labeling, these
techniques illustrate how methods developed on non-reconfigurable
models can be translated to constant-time algorithms on reconfig-
urable architectures.
Chapter 7: Computational Geometry & Image Processing
This chapter applies the methods developed in preceding chapters
to solve problems such as convex hull, Voronoi diagrams, histogram-
ming, and quadtree generation.
Chapter 8: Model and Algorithmic Scalability
Normally, algorithm design does not consider the relationship be-
tween problem size and the size of the available machine. This chap-
ter deals with issues that arise from a mismatch between the problem
and machine sizes, and introduces methods to cope with them.
Chapter 9: Computational Complexity of Reconfiguration
This chapter compares the computational “powers” of different re-
configurable models and places “reconfigurable complexity classes”
in relation to conventional Turing machine, PRAM, and circuit com-
plexity classes.
Chapter 10:
Optical Reconfigurable Models
This chapter describes reconfigurable architectures that employ fiber-
optic buses. An optical bus offers a useful pipelining technique that
permits moving large amounts of information among processors de-

spite a small bisection width. The chapter introduces models, de-
scribes algorithms and techniques, and presents complexity results.
Chapter 11: Run-Time Reconfiguration
This chapter details run-time reconfiguration techniques for Field
Programmable Gate Arrays (FPGAs) and touches upon the relation-
ships between FPGA-type and R-Mesh-type platforms. Towards this
end, it presents an approach to implementing R-Mesh algorithms on
an FPGA-type environment.
Acknowledgments. We are grateful to the National Science Founda-
tion for its support of our research on dynamic reconfiguration; numer-
ous results in this book and much of the insight that formed the basis
of our presentation resulted from this research. Our thanks also go to
Hossam ElGindy, University of New South Wales, for his suggestions on
organizing Chapter 2. Our thanks go to numerous students for their
PREFACE
xxiii
constructive criticisms of a preliminary draft of this book. Most impor-
tantly, this book would not have been possible without the patience and
support of our families. We dedicate this book to them.
R. VAIDYANATHAN
J. L. TRAHAN
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