ultra low-power electronics and design

TLFeBOOK
ULTRA LOW-POWER ELECTRONICS AND DESIGN
TLFeBOOK
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TLFeBOOK
Ultra Low-Power
Electronics and Design
Edited by
Enrico Macii
Politecnico di Torino,
Italy
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
TLFeBOOK
eBook ISBN: 1-4020-8076-X
Print ISBN: 1-4020-8075-1
©2004 Springer Science + Business Media, Inc.
Print ©2004 Kluwer Academic Publishers
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
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Created in the United States of America
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Contents
CONTRIBUTORS…………………………………………………………………….VII
PREFACE…………………………………………………………….……………… IX
INTRODUCTION……………………………………………………………………XIII
1. ULTRA-LOW-POWER DESIGN: DEVICE AND LOGIC DESIGN

APPROACHES……………………………………….………………………………….1
2. ON-CHIP OPTICAL INTERCONNECT FOR LOW-POWER……………………21
3. NANOTECHNOLOGIES FOR LOW POWER……………….…………………….40
4. STATIC LEAKAGE REDUCTION THROUGH SIMULTANEOUS
V
t
/T
ox
AND STATE ASSIGNMENT………………………………………………….56
5. ENERGY-EFFICENT SHARED MEMORY ARCHITECTURES FOR
MULTI-PROCESSOR SYSTEMS-ON-CHIP
………………………………… …
84
6. TUNING CACHES TO APPLICATIONS FOR LOW-ENERGY EMBEDDED
SYSTEMS…………………………………………………………………………… 103
7. REDUCING ENERGY CONSUMPTION IN CHIP MULTIPROCESSORS
USING WORKLOAD VARIATIONS…………………………………………… 123
8. ARCHITECTURES AND DESIGN TECHNIQUES FOR ENERGY
EFFICIENT EMBEDDED DSP AND MULTIMEDIA PROCESSING……….….141
9. SOURCE-LEVEL MODELS FOR SOFTWARE POWER OPTIMIZATION… 156
10. TRANSMITTANCE SCALING FOR REDUCING POWER DISSIPATION
OF A BACKLIT TFT-LCD………………………………………………………… 172
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11. POWER-AWARE NETWORK SWAPPING FOR WIRELESS PALMTOP
PCS…………………………………………………………………………………… 198
12. ENERGY EFFICIENT NETWORK-ON-CHIP DESIGN…………………………214
13. SYSTEM LEVEL POWER MODELING AND SIMULATION OF
HIGH-END INDUSTRIAL NETWORK-ON-CHIP
……………………………….
233

14. ENERGY AWARE ADAPTATIONS FOR END-TO-END VIDEO
STREAMING TO MOBILE HANDHELD DEVICES…………………………….255
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Contributors
A. Acquaviva
Università di Urbino
L. Benini
Università di Bologna
D. Bertozzi
Università di Bologna
D. Blaauw
University of Michigan, Ann Arbor
A. Bogliolo
Università di Urbino
A. Bona
STMicroelectronics
C. Brandolese
Politecnico di Milano
W.C. Cheng
University of Southern California
G. De Micheli
Stanford University
N. Dutt
University of California, Irvine
W. Fornaciari
Politecnico di Milano
F. Gaffiot
Ecole Centrale de Lyon
J. Gautier

CEA-DRT–LETI/D2NT–CEA/GRE
A. Gordon-Ross
University of California, Riverside
R. Gupta
University of California, San Diego
C. Heer
Infineon Technologies AG
M. J. Irwin
Pennsylvania State University
I. Kadayif
Canakkale Onsekiz Mart University
M. Kandemir
Pennsylvania State University
B. Kienhuis
Leiden
I. Kolcu
UMIST
E. Lattanzi
Università di Urbino
D. Lee
University of Michigan, Ann Arbor
A. Macii
Politecnico di Torino
S. Mohapatra
University of California, Irvine
I. O’Connor
Ecole Centrale de Lyon
K. Patel
Politecnico di Torino
M. Pedram

University of Southern California
C. Pereira
University of California, San Diego
C. Piguet
CSEM
M. Poncino
Università di Verona
F. Salice
Politecnico di Milano
P. Schaumont
University of California, Los Angeles
U. Schlichtmann
Technische Universität München
D. Sylvester
University of Michigan, Ann Arbor
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F. Vahid
University of California, Riverside
and University of California, Irvine
N. Venkatasubramanian
University of California, Irvine
I. Verbauwhede
University of California, Los Angeles
and K.U.Leuven
N. Vijaykrishnan
Pennsylvania State University
V. Zaccaria
STMicroelectronics
R. Zafalon

STMicroelectronics
B. Zhai
University of Michigan, Ann Arbor
C. Zhang
University of California, Riverside
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Preface
Today we are beginning to have to face up to the consequences of the
stunning success of Moore’s Law, that astute observation by Intel’s Gordon
Moore which predicts that integrated circuit transistor densities will double
every 12 to 18 months. This observation has now held true for the last 25
years or more, and there are many indications that it will continue to hold
true for many years to come. This book appears at a time when the first
examples of complex circuits in 65nm CMOS technology are beginning to
appear, and these products already must take advantage of many of the
techniques to be discussed and developed in this book. So why then should
our increasing success at miniaturization, as evidenced by the success of
Moore’s Law, be creating so many new difficulties in power management in
circuit designs?
The principal source and the physical origin of the problem lies in the
differential scaling rates of the many factors that contribute to power
dissipation in an IC – transistor speed/density product goes up faster than
the energy per transition comes down, so the power dissipation per unit area
increases in a general sense as the technology evolves.
Secondly, the “natural” transistor switching speed increase from one
generation to the next is becoming downgraded due to the greater parasitic
losses in the wiring of the devices. The technologists are offsetting this
problem to some extent by introducing lower permittivity dielectrics (“low-
k”) and lower resistivity conductors (copper) – but nonetheless to get the

needed circuit performance, higher speed devices using techniques such as
silicon-on-insulator (SOI) substrates, enhanced carrier mobility (“strained
silicon”) and higher field (“overdrive”) operation are driving power
densities ever upwards. In many cases, these new device architectures are
increasingly leaky, so static power dissipation becomes a major headache in
power management, especially for portable applications.
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A third factor is system or application driven – having all this integration
capability available encourages us to combine many different functional
blocks into one system IC. This means that in many cases, a large part of the
chip’s required functionality will come from software executing on and
between multiple on-chip execution units; how the optimum partitioning
between hardware architecture and software implementation is obtained is a
vast subject, but clearly some implementations will be more energy efficient
than others. Given that, in many of today’s designs, more than 50% of the
total development effort is on the software that runs on the chip, getting this
partitioning right in terms of power dissipation can be critical to the success
of (or instrumental in the failure of!) the product.
A final motivation comes from the practical and environmental
consequences of how we design our chips – state-of-the-art high
performance circuits are dissipating up to 100W per square centimeter – we
only need 500 square meters of such silicon to soak up the output of a small
nuclear power station. A related argument, based on battery lifetime, shows
that the “converged” mobile phone application combining telephony, data
transmission, multimedia and PDA functions that will appear shortly is
demanding power at the limit of lithium-ion or even methanol-water fuel cell
battery technology. We have to solve the power issue by a combination of
design and process technology innovations; examples of current approaches
to power management include multiple transistor thresholds, triple gate

oxide, dynamic supply voltage adjustment and memory architectures.
Multiple transistor thresholds is a technique, practiced for several years
now, that allows the designer to use high performance (low Vt) devices
where he needs the speed, and low leakage (high Vt) devices elsewhere. This
benefits both static power consumption (through less sub-threshold leakage)
and dynamic power consumption (through lower overall switching currents).
High threshold devices can also be used to gate the supplies to different parts
of the circuit, allowing blocks to be put to sleep until needed.
Similar to the previous technique, triple gate oxide (TGO) allows circuit
partitioning between those parts that need performance and other areas of the
circuit that don’t. It has the additional benefit of acting on both sub-threshold
leakage and gate leakage. The third oxide is used for I/O and possibly
mixed-signal. It is expected over the next few years that the process
technologists will eventually replace the traditional silicon dioxide gate
dielectric of the CMOS devices by new materials such as rare earth oxides
with much higher dielectric constants that will allow the gate leakage
problem to be completely suppressed.
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Dynamic supply voltage adjustment allows the supply voltage to different
blocks of the circuit to be adjusted dynamically in response to the immediate
performance needs for the block – this very sophisticated technique will take
some time to mature.
Finally, many, if not most, advanced devices use very large amounts of
memory for which the contents may have to be maintained during standby;
this consumes a substantial amount of power, either through refreshing
dynamic RAM or through the array leakage for static RAM. Traditional non-
volatile memories have writing times that are orders of magnitude too slow
to allow them to substitute these on-chip memories. New developments,
such as MRAM, offer the possibility of SRAM-like performance coupled

with unlimited endurance and data retention, making them potential
candidates to replace the traditional on-chip memories and remove this
component of standby power consumption.
Most of the approaches to power management described briefly above
will be employed in 65nm circuits, but there are a lot more good ideas
waiting to be applied to the problem, many of which you will find clearly
and concisely explained in this book.
Mike Thompson, Philippe Magarshac
k
STMicroelectronics, Central R&D
Crolles, France
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Introduction
ULTRA LOW-POWER ELECTRONICS AND
DESIGN
Enrico Macii
Politecnico di Torino
Power consumption is a key limitation in many electronic systems today,
ranging from mobile telecom to portable and desktop computing systems,
especially when moving to nanometer technologies. Power is also a
showstopper for many emerging applications like ambient intelligence and
sensor networks. Consequently, new design techniques and methodologies
are needed to control and limit power consumption.
The 2004 edition of the DATE (Design Automation and Test in Europe)
conference has devoted an entire Special Focus Day to the power problem
and its implications on the design of future electronic systems. In particular,
keynote presentations and invited talks by outstanding researchers in the field

of low-power design, as well as several technical papers from the regular
conference sessions have addressed the difficulties ahead and advanced
strategies and principles for achieving ultra low-power design solutions.
Purpose of this book is to integrate into a single volume a selection of these
contributions, duly extended and transformed by the authors into chapters
proposing a mix of tutorial material and advanced research results.
The manuscript consists of a total of 14 chapters, addressing different aspects
of ultra low-power electronics and design. Chapter 1 opens the volume by
providing an insight to innovative transistor devices that are capable of
operating with a very low threshold voltage, thus contributing to a significant
reduction of the dynamic component of power consumption. Solutions for
limiting leakage power during stand-by mode are also discussed. The chapter
closes with a quick overview of low-power design techniques applicable at
the logic level, including multi-V
dd
, multi-V
th
and hybrid approaches.
Chapter 2 focuses on the problem of reducing power in the interconnect
network by investigating alternatives to traditional metal wires. In fact,
according to the 2003 ITRS roadmap, metallic interconnections may not be
able to provide enough transmission speed and to keep power under control
for the upcoming technology nodes (65nm and below). A possible solution,
explored in the chapter, consists of the adoption of optical interconnect
networks. Two applications are presented: Clock distribution and data
communication using wavelength division multiplexing.
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In Chapter 3, the power consumption problem is faced from the technology
point of view by looking at innovative nano-devices, such as single-electron

or few-electron transistors. The low-power characteristics and potential of
these devices are reviewed in details. Other devices, including carbon nano-
tube transistors, resonant tunnelling diodes and quantum cellular automata
are also treated.
Chapter 4 is entirely dedicated to advanced design methodologies for
reducing sub-threshold and gate leakage currents in deep-submicron CMOS
circuits by properly choosing the states to which gates have to be driven
when in stand-by mode, as well as the values of the threshold voltage and of
the gate oxide thickness. The authors formulate the optimization problem for
simultaneous state/V
th
and state/V
th
/T
ox
assignments under delay constraints
and propose both an exact method for its optimal solution and two practical
heuristics with reasonable run-time. Experimental results obtained on a
number of benchmark circuits demonstrate the viability of the proposed
methodology.
Chapter 5 is concerned with the issue of minimizing power consumption of
the memory subsystem in complex, multi-processor systems-on-chip
(MPSoCs), such as those employed in multi-media applications. The focus is
on design solutions and methods for synthesizing memory architectures
containing both single-ported and multi-ported memory banks. Power
efficiency is achieved by casting the memory partitioning design paradigm to
the case of heterogeneous memory structures, in which data need to be
accessed in a shared manner by different processing units.
Chapter 6 addresses the relevant problem of minimizing the power consumed
by the cache hierarchy of a microprocessor. Several design techniques are

discussed, including application-driven automatic and dynamic cache
parameter tuning, adoption of configurable victim buffers and frequent-value
data encoding and compression.
Power optimization for parallel, variable-voltage/frequency processors is the
subject of Chapter 7. Given a processor with such an architecture, this
chapter investigates the energy/performance tradeoffs that can be spanned in
parallelizing array-intensive applications, taking into account the possibility
that individual processing units can operate at different voltage/frequency
levels. In assigning voltage levels to processing units, compiler analysis is
used to reveal hetherogeneity between the loads of the different units in
parallel execution.
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Chapter 8 provides guidelines for the design and implementation of DSP and
multi-media applications onto programmable embedded platforms. The
RINGS architecture is first introduced, followed by a detailed discussion on
power-efficient design of some of the platform components, namely, the
DSPs. Next, design exploration, co-design and co-simulation challenges are
addressed, with the goal of offering to the designers the capability of
including into the final architecture the right level of programmability (or
reconfigurability) to guarantee the required balance between system
performance and power consumption.
Chapter 9 targets software power minimization through source code
optimization. Different classes of code transformations are first reviewed;
next, the chapter outlines a flow for the estimation of the effects that the
application of such transformations may have on the power consumed by a
software application. At the core of the estimation methodology there is the
development of power models that allow the decoupling of processor-
independent analysis from all the aspects that are tightly related to processor
architecture and implementation. The proposed approach to software power

minimization is validated through several experiments conducted on a
number of embedded processors for different types of benchmark
applications.
Reduction of the power consumed by TFT liquid crystal displays, such as
those commonly used in consumer electronic products is the subject of
Chapter 10. More specifically, techniques for reducing power consumption
of transmissive TFT-LCDs using a cold cathode fluorescent lamp backlight
are proposed. The rationale behind such techniques is that the transmittance
function of the TFT-LCD panel can be adjusted (i.e., scaled) while meeting
an upper bound on a contrast distortion metric. Experimental results show
that significant power savings can be achieved for still images with very little
penalty in image contrast.
Chapter 11 addresses the issue of efficiently accessing remote memories
from wireless systems. This problem is particularly important for devices
such as palmtops and PDAs, for which local memory space is at a premium
and networked memory access is required to support virtual memory
swapping. The chapter explores performance and energy of network
swapping in comparison with swapping on local microdrives and FLASH
memories. Results show that remote swapping over power-manageable
wireless network interface cards can be more efficient than local swapping
and that both energy and performance can be optimized by means of power-
aware reshaping of data requests. In other words, dummy data accesses can
be preemptively inserted in the source code to reshape page requests in order
to significantly improve the effectiveness of dynamic power management.
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Chapter 12 focuses on communication architectures for multi-processor
SoCs. The network-on-chip (NoC) paradigm is reviewed, touching upon
several issues related to power optimization of such kinds of communication
architectures. The analysis goes on a layer-by-layer basis, and particular

emphasis is given to customized, domain-specific networks, which represent
the most promising scenario for communication-energy minimization in
multi-processor platforms.
Chapter 13 provides a natural follow up to the theory of NoCs covered in the
previous chapter by describing an industrial application of this type of
communication architecture. In particular, the authors introduce an
innovative methodology for automatically generating the power models of a
versatile and parametric on-chip communication IP, namely the STBus by
STMicroelectronics. The methodology is validated on a multi-processor
hardware platform including four ARM cores accessing a number of
peripheral targets, such as SRAM banks, interrupt slaves and ROM
memories.
The last contribution, offered in Chapter 14, proposes an integrated end-to-
end power management approach for mobile video streaming applications
that unifies low-level architectural optimizations (e.g., CPU, memory,
registers), OS power-saving mechanisms (e.g., dynamic voltage scaling) and
adaptive middleware techniques (e.g., admission control, trans-coding,
network traffic regulation). Specifically, interaction parameters between the
different levels are identified and optimized to achieve a reduction in the
power consumption.
Closing this introductory chapter, the editor would like to thank all the
authors for their effort in producing their outstanding contributions in a very
short time. A special thank goes to Mike Thompson and Philippe
Magarshack of STMicroelectronics for their keynote presentation at DATE
2004 and for writing the foreword to this book. The editor would also like to
acknowledge the support offered by Mark De Jongh and the Kluwer staff
during the preparation of the final version of the manuscript. Last, but not
least, the editor is grateful to Agnieszka Furman for taking care of most of
the “dirty work” related to book editing, paging and preparation of the
camera-ready material.

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Chapter 1
ULTRA-LOW-POWER DESIGN: DEVICE AND
LOGIC DESIGN APPROACHES
Christoph Heer
1
and Ulf Schlichtmann
2
1
Infineon Technologies AG;
2
Technische Universität München
Abstract Power consumption increasingly is becoming the bottleneck in the design of
ICs in advanced process technologies. We give a brief introduction into the
major causes of power consumption. Then we report on experiments in an
advanced process technology with ultra-low threshold voltage (V
th
) devices. It
turns out that in contrast to older process technologies, this approach
increasingly is becoming less suitable for industrial usage in advanced process
technologies. Following, we describe methodologies to reduce power
consumption by optimizations in logic design, specifically by utilizing
multiple levels of supply voltage V
dd
and threshold voltage V
th
. We evaluate
them from an industrial product development perspective. We also give a brief
outlook to proposals on other levels in the design flow and to future work.

Keywords: Low-power design, dynamic power reduction, leakage power reduction, ultra-
low-V
th
devices, multi-V
dd
, multi-V
th
, CVS
1.1 INTRODUCTION
The progress of silicon process technology marches on relentlessly. As
predicted by Gordon Moore decades ago, silicon process technology
continues to achieve improvements at an astonishing pace [1]. The number
of transistors that can be integrated on a single IC approximately doubles
every 2 years [2,3]. This engineering success has created innovative new
industries (e.g. personal computers and peripherals, consumer electronics)
and revolutionized other industries (e.g. communications).
Today, however, it is becoming increasingly difficult to achieve
improvements at the pace that the industry has become accustomed to. More
and more technical challenges appear that require increasing resources to be
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solved [4]. One such problem is the increasing power consumption of
integrated circuits. It becomes even more critical as an increasing number of
today’s high-volume consumer products are battery-powered.
In the following, we will consider the sources of power consumption and
their development over time. We will show why reduction of power
consumption increasingly is becoming critical to product success and will
review traditional approaches in Sections 1.1 and 1.2. In Section 1.3 we will
then analyze a potential solution based on introduction of an optimized
transistor with a very low threshold voltage V

th
. Thereafter, we will present
and discuss logic-level design optimizations for power reduction in Section
1.4. Also, we will briefly point out potential optimizations on higher levels.
Our observations are made from the perspective of industrial IC product
development where technical optimizations must be carefully evaluated
against the cost associated with achieving and implementing them. Mostly,
the presented methodologies are already being utilized in leading-edge
industrial ICs.
1.2 POWER CONSUMPTION BECOMES CRITICAL
Depending on the type of end-product and its application, different
aspects of power consumption are the primary concern: dynamic power or
leakage power.
Reduction of
dynamic power consumption
is a concern for almost all
IC products today. For battery-powered products, reduced power
consumption directly results in longer operating time for the product, which
is a very desirable characteristic. Even for non-battery-powered products,
reduced power consumption brings many advantages, such as reduced cost
because of cheaper packaging or higher performance because of lower
temperatures. Finally, reduced power consumption often leads to lower
system cost (no fans required; no or cheaper air conditioning for data /
telecom center etc.).
Dynamic power consumption is caused by the charging and discharging
of capacitances when a circuit switches. In addition, during switching a
short-circuit current flows, but this current is typically much smaller, and
will therefore be neglected in the following. The dynamic current due to
capacitance charging and discharging is determined by the following well-
known relationship:

2
~
ddLdyn
VCfP ••
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Based on constant electrical field scaling, V
dd
and C
L
each are reduced by
30% in each successive process generation. Also, delay decreases by 30%,
resulting in 43% increase in frequency. Therefore, the dynamic power
consumption per device is reduced by 50% from one process generation to
the next. As scaling also doubles the number of devices that can be
implemented in a given die area, dynamic power consumption per area
should stay roughly identical. However, historically frequency has increased
by significantly more than 43% from one process generation to the next (e.g.
in microprocessors, it has roughly doubled, due to architectural
optimizations, such as deeper pipeline stages), and in addition, die sizes have
increased with each new process technology, further increasing the power
consumption, due to an increased number of active devices [5]. For these
reasons, dynamic power consumption has increased exponentially, as is
shown in Figure 1-1 for the example of microprocessors.
Reduction of
leakage power consumption
today is primarily a concern
for products that are powered by battery and spend most of their operating
hours in some type of standby mode, such as cell phones.
For many process generations, however, leakage has increased roughly

by a factor of 10 for every two process nodes [6]. Due to this dramatic
increase with newer process generations, leakage is becoming a significant
contribution to overall IC power consumption even in normal operating
mode, as can be seen in Figure 1-1 as well. Leakage was estimated to
increase from 0.01% of overall power consumption in a 1.0µm technology,
to 10% in a 0.1µm technology [6]. For a microprocessor, Intel estimated
leakage power consumption at more than 50W for a 100nm technology
node[3]. This figure probably is extreme, and leakage depends strongly on a
number of factors, such as threshold voltage (V
th
) of the transistor, gate
oxide thickness and environmental operating conditions (supply voltage V
dd
,
temperature T). Nevertheless, for an increasing number of products leakage
power consumption is turning into a problem, even when they are not
battery-powered.
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Figure 1-1. Development of dynamic and leakage power consumption over time [3,7]
1.3 TRADITIONAL APPROACHES TO POWER
REDUCTION
As outlined above, dynamic power consumption is governed by:
2
~
ddLdyn
VCfP ••
with f denoting the switching frequency, C
L
the capacitance being

switched, and V
dd
the supply voltage . This formula immediately identifies
the key levers to reduce dynamic power:
•
Reduce operating frequency
•
Reduce driven capacity
•
Reduce supply voltage
Traditionally, reduction in supply voltage V
dd
has been the most often
followed strategy to reduce power consumption. Unfortunately, lowering V
dd
has the side effect of reducing performance as well, primarily because gate
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overdrive (the difference between V
dd
and V
th
) diminishes if the threshold
voltage V
th
is kept constant. Based on the alpha power law model [8], the
delay t
d
of an inverter is given by
()

α
thdd
ddL
d
VV
VC
t
−
•
=
with
α
denoting a fitting constant. As supply voltages are driven below
1.0V, the reductions in gate overdrive are more pronounced than previously.
In addition, newer process technologies give significantly less of a
performance boost compared to the previous process generation than has
traditionally been the case, therefore a further reduction in performance is
highly undesirable. Finally, the power reduction achieved by moving to a
new process generation has trended down over time, since supply voltages
have been scaled by increasingly less than the 30% prescribed by the
constant electrical field scaling paradigm.
Consequently, more advanced approaches are required.
In the following, our main focus will be on dynamic power consumption,
but we will also consider leakage power consumption.
1.4 ZERO-V
TH
DEVICES
The concept of zero-V
th
devices was developed in the mid 90-ies. It

overcomes the diminishing gate overdrive by radically setting the threshold
voltage of the active devices to zero. It has been shown [9], that the optimum
power dissipation is obtained, if P
leak
(leakage contribution) is in the same
order of magnitude as P
dyn
(dynamic switching contribution). This can be
achieved for transistors with V
th
close to 0V (‘zero-V
th
transistor‘). Therefore
the devices will never completely switch off. But from an overall power
perspective the gain in active power consumption is tremendous.
Using these transistors the supply voltage of 130nm circuits can be
reduced to values below 0.3V to achieve a P
dyn
reduction by 90% without
performance degradation. Alternatively, the circuit can be operated at twice
the clock frequency when keeping the supply voltage at 1.2V, as shown in
Figure 1-2. The corresponding I
on
/I
off
-ratio for the zero-V
th
transistor is about
10-100 instead of >10
5

for the standard transistor options. During standby,
the complete circuits are switched-off or are set into a low leakage mode to
cope with the very high leakage contribution. The low leakage mode is
achieved by ‘active well’ control, which denotes the use of the body effect.
The well potentials of the PFETs and NFETs are altered to change V
th
. To
achieve a lower leakage current, the absolute value of V
th
is increased by
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reverse back biasing: a negative well-to-source voltage U
sb
is used.
Therefore voltages below V
ss
for NFETs and above V
dd
for PFETs have to
be generated. Furthermore, active well is required to compensate the lot-to-
lot or wafer-to-wafer variations of V
th
.
The initial ‘zero-V
th
’ concept assumed constant junction temperatures T
j
below 40°C. For some high-end computer equipment the costs for active
chip cooling are affordable to achieve this junction temperature. But this is

definitely not the case for cost-driven consumer products. For this
application domain T
j
in active mode ranges between 85°C and 125°C, and
in some applications the specified worst-case ambient temperature is even
80°C. The proposed zero-V
th
concept is therefore not applicable without
changes and adaptations.
Figure 1-2. Simulated performance curves of transistors with ultra-low V
th
. Compared to low-
V
th
, either a performance gain or a V
dd
reduction can be achieved. Curves for reg-V
th
and
high-V
th
transistors of a 130 nm technology are included
A more conservative approach with respect to zero-V
th
, but still
aggressive compared to current devices, had to be chosen. An ultra-low V
th
device with about 150mV threshold voltage proved to be the best
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compromise between zero-V
th
and current low-V
th
of about 300mV within a
130 nm CMOS technology.
To identify the optimal choice of V
th
and V
dd
in combination with the
higher junction temperature T
j
, simulations with modified parameters of the
130nm low-V
th
transistor are performed. In Figure 1-3 the power dissipation
is shown for a high activity circuit (ı= 20%) with various options for the
transistor threshold voltages: reg-V
th
, low-V
th
, and transistors whose V
th
are
reduced to 200mV, 150mV, 100mV and 50mV. The reg-V
th
circuit
performance was used as the reference (V
dd

= 1.5V), and the supply voltages
for the other transistor options were reduced to meet that reference
performance.
Device Option / Vth (mV)
Power [W]
Figure 1-3. Power dissipation at T=125°C in active mode for several transistor options with
reduced V
th
. A minimum power consumption is achieved at 150mV V
th
. (At T=55°C the
minimum is achieved for the same option but process variations show less impact).
The reduced supply voltage leads to lower overall active power
consumption P
active
. A minimum power consumption is reached at V
th
=
150mV. With even lower threshold voltages P
active
starts to increase again
because of the increase of the leakage current. The steep rise of P
active
originates from the exponential relation between V
th
and leakage current. As
a rule of thumb a 100mV reduction of the threshold voltage allows for a V
dd
0,0E+00
5,0E-06

1,0E-05
1,5E-05
2,0E-05
2,5E-05
3,0E-05
3,5E-05
reg-Vt low-Vt 200mV 150mV 100mV 50mV
T= 125°C
1.0V
1.2V
V
dd
= 1.5V
0.8V 0.7V
0.6V
fast
nom
= target
slow
7
TLFeBOOK
reduction by § 0.15V but on the other hand results in a tenfold increase of
the leakage current. From Figure 1-3 also the impact of technology
variations is visible. Due to the high leakage contribution a power reduction
of only 25% is achieved under fast process conditions. Using back biasing in
reverse mode, the high performance of fast transistors can be reduced
through increasing V
th
. The corresponding leakage current therefore
decreases and allows a power reduction by 50% (stippled arrow).

A process modification has been developed to manufacture devices with
the threshold voltage of 150 mV, which proves to be the most efficient for
the target application domain of mobile consumer products [10]. In Table1-1
the key transistor parameters of our ultra-low-Vth FETs (ulv) and of the
standard low-V
th
transistor are listed. The V
th
values are 165mV and 161mV
for the ulv-NFET and ulv-PFET respectively, I
on
increases by 35% and 22%,
which translates into an average decrease of the CV/I-metric delay by 29%.
Circuit simulations showed a performance increase of 25%. Concerning V
th
,
performance, and I
off
the target values have been nearly met.
Table 1-1. Extracted key parameters of the ulv-FETSs in comparison with the target values
and the low- V
th
FETs
130nm low-Vt
NFET / PFET
130nm ulv-FET
NFET / PFET
Target
I
on

[µA/µm]
560 / 240 755 / 295
I
off
[nA/µm]
1.2 / 1.2 48 / 17 §35
V
th
[mV]
295 / 260 165/160 150
body effect
[mV/V]
150 / 135 60/65 90
V
th
@¨L=10nm
[mV]
35 / 30 65/30
V
th
@¨L=15nm
[mV]
65 / 70 100/90
Simulated gate delay
[relative units]
1 0.8 0.75
The sensitivity of V
th
to gate length variation (roll-off) is expressed in
V

th
-shift per 10nm or 15nm gate length decrease. A comparison with low-
V
th
-FETs shows a pronounced increase. Therefore in addition to temperature
compensation, back biasing has also to be used to compensate for this strong
technology variation.
8
TLFeBOOK