nanopackaging. nanotechnologies and electronics packaging, 2008, p.553

Nanopackaging
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James E. Morris
Editor
Nanopackaging
Nanotechnologies and Electronics Packaging
Morris_FM.indd iiiMorris_FM.indd iii 9/29/2008 8:43:01 PM9/29/2008 8:43:01 PM
Editor
James E. Morris
Portland State University
Department of Electrical and Computer Engineering
1900 SW 4
th
Avenue
Portland, OR 97201
USA
ISBN 978-0-387-47325-3 e-ISBN 978-0-387-47326-0
Library of Congress Control Number: 2008923105
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Foreword
Semiconductors entered the nanotechnology era when they went below the 100 nm
technology node a few years ago. Today the industry is shipping 65 nm technology
wafers in high volume, 45 nm is in production, with 32 nm working at the develop-
ment stage. While the predictions that Moore’s Law has reached it practical limits
have been heard for years, they have proven to be premature. And it is expected
that the technology will continue to move forward unabated for some years before
it comes close to the basic physical limits to CMOS scaling.
Consumers are becoming the dominant force for electronic products. The indus-
try has learnt that the consumer market is driven by many factors other than CMOS
scaling alone. Functional diversification, accomplished through integration of mul-
tiple circuit types, and different device types, such as MEMs, optoelectronics,
chemical and biological sensors and others, provides electronic product designers
with different functional capabilities meeting the needs, wants, and tastes of con-
sumers. This functional diversification together with cost, weight, size, fashion and
appearance, and time to market, are critical differentiators in the market place.
These two technology directions are often described as “More Moore” and “More
than Moore”.
Packaging is the final manufacturing process transforming semiconductor
devices into functional products for the end user. Packaging provides electrical
connections for signal transmission, power input, and voltage control. It also pro-
vides for thermal dissipation and the physical protection required for reliability.
Packaging governs the size, weight, and shape of the end product and is the enabler
for functional diversification through package architecture and package design. In
the new landscape of advancing device technology nodes, and a dynamic consumer
market place, packaging can become either the enabling or limiting factor. This
market force has resulted in an unprecedented acceleration of innovation. Design
concepts, packaging architecture, material, manufacturing process, equipment, and

system integration technologies, are all changing rapidly.
Materials are at the heart of packaging technology. Packaging material contrib-
utes significantly to the packaged device performance, reliability and workability
as well as to the total cost of the package. With the driving forces from “More
Moore” and “More than Moore,” the challenges for packaging materials have
broadened from traditional package requirements for future generation devices to
v
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include those for new package types, such as the system in package (SiP) families,
wafer level packaging, integrated passive device (IPD), through silicon vias
(TSV), die and wafer stacking, 3D packaging, and RF, MEMs, physical, chemical
and biological sensors, and optoelectronics applications. It is believed that materi-
als in use today cannot meet the requirements of future packaging requirements.
This is particularly true for complex SiP structures where hot spots, high currents,
mechanical stresses for very thin die and ever shrinking geometries would require
electrical, thermal, and mechanical properties that are beyond those of existing
materials and manufacturing processes.
Nanomaterials and nanotechnologies promise to offer significant solutions
towards packaging technology challenges in coming years. Carbon nanotubes
(CNTs), nanowires and nanoparticles, have shown unique electrical, thermal, and
mechanical properties orders of magnitude superior to current packaging materials
used today. They had fired up the imaginations of engineers and scientists alike.
How to design the next generation packaging materials and develop materials
processing and application methodologies utilizing the nanomaterials’ unique physi-
cal properties is an important question for the electronic packaging community.
Do CNTs have a place in future generation low-dimensional thermal interface
materials (TIM), smoothing out the hot spots and taking higher levels of thermal
energy away from the die? How do we utilize the CNT electrical properties for
future generation high density packages? What role will nanoparticles play in the
new generation passives? How would macromolecules be designed into polymer

materials to provide specific electrical, thermal and mechanical properties required
for the package function? With advances on the science and technology of nano-
materials, one envisions that whole new classes of materials will be introduced into
the packaging structure to enable high power, high density interconnects, and new
package features such as embedded and integrated passives, stacked and thinned
dies, wafer level process, TSVs, MEMS, sensors, and medical and bio-chip
applications.
This book is a compendium of in depth reviews written by some of the leading
practitioners in the field. They cover the broad aspects of the field from materials
preparations, materials properties, surface modifications, engineering applications,
mathematical simulations, and “More than Moore” technical issues. It is a timely
and important contribution to the technical literature for practitioners and research-
ers in the electronic industry field.
The editor of this book is a member of the IEEE Nanotechnology Council. Many
of the contributors are from the IEEE/CPMT Society membership. They are to be
congratulated for bringing this very important topic forth in the timely manner for
the benefit of the electronic packaging and materials community.
Santa Clara, CA William T. Chen
vi Foreword
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Preface
Moore’s Law has been remarkably effective over 40 years or so in predicting the
march of CMOS technology, as device dimensions shrank to mils, to microns, to
nanometers. With continued CMOS shrinkage projected to 20 nm, there is clearly
continued life in the technology, despite past predictions of its demise which turn
out to be, like Mark Twain’s, greatly exaggerated. However, the day will clearly
come when the physical device structure cannot be supported at near atomic dimen-
sions, but despite concerted research, no obvious successor technology has yet
emerged as a clear winner. One of the factors in identifying that technology must
be consideration of packaging techniques and design for reliability. However,

package design depends on the nature of the basic device technology, and the deci-
sion process goes in circles.
However, the rapid development of nanotechnologies in almost every branch of
science and engineering is already yielding new approaches to packaging materials
and techniques, and these should be well developed and compatible for the next
generation of devices, whether they are single electron transistors, spintronics,
carbon nanotube transistors, molecular electronic devices, or something not yet
envisaged.
While the packaging of nanoelectronic devices has been slowed by uncertainty
of which device technology will turn out to be commercially viable, nanotechnolo-
gies are being developed to address current packaging problems of microelectronic
systems, with details showing up in many conference presentations, e.g., at the
annual IEEE Electronic Component and Technology Conference. However, many
experts in nanotechnologies are unaware of the possible applications in electronics
packaging, and conversely many packaging engineers are unfamiliar with the
potential of nanoscale materials and devices. This book is intended to bridge that
gap, with Chap. 1 introducing the scope of the field with a literature survey.
Then three chapters deal with computer modeling in nanopackaging. Bailey
et al. take a high-level approach to the modeling process in Chap. 2, backed up with
multiple examples of nanoscale modeling in packaging, present and future,
including nanoimprinting, solder paste printing, microwave heating, underfill, and
anisotropic conductive film. Chapter 3 from Fan and Yuen and Chap. 4 from van
der Sluis et al. both focus on the molecular modeling technique, especially for
interfacial characterization, with applications to carbon nanotube (CNT) thermal
vii
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performance, moisture diffusion and thermal cycling, and delamination failures.
The intention in each case is to understand macroscale package properties by mod-
eling at nanoscale dimensions, and emphasize the need to be able to transfer model-
ing results between software at different length scales.

The bulk of the book from here on splits naturally into nanoparticle and CNT
applications.
Morris covers fundamental metal nanoparticle properties in Chap. 5, with intro-
ductions to melting point depression, the coulomb block, interface diffusion effects,
optical absorption, sintering, etc. The references in this chapter intentionally
include many from the earliest days on nanotechnology research, to make the point
that much work was done before the current decade’s surge of interest and funding.
Nanoparticle fabrication is introduced in Chap. 6 by Hayashi et al., who concen-
trate on an ecologically friendly sonochemical technique. Other fabrication meth-
ods are touched on in other chapters, including Chaps. 7 and 14.
The next three chapters consider nanotechnologies for passive devices, which
are moving into the substrate as embedded components. The development of
nanoparticle based high-k dielectrics is covered by Lu and Wong in Chap. 7, with
consideration of the effects of both metallic and ferroelectric nanoparticles on
material performance. At higher metal loading levels, the cermet (ceramic–metal,
or polymer–metal) material becomes resistive, and cermets have been used as resis-
tors in various applications for decades. The basic principle of operation balances
the nanoscale effects of activated tunneling and percolation, as explained by Wu
and Morris in Chap. 8. Nanoparticle applications in passive components are
rounded out by the Jha et al.’s Chap. 9 on inductors and antennas, which are essen-
tial to portable wireless systems. These are generally micron-sized devices with
nanoscale features, e.g., size effects, surface roughness, and nano-granular materi-
als (for which classical theory does not match the properties).
Nanoscale engineering of isotropic conductive adhesives (ICAs) in Chap. 10, by
Lu et al., covers both nanoparticle additives (i.e., low temperature nanosintering,
CNT additives, etc.,) and enhancements by surface treatments. Chapter 11 by Das
and Egitto deals with printed wiring board (PWB) microvias, and especially nanopar-
ticle loaded fillers. Completing this group of three chapters, Felba and Schäfer cover
nanoparticle-based PWB interconnect developments in Chap. 12, including progress
toward a printable solution, and sintering (or laser sintering) of nano-Ag.

Soldering is the core technology of circuit assembly, so it is not surprising that
researchers would explore the possible benefits of nanoparticle or CNT additives.
As it turns out, Co, Ni, or Pt nanoparticles have some dramatic effects in limiting
intermetallic compound (IMC) growth and hence mechanical failure by brittle
fracture. These effects and others are covered by Amagai in Chap. 13.
Lall et al. describe the use of ceramic nanoparticle additives to lower the coeffi-
cient of thermal expansion in underfill in Chap. 14, the final chapter on nanoparti-
cles. To model this effect, they also consider the problems of random distributions,
viscoelasticity, etc.
The cluster of CNT chapters is introduced by two from the same research group.
Various CNT fabrication techniques are reviewed in Chap. 15, by Yadav et al., and
viii Preface
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then Chap. 16 follows up with a review of basic CNT properties, characterization,
and applications from Kunduru et al., who provide a primer on some device
research which parallels the work described in this book.
High thermal conductance CNT microchannel cooling is described by Liu and
Wang in Chap. 17, where they also cover the thermal conductance of CNT bumps and
a novel electro-spun thermal interface material incorporating metal nanoparticles.
High CNT conductance suggests CNT—polymer composites for light weight
electromagnetic shielding, and Cheng et al. present their work on the effectiveness
of this technique in Chap. 18.
Chapter 19 provides the CNT parallel to Chap. 13, with the account by Kumar
et al. of the results of adding CNTs to both eutectic Sn–Pb and Pb-free solders, with
the verdict that essentially every parameter of interest can be improved.
The subject moves from CNTs to nanowires in Chap. 20 by Fiedler et al. The chap-
ter includes both applications and fundamental problems, with an extensive biblio-
graphic review. Then Ma et al. introduce a novel stress-engineered cantilever technique
to form free-standing interconnect wires (or springs) in Chap. 21. Micron-scale struc-
tures are described first, before demonstrating their reduction to the nanoscale.

There is very little in the current literature about the specific packaging prob-
lems of either extreme CMOS shrinkage (to 45 nm and below) or future disruptive
nanoelectronics technologies. Chapter 22 by Mallik et al. is devoted to the shrink-
ing CMOS issue, providing historical perspective and analysis of the nm-CMOS
challenges, along with insights on the future.
Zhang rounds out the book in Chap. 23 with a broad top-down overview of future
directions of the industry as microelectronics moves to nanoelectronics, with both
“More Moore” and “More-than-Moore” applications beyond CMOS integration.
Most chapters include a focus on the authors’ own research in each respective
field, but all end with extensive reference listings. The intentions of the book are to
present an overview of each topic area, usually with the deeper treatment of one
particular aspect, and especially to provide the reader with a resource for future
study of those of interest. Hopefully, the book will pique such interest.
Portland, OR James E. Morris
Preface ix
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Contents
1 Nanopackaging: Nanotechnologies and Electronics Packaging 1
James E. Morris
2 Modelling Technologies and Applications 15
C. Bailey, H. Lu, S. Stoyanov, T. Tilford, X. Xue,
M. Alam, C. Yin, and M. Hughes
3 Application of Molecular Dynamics Simulation
in Electronic Packaging 39
Haibo Fan and Matthew M.F. Yuen
4 Advances in Delamination Modeling 61
O. van der Sluis, C.A. Yuan, W.D. van Driel, and G.Q. Zhang
5 Nanoparticle Properties 93
James E. Morris

6 Nanoparticle Fabrication 109
Y. Hayashi, M. Inoue, H. Takizawa, and K. Suganuma
7 Nanoparticle-Based High-k Dielectric Composites:
Opportunities and Challenges 121
Jiongxin Lu and C.P. Wong
8 Nanostructured Resistor Materials 139
Fan Wu and James E. Morris
9 Nanogranular Magnetic Core Inductors: Design, Fabrication,
and Packaging 163
Gopal C. Jha , Swapan K. Bhattacharya, and Rao R. Tummala
xi
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10 Nanoconductive Adhesives 189
Daoqiang Daniel Lu

, Yi Grace Li, and C P. Wong
11 Nanoparticles in Microvias 209
Rabindra N. Das and Frank D. Egitto
12 Materials and Technology for Conductive Microstructures 239
Jan Felba and Helmut Schaefer
13 A Study of Nanoparticles in SnAg-Based Lead-Free Solders 265
Masazumi Amagai
14 Nano-Underfills for Fine-Pitch Electronics 287
Pradeep Lall, Saiful Islam, Guoyun Tian, Jeff Suhling,
and Darshan Shinde
15 Carbon Nanotubes: Synthesis and Characterization 325
Yamini Yadav, Vindhya Kunduru, and Shalini Prasad
16 Characteristics of Carbon Nanotubes
for Nanoelectronic Device Applications 345
Vindhya Kunduru, Yamini Yadav, and Shalini Prasad

17 Carbon Nanotubes for Thermal Management of Microsystems 377
Johan Liu and Teng Wang
18 Electromagnetic Shielding of Transceiver Packaging
Using Multiwall Carbon Nanotubes 395
Wood-Hi Cheng, Chia-Ming Chang, and Jin-Chen Chiu
19 Properties of 63Sn-37Pb and Sn-3.8Ag-0.7Cu Solders
Reinforced With Single-Wall Carbon Nanotubes 415
K. Mohan Kumar, V. Kripesh, and Andrew A.O. Tay
20 Nanowires in Electronics Packaging 441
Stefan Fielder, Michael Zwanzig, Ralf Schmidt, and Wolfgang Scheel
21 Design and Development of Stress-Engineered
Compliant Interconnect for Microelectronic Packaging 465
Lunyu Ma, Suresh K. Sitaraman, Qi Zhu, Kevin Klein,
and David Fork
xii Contents
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22 Flip Chip Packaging for Nanoscale Silicon
Logic Devices: Challenges and Opportunities 491
Debendra Mallik, Ravi Mahajan, and Vijay Wakharkar
23 Nanoelectronics Landscape: Application,
Technology, and Economy 517
G.Q. Zhang
Index 537
Contents xiii
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Contributors
Mohammad Alam
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Masazumi Amagai
Tsukuba Technology Center, Texas Instruments, 17 Miyukigaoka,
Tsukuba-shi, Ibaragi-ken 305-0841 Japan

Chris Bailey
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Swapan K. Bhattacharya
School of Electrical and Computer Engineering, Georgia Institute of Technology,
Atlanta, GA 30332, USA

Chia-Ming Chang
Institute of Electro-Optical Engineering, National Sun Yat-sen University,
Kaohsiung 80424, Taiwan, ROC

Wood-Hi Cheng
Institute of Electro-Optical Engineering, National Sun Yat-sen University,
Kaohsiung 80424, Taiwan, ROC

Jin-Chen Chiu
Institute of Electro-Optical Engineering, National Sun Yat-sen University,
Kaohsiung 80424, Taiwan, ROC

xv
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Rabindra N. Das
Endicott Interconnect Technologies, Inc., 1093 Clark Street, Endicott,
New York, NY 13760, USA

Frank D. Egitto
Endicott Interconnect Technologies, Inc., 1093 Clark Street, Endicott, New York,
NY 13760, USA

Haibo Fan
Department of Mechanical Engineering, Hong Kong University of Science
and Technology, Clearwater Bay, N.T., Hong Kong

Jan Felba
Faculty of Microsystem Electronics and Photonics, Wroclaw University
of Technology, ul. Janiszewskiego 11/17, 50-372 Wroclaw, Poland

Stefan Fiedler
Dept. Module Integration and Board Interconnection Technologies,
Fraunhofer Institut Zuverlässigkeit und Mikrointegration (IZM),
13355 Berlin, Gustav-Meyer-Allee 25, Germany

David K. Fork
Palo Alto Research Center, 3333 Coyote Hill Rd., Palo Alto, CA 94304, USA
Yamato Hayashi
Department of Applied Chemistry, Tohoku University, 6-6-07 Aoba Aramaki,
Aoba-ku, Sendai 980-8579, Japan

Michael Hughes
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Masahiro Inoue
Nanoscience and Nanotechnology Center, The Institute of Scientific

and Industrial Research (ISIR), Osaka University, Mihogaoka 8-1, Ibaraki,
Osaka 567-0047, Japan

Saiful Islam
Intel Corporation, 5000 W. Chandler Blvd., Chandler, AZ 85226, USA

xvi Contributors
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Gopal C. Jha
Packaging Research Center, Georgia Institute of Technology,
Atlanta, GA 30332, USA

Kevin Klein
Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab,
The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332-0405, USA
Vaidyanathan Kripesh
Institute of Microelectronics, 11 Science Park Road, Science Park II,
Singapore, Singapore 117685

Katta Mohan Kumar
Nano/Microsystems Integration Laboratory, Department of Mechanical
Engineering, National University of Singapore, 9 Engineering Drive 1,
Singapore, Singapore 117576

Vindhya Kunduru
Department of Electrical & Computer Engineering, Portland State University,
FAB Suite 160, 1900 SW 4th Avenue, Portland, OR 97207-0751, USA

Pradeep Lall

Department of Mechanical Engineering, Auburn University, 270 Ross Hall,
Auburn, AL 36849, USA

Grace Li
School of Materials Science and Engineering, Georgia Institute of Technology,
771 Ferst Dr. NW, Atlanta, GA 30332, USA

Johan Liu
Bionano Systems Laboratory, Department of Microtechnology and Nanoscience,
Chalmers University of Technology, Kemivägen 9 Room A517, Se 412 96
Gothenburg, Sweden

Daniel D. Lu
Henkel Loctite (China) Co., Ltd, 90 Zhujiang Road, Yantai, ETDZ, Shandong,
China 264006

Hua Lu
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Contributors xvii
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Jiongxin Lu
Georgia Institute of Technology, Atlanta, GA, USA
Lunyu Ma
Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab,
The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology, 813 Ferst Drive, Atlanta,
GA 30332-0405, USA
Ravi Mahajan

Intel Corp, M/S CH5-157, 5000 W. Chandler Blvd., Chandler, AZ 85226, USA

Debendra Mallik
Intel Corp, M/S CH5-157, 5000 W. Chandler Blvd., Chandler, AZ 85226, USA

James E. Morris
Department of Electrical & Computer Engineering, Portland State University,
P.O. Box 751, Portland, OR 97201, USA

Shalini Prasad
Department of Electrical & Computer Engineering, Portland State University,
FAB Suite 160, 1900 SW 4th Avenue, Portland, OR 97207-0751, USA

Helmut Schaefer
Fraunhofer Institut Fertigungstechnik Materialforschung (IFAM),
Wiener Strasse 12, 28359 Bremen, Germany

Wolfgang Scheel
Department of Module Integration and Board Interconnection Technologies,
Fraunhofer Institut Zuverlässigkeit und Mikrointegration (IZM), 13355 Berlin,
Gustav-Meyer-Allee 25, Germany

Ralf Schmidt
Department of Module Integration and Board Interconnection Technologies,
Fraunhofer Institut Zuverlässigkeit und Mikrointegration (IZM), 13355 Berlin,
Gustav-Meyer-Allee 25, Germany

Darshan Shinde
Department of Mechanical Engineering, Auburn University, 270 Ross Hall,
Auburn, AL 36849, USA

xviii Contributors
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Suresh K. Sitaraman
Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab,
The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332-0405, USA

Stoyan Stoyanov
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Katsuaki Suganuma
Nanoscience and Nanotechnology Center, The Institute of Scientific and
Industrial Research (ISIR), Osaka University, Mihogaoka 8-1, Ibaraki,
Osaka 567-0047, Japan

Jeff Suhling
Department of Mechanical Engineering, Auburn University,
270 Ross Hall, Auburn, AL 36849, USA

Hirotsugu Takizawa
Department of Applied Chemistry Tohoku University, 6-6-07 Aoba Aramaki,
Aoba-ku, Sendai, 980-8579, Japan

Andrew A.O. Tay
Nano/Microsystems Integration Laboratory, Department of Mechanical
Engineering, National University of Singapore, 9 Engineering Drive 1,
Singapore

Guoyun Tian
Department of Mechanical Engineering, Auburn University,
270 Ross Hall, Auburn, AL 36849, USA

Tim Tilford
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Rao R. Tummala
Packaging Research Center, Georgia Institute of Technology, Atlanta,
GA 30332, USA

Contributors xix
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O. (Olaf) van der Sluis
Department of Precision and Microsystems Engineering, Delft University
of Technology, Mekelweg 2 2628 CD Delft, The Netherlands

and
Philips Applied Technologies, High Tech Campus 7 5656 AE Eindhoven,
The Netherlands

W.D. (Willem) van Driel
NXP Semiconductors, Gerstweg 2 6534 AE Nijmegen, The Netherlands
Department of Precision and Microsystems Engineering, Delft University
of Technology, Mekelweg 2 2628 CD Delft, The Netherlands

Vijay Wakharkar
Intel Corp, M/S- CH5-157, 5000 W. Chandler Blvd., Chandler, AZ 85226, USA

Teng Wang
Bionano Systems Laboratory, Department of Microtechnology and Nanoscience,
Chalmers University of Technology, Kemivägen 9 Room A517, Se 412 96
Gothenburg, Sweden

C P. Wong
School of Materials Science and Engineering, Georgia Institute of Technology,
771 Ferst Dr. NW, Atlanta, GA 30332, USA

Fan Wu
Zounds, Inc., 1910 S. Stapley Drive, Suite 202, Mesa, AZ 85204, USA

Xiangdiong Xue
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

Yamini Yadav
Department of Electrical & Computer Engineering, Portland State University,
FAB Suite 160, 1900 SW 4th Avenue, Portland, OR 97207-0751, USA

Chunyan Yin
School of Computing and Mathematical Sciences, University of Greenwich,
Old Royal Naval College, Greenwich, London SE10 9LS, UK

xx Contributors
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C.A. (Cadmus) Yuan
Department of Precision and Microsystems Engineering, Delft University
of Technology, Mekelweg 2, 2628 CD Delft, The Netherlands

and
NXP Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands
Matthew

M.F. Yuen
Department of Mechanical Engineering, Hong Kong
University of Science and Technology, Clearwater Bay, N.T., Hong Kong

G.Q. (Kouchi) Zhang
Department of Precision and Microsystems Engineering, Delft University
of Technology, Mekelweg 2, 2628 CD Delft, The Netherlands

and
NXP Semiconductors, High Tech Campus 60, Room 203, 5656 AG Eindhoven,
The Netherlands

Qi Zhu
Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab,
The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332-0405, USA
Michael Zwanzig
Department of Module Integration and Board Interconnection Technologies,
Fraunhofer Institut Zuverlässigkeit und Mikrointegration (IZM), 13355 Berlin,
Gustav-Meyer-Allee 25, Germany

Contributors xxi
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Chapter 1
Nanopackaging: Nanotechnologies

and Electronics Packaging
James E. Morris
1.1 Introduction
It often seems that the promise of nanotechnology’s impact on everyone’s quality
of life is as overhyped as past promises of endless cheap energy from cold fusion
and high-temperature superconductivity. But there are two major differences.
While the term “nanotechnology” has caught the attention of industry, legislators,
and research funding agencies, in most cases the technologies in question are
rooted in steady research progress in the field in question, as fabrication and char-
acterization techniques have steadily conquered ever smaller dimensions, with the
parallel development of theory to explain and model the new phenomena exposed.
Furthermore, nanotechnologies have already yielded everyday consumer benefits
beyond stain-resistant clothing and transparent sunblock. So, it is hardly surprising
to discover active research and development programs in nanotechnology applica-
tions to electronics packaging, with special nanotechnology sessions at electronics
packaging research conferences and research journal papers demonstrating the
range and progress of these applications.
The definition of nanotechnology is usually taken to be where the size of the
functional element falls below 100 nm or 0.1 µm. Of course, according to this defi-
nition, and with 45-nm CMOS in production, the nanoelectronics era is already
here. Furthermore, with metallic grain sizes typically below this limit, one might
also argue that solder has always qualified as a nanotechnology, along with many
thin film applications. So, the requirement that the specific function depends upon
this nanoscale dimension is conventionally added to the definition. According to
this caveat , MOSFET technology, for example, would not qualify by simple device
shrink, but would at dimensions permitting ballistic charge transport.
Nanotechnology drivers are the varied ways in which materials properties
change at low dimensions. Electron transport mechanisms at small dimensions
J.E. Morris
Department of Electrical & Computer Engineering , Portland State University, P.O. Box 751,

Portland , OR, 97207-0751, USA
J.E. Morris (ed.) Nanopackaging: Nanotechnologies and Electronics Packaging, 1
DOI: 10.1007/978-0-387-47326-0_1, © Springer Science + Business Media, LLC 2008
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2 J.E. Morris
include ballistic transport, severe mean free path restrictions in very small nanopar-
ticles, various forms of electron tunneling, electron hopping mechanisms, and
more. Other physical property changes include:
• Melting point depression, i.e., the reduction of metal nanoparticle melting
points at small sizes [1] , although this is unlikely to be a factor in packaging
applications with even 10% reductions typically requiring dimensions under
5 nm [2]
• Sintering by surface self-diffusion, which is thermally activated, with net diffu-
sion away from convex surfaces of high curvature [3]
• The Coulomb blockade effect, which requires an external field or thermal source
of electrostatic energy to charge an individual nanoparticle, and is the basis of
single-electron transistor operation [4]
• Theoretical maximum mechanical strengths in single grain material
structures [5]
• Unique optical scattering properties by nanoparticles that are one to two orders
smaller than the wavelength of visible light [6]
• The enhanced chemical activities of nanoparticles, which make them effective
as catalysts, and other effects of the high surface-to-volume ratio
New nanoscale characterization techniques will be applied wherever they can provide
useful information, and the atomic force microscope (AFM), for example, is rela-
tively commonly used to correlate adhesion to surface feature measurements. More
recently, confocal microscopy has been applied to packaging research [7] , but it is
especially interesting to note the development of a new instrument, such as the
atomic force acoustic microscope [8] , which adapts the AFM to the well-known
technique for package failure detection.

1.2 Computer Modeling
The use of composite materials is well established for many applications. But,
while overall effective macroscopic properties are satisfactory for computer mode-
ling of automotive body parts, for example, they are clearly inadequate for struc-
tures of dimensions similar to the particulate sizes in the composite. The modeling
of such microelectronics (or nanoelectronics) packages must include two-phase
models of the composite structure, and this general principle of inclusion of the
nanoscale structural detail in expanded material models must be extended to all
aspects of package modeling [9] . The extended computer models can be based on
either the known properties of the constituent materials (and hopefully known at
appropriate dimensions) or the measured nanoscale properties (e.g., by a nanoin-
denter [10 , 11] or AFM [12] ). Molecular Dynamics modeling software has been
particularly useful in the prediction of macroscale effects from the understanding
of nanoscale interactions [13] .
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