1 principles and elements of power electronics

BWW





Principles and Elements

of


P
OWER ELECTRONICS


Devices, Drivers, Applications, and Passive Components














Barry W Williams

B.Sc., Dipl.Eng., B.Eng., M.Eng.Sc., Ph.D., D.I.C.

Professor of Electrical Engineering
University of Strathclyde
Glasgow








Published by Barry W Williams
ISBN 978-0-9553384-0-3
© Barry W Williams
2006


Power Electronics
ii

Table of Contents






1

1
Basic Semiconductor Physics and Technology

Example 1.1: Resistance of homogeneously doped silicon 2
1.1 Processes forming and involved in forming semiconductor devices 4

1.1.1 Alloying
1.1.2 Diffused
Example 1.2: Constant Surface Concentration diffusion – predepostion 7
Example 1.3: Constant Total Dopant diffusion – drive in-1 8
Example 1.4: Constant Total Dopant diffusion – drive in-2 8
1.1.3 Epitaxy growth - deposition
1.1.4 Ion-implantation and damage annealing
Example 1.5: Ion implantation 12

1.2 Thin Film Deposition 13

1.2.1 Chemical Vapour Deposition (CVD)
1.2.2 Physical Vapour deposition (PVD)

1.3 Thermal oxidation and the masking process 17

1.4 Polysilicon deposition 20

1.5. Lithography – optical and electron 21

1.5.1 Optical Lithography
1.5.2 Electron Lithography

1.6 Etching 26

1.6.1 Wet Chemical Etching
1.6.2 Dry Chemical Etching

1.7 Lift-off Processing 32

1.8 Resistor Fabrication 32

1.9 Isolation Techniques 33

1.10 Wafer Cleaning 33

1.11 Planarization 35

1.12 Gettering 35

1.13 Lifetime control 36

1.14 Silicide formation 36

1.15 Ohmic contact 38

1.16 Glassivation 41

1.17 Back side metallisation and die separation 41

1.18 Wire bonding 41

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1.19 Types of silicon 43

1.19.1 Purifying silicon
1.19.2 Crystallinity
1.19.3 Single crystal silicon
1.19.3i Czochralski process
1.19.3ii Float-zone process
1.19.3iii Ribbon silicon
1.19.4 Multi-crystalline Silicon
1.19.5 Amorphous Silicon

1.20 Silicon Carbide 48

1.21 Si and SiC physical and electrical properties compared 48


2
51
The pn Junction

Example 2.1: Built-in potential of an abrupt junction
52

2.1 The pn junction under forward bias (steady-state) 53

2.2 The pn junction under reverse bias (steady-state) 53

2.2.1 Punch-through voltage
2.2.2 Avalanche breakdown

2.2.3 Zener breakdown

2.3 Thermal effects 54
Example 2.2: Diode forward bias characteristics
55

2.4 Models for the bipolar junction diode 55

2.4.1 Piecewise-linear junction diode model
Example 2.3: Using the pwl junction diode model
56
Example 2.4: Static linear diode model
56
2.4.2 Semiconductor physics based junction diode model
2.4.2i - Determination of zero bias junction capacitance, C
jo

2.4.2ii - One-sided pn diode equations
Example 2.5: Space charge layer parameter values 61





3
65
Power Switching Devices
and their Static Electrical Characteristics

3.1 Power diodes 65

3.1.1 The pn fast-recovery diode
3.1.2 The p-i-n diode
3.1.3 The power Zener diode
3.1.4 The Schottky barrier diode
3.1.5 The silicon carbide Schottky barrier diode
Power Electronics
iv

3.2 Power switching transistors 70

3.2.1 The bipolar npn power switching junction transistor (BJT) 70
3.2.1i - BJT gain
3.2.1ii - BJT operating states
3.2.1iii - BJT maximum voltage - first and second breakdown
3.2.2 The metal oxide semiconductor field effect transistor (MOSFET) 73
3.2.2i - MOSFET structure and characteristics
3.2.2ii - MOSFET drain current
3.2.2iii - MOSFET transconductance and output conductance
3.2.2iv - MOSFET on-state resistance
3.2.2v - MOSFET p-channel device
Example 3.1: Properties of an n-channel MOSFET cell 78
3.2.2vi - MOSFET parasitic BJT
3.2.2vii - MOSFET on-state resistance reduction
1 - Trench gate
2 - Vertical super-junction
3.2.3 The insulated gate bipolar transistor (IGBT) 81
3.2.3i - IGBT at turn-on
3.2.3ii - IGBT in the on-state
3.2.3iii - IGBT at turn-off

3.2.3iv - IGBT latch-up
1 - IGBT on-state SCR static latch-up
2 - IGBT turn-off SCR dynamic latch-up
3.2.4 Reverse blocking NPT IGBT 84
3.2.5 Forward conduction characteristics
85
3.2.6
PT IGBT and NPT IGBT comparison 85
3.2.7 The junction field effect transistor (
JFET) 85

3.3 Thyristors 86

3.3.1 The silicon-controlled rectifier (SCR)
3.3.1i - SCR turn-on
3.3.1ii - SCR cathode shorts
3.3.1iii - SCR amplifying gate
3.3.2 The asymmetrical silicon-controlled rectifier (ASCR)
3.3.3 The reverse-conducting thyristor (
RCT)
3.3.4 The bi-directional-conducting thyristor (
BCT)
3.3.5 The gate turn-off thyristor (
GTO)
3.3.5i - GTO turn-off mechanism
3.3.6 The gate commutated thyristor (GCT)
3.3.6i - GCT turn-off
3.3.6ii - GCT turn-on
3.3.7 The light triggered thyristor (LTT)
3.3.8 The triac

3.4 Power packages and modules 98




4
101
Electrical Ratings and Characteristics
of Power Semiconductor Switching Devices

4.1 General maximum ratings of power switching semiconductor devices 101

4.1.1 Voltage ratings
4.1.2 Forward current ratings
4.1.3 Temperature ratings
4.1.4 Power ratings
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4.2 The fast-recovery diode 103

4.2.1 Turn-on characteristics
4.2.2 Turn-off characteristics
4.2.3 Schottky diode dynamic characteristics

4.3 The bipolar, high-voltage, power switching npn junction transistor 106

4.3.1 Transistor ratings

4.3.1i - BJT collector voltage ratings
4.3.1ii - BJT safe operating area (SOA)
4.3.2 Transistor switching characteristics

4.3.2i - BJT turn-on time
4.3.2ii - BJT turn-off time
4.3.3 BJT phenomena

4.4 The power MOSFET 111

4.4.1 MOSFET absolute maximum ratings
4.4.2 Dynamic characteristics
4.4.2i - MOSFET device capacitances
4.4.2ii - MOSFET switching characteristics
1 - MOSFET turn-on
2 - MOSFET turn-off
Example 4.1: MOSFET drain characteristics 116

4.5 The insulated gate bipolar transistor 117

4.5.1 IGBT switching
4.5.2
IGBT short circuit operation

4.6 The thyristor 119

4.6.1 SCR ratings
4.6.1i - SCR anode ratings
4.6.1ii - SCR gate ratings
4.6.2 Static characteristics

4.6.2i - SCR gate trigger requirements
4.6.2ii - SCR holding and latching currents
4.6.3 Dynamic characteristics
4.6.3i - SCR anode at turn-on
4.6.3ii - SCR anode at turn-off

4.7 The gate turn-off thyristor 122

4.7.1 Turn-on characteristics
4.7.2 Turn-off characteristics

4.8 Appendix: Effects on MOSFET switching of negative gate drive 124





5
125
Cooling of Power Switching Semiconductor Devices


5.1 Thermal resistances 128

5.2 Contact thermal resistance 128

5.2.1 Thermal Interface Materials
5.2.2 Phase Change Gasket Materials (solid to liquid)

5.3 Heat-sinking thermal resistance 132

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5.4 Modes of power dissipation 136

5.4.1 Steady-state response
5.4.2 Pulse response
Example 5.1: Semiconductor single power pulse capability
139
Example 5.2: A single rectangular power pulse 141
5.4.3 Repetitive transient response
Example 5.3: Semiconductor transient repetitive power capability
142
Example 5.4: Composite rectangular power pulses 143
Example 5.5: Non-rectangular power pulses 145

5.5 Average power dissipation 148

5.5.1 Graphical integration
5.5.2 Practical superposition

5.6 Power losses from manufacturers’ data sheets 148

5.6.1 Switching transition power loss, P
s

5.6.2 Off-state leakage power loss,
A
P
5.6.3 Conduction power loss, P

c
5.6.4 Drive input device power loss, P
G


5.7 Heat-sinking design cases 150

5.7.1 Heat-sinking for diodes and thyristors

5.7.1i - Low-frequency switching
5.7.1ii - High-frequency switching
Example 5.6: Heat-sink design for a diode 152
5.7.2 Heat-sinking for
IGBTs
Example 5.7: Heat-sink design for an IGBT -
repetitive operation at a high duty cycle 153
5.7.3 Heat-sinking for power MOSFETs
Example 5.8:
Heat-sink for a MOSFET - repetitive operation at high peak current, low duty cycle 154
Example 5.9: Heat-sink design for a mosfet - repetitive operation at high duty cycle 155
Example 5.10: Two thermal elements on a common heatsink
155
Example 5.11: Six thermal elements in a common package
156

5.8 High-performance cooling for power electronics 157

5.9 Conduction and heat spreading 157

5.10 Heat-sinks 159

5.10.1 Required heat-sink thermal resistance
5.10.2 Heat-sink selection
5.10.3 Heat sink types
5.10.4 Heatsink fin geometry
5.10.5 Thermal performance graph

5.11 Heatsink cooling enhancements 166

5.12 Heatsink fan and blower cooling 166

5.12.1 Fan selection
5.12.2 The fan Laws
Example 5.12: Fan laws
173
5.12.3 Estimating fan life
Example 5.13: Fan lifetime
177
Example 5.14: Fan testing
178

5.13 Enhanced air cooling 179

5.14 Liquid coolants for power electronics cooling 180

5.14.1 Requirements for a liquid coolant
5.14.2 Dielectric liquid coolants
5.14.3 Non-dielectric liquid coolants

5.15 Direct and indirect liquid cooling 184

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5.16 Indirect liquid cooling 184

5.16.1 Heat pipes – indirect cooling
Example 5.15: Heat-pipe
191
5.16.2 Cold plates – indirect cooling
Example 5.16: Cold plate design
199

5.17 Direct liquid cooling 200

5.17.1 Immersion cooling – direct cooling
5.17.2 Liquid jet impingement – direct cooling
5.17.3 Spray cooling – direct cooling

5.18 Microchannels and minichannels 205

5.19 Electrohydrodynamic and electrowetting cooling 207

5.20 Liquid metal cooling 208

5.21 Solid state cooling 209

5.21.1 Thermoelectric coolers
Example 5.17: Thermoelectric cooler design
210

Example 5.18: Thermoelectrically enhanced heat sink
211
5.21.2 Superlattice and heterostructure cooling
5.21.3 Thermionic and thermotunnelling cooling

5.22 Cooling by phase change 215

5.23 Appendix: Comparison between aluminium oxide and aluminium nitride 217

5.24 Appendix: Properties of substrate and module materials 219

5.25 Appendix: Emissivity and heat transfer coefficient 221

5.26 Appendix: Ampacities and mechanical properties of rectangular copper busbars 223

5.27 Appendix: Isolated substrates for power modules 224



6
229
Load, Switch, and Commutation Considerations

6.1 Load types 229

6.1.1 The resistive load
Example 6.1: Resistive load switching losses
232
Example 6.2: Transistor switching loss for non-linear electrical transitions
233

6.1.2 The inductive load
Example 6.3: Zener diode, switch voltage clamping
235
Example 6.4: Inductive load switching losses
239
6.1.3 Diode reverse recovery with an inductive load
Example 6.5: Inductive load switching losses with device models
240

6.2 Switch characteristics 242

6.3 Switching classification 242

6.3.1 Hard switching
6.3.2 Soft switching
6.3.3 Resonant switching
6.3.4 Naturally-commutated switching

6.4 Switch configurations 244

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7
247
Driving Transistors and Thyristors

7.1 Application of the power MOSFET and IGBT 247

7.1.1 Gate drive circuits
7.1.1i - Negative gate drive

7.1.1ii - Floating power supplies
1 - capacitive coupled charge pump
2 - diode bootstrap
7.1.2 Gate drive design procedure
Example 7.1: MOSFET input capacitance and switching times
255

7.2 Application of the Thyristor 255

7.2.1 Thyristor gate drive circuits
i. Vacuum cleaner suction control circuit
ii. Lamp dimmer circuit
iii. Back EMF feedback circuits

7.2.2 Thyristor gate drive design
Example 7.2: A light dimmer
263

7.3 Drive design for GCT and GTO thyristors 264



8
267
Protecting Diodes, Transistors, and Thyristors

8.1 The non-polarised R-C snubber 268

8.1.1 R-C switching aid circuit for the GCT, the MOSFET, and the diode
Example 8.1: R-C snubber design for

MOSFETs 269
8.1.2 Non-polarised R-C snubber circuit for a converter grade thyristor and a triac
Example 8.2: Non-polarised R-C snubber design for a converter grade thyristor
271

8.2 The soft voltage clamp 272

Example 8.3: Soft voltage clamp design 273

8.3 Polarised switching-aid circuits 275

8.3.1 The polarised turn-off snubber circuit - assuming a linear current fall
8.3.2 The turn-off snubber circuit - assuming a cosinusoidal current fall
Example 8.4: Capacitive turn-off snubber design
282
8.3.3 The polarised turn-on snubber circuit - with air core (non-saturable) inductance
Example 8.5: Turn-on air-core inductor snubber design
288
8.3.4 The polarised turn-on snubber circuit - with saturable ferrite inductance
Example 8.6: Turn-on ferrite-core saturable inductor snubber design
291
8.3.5 The unified turn-on and turn-off snubber circuit

8.4 Snubbers for bridge legs 294

8.5 Appendix: Non-polarised turn-off R-C snubber circuit analysis 297

8.6 Appendix: Polarised turn-off R-C-D switching aid circuit analysis 298

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9
303
Switching-aid Circuits with Energy Recovery

9.1 Energy recovery for inductive turn-on snubber circuits-single ended 303

9.1.1 Passive recovery
9.1.2 Active recovery

9.2 Energy recovery for capacitive turn-off snubber circuits-single ended 307

9.2.1 Passive recovery
9.2.2 Active recovery

9.3 Unified turn-on and turn-off snubber circuit energy recovery 314

9.3.1 Passive recovery
9.3.2 Active recovery

9.4 Inverter bridge legs 320

9.4.1 Turn-on snubbers
9.4.2 Turn-on and turn-off snubbers

9.5 Snubbers for multi-level inverters 323

9.5.1 Snubbers for the cascaded H-bridge multi-level inverter
9.5.2 Snubbers for the diode-clamped multi-level inverter
9.5.3 Snubbers for the flying-capacitor clamped multi-level inverter

9.6 Snubbers for series connected devices 324

9.6.1 Turn-off snubber circuit active energy recovery
9.6.2 Turn-on snubber circuit active energy recovery
9.6.3 Turn-on and turn-off snubber circuit active energy recovery
9.6.4 General active recovery concepts

9.7 Snubber energy recovery for magnetically coupled based switching circuits
331
9.7.1 Passive recovery
9.7.2 Active recovery


9.8 General passive snubber energy recovery concepts 333



10
339
Device Series and Parallel Operation, Protection,
and Interference

10.1 Parallel and series connection and operation of power semiconductor devices 339

10.1.1 Series semiconductor device operation
10.1.1i - Steady-state voltage sharing
Example 10.1: Series device connection – static voltage balancing 341
10.1.1ii - Transient voltage sharing
Example 10.2: Series device connection – dynamic voltage balancing 344
10.1.2 Parallel semiconductor device operation

10.1.2i - Matched devices
10.1.2ii - External forced current sharing
Example 10.3: Resistive parallel current sharing – static current balancing 347
(a) current sharing analysis for two devices:– r
o
=

0
(b) current sharing analysis for two devices:– r
o
≠

0
(c) current sharing analysis for n devices:– r
o
=

0
Example 10.4: Transformer current sharing–static and dynamic current balancing 352

Power Electronics
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10.2 Protection overview - over-voltage and over-current 353

10.2.1 Ideal secondary level protection
10.2.2 Overvoltage protection devices
10.2.3 Over-current protection devices

10.3 Over-current Protection 356

10.3.1 Protection with fuses
10.3.1i - Pre-arcing I
2
t
10.3.1ii - Total I
2
t let-through
10.3.1iii - Fuse link and semiconductor I
2
t co-ordination
10.3.1iv - Fuse link derating and losses
Example 10.5: AC circuit fuse link design 364
10.3.1v – Pulse derating
Example 10.6: AC circuit fuse link design for I
2
t surges 366
10.3.1vi
- Other fuse link derating factors
Example 10.7: AC circuit fuse link derating 367
10.3.1vii -
Fuse link dc operation
Example 10.8: DC circuit fuse link design 369

10.3.1viii - Alternatives to dc fuse operation
10.3.2 Protection with resettable fuses
10.3.2i Polymeric PTC devices
10.3.2ii Ceramic PTC devices
Example 10.9: Resettable ceramic fuse design 379
10.3.3 Summary of over-current limiting devices

10.4 Overvoltage 381

10.4.1 Transient voltage suppression devices
10.4.1i - Comparison between Zener diodes and varistors
Example 10.10: Non-linear voltage clamp 388
10.4.2 Transient voltage fold-back devices
10.4.2i The surge arrester
10.4.2ii Thyristor voltage fold-back devices
10.4.2iii Polymeric voltage variable material technologies
10.4.2iv The crowbar
10.4.3 Coordination protection
10.4.4 Summary of voltage protection devices

10.5 Interference 397

10.5.1 Noise

10.5.1i - Conducted noise
10.5.1ii - Radiated electromagnetic field coupling
10.5.1iii - Electric field coupling
10.5.1iv - Magnetic field coupling
10.5.2 Mains filters
10.5.3 Noise filtering precautions

10.6 Earthing 400

11
403
Naturally Commutating AC to DC Converters
- Uncontrolled Rectifiers

11.1 Single-phase uncontrolled converter circuits - ac rectifiers 403

11.1.1 Half-wave circuit with a resistive load, R
11.1.2 Half-wave circuit with a resistive and back emf R-E load
Example 11.1: Half-wave rectifier with resistive and back emf load
405
11.1.3 Single-phase half-wave circuit with an R-L load
11.1.3i - Inductor equal voltage area criterion
11.1.3ii - Load current zero slope criterion
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11.1.4x Half-wave rectifier circuit with a R load and capacitor filter
Example 11.2: Half-wave rectifier with source resistance
410
11.1.4 Single-phase half-wave circuit with an R-L load and freewheel diode
Example 11.3: Half-wave rectifier – with load freewheel diode
414
11.1.5 Single-phase full-wave bridge rectifier circuit with a resistive load, R
11.1.6 Single-phase full-wave bridge rectifier circuit with a resistive and back emf load
Example 11.4:
Full-wave rectifier with resistive and back emf load 417

11.1.7 Single-phase full-wave bridge rectifier circuit with an R-L load

11.1.7i - Single-phase full-wave bridge rectifier circuit with an output L-C filter
11.1.7ii Single-phase, full-wave bridge rectifier circuit with an R-L-E load
Example 11.5:
Full-wave diode rectifier with L-C filter and continuous load current 423
11.1.7ii - Single-phase full-wave bridge rectifier with highly inductive loads–
constant load current
11.1.7iii - Single-phase full-wave bridge rectifier circuit with a C-filter and resistive load
Example 11.6: Single-phase full-wave bridge circuit with C-filter and resistive load 426
11.1.7iv - Other single-phase bridge rectifier circuit configurations

11.2 Three-phase uncontrolled rectifier converter circuits 428

11.2.1 Three-phase half-wave rectifier circuit with an inductive R-L load
11.2.2 Three-phase full-wave rectifier circuit with an inductive R-L load

11.2.2i - Three-phase full-wave bridge rectifier circuit with continuous load current
11.2.2ii - Three-phase full-wave bridge rectifier circuit with highly inductive load
11.2.2iii Three-phase full-wave bridge circuit with highly inductive load with an EMF source
11.2.2iv Three-phase full-wave bridge circuit with capacitively filtered load resistance

Example 11.7: Three-phase full-wave rectifier 435
Example 11.8: Rectifier average load voltage 436

11.3 DC MMFs in converter transformers 437

11.3.1 Effect of multiple coils on multiple limb transformers
11.3.2 Single-phase toroidal core mmf imbalance cancellation – zig-zag winding
11.3.3 Single-phase transformer connection, with full-wave rectification

11.3.4 Three-phase transformer connections
11.3.5 Three-phase transformer, half-wave rectifiers - core mmf imbalance
11.3.6 Three-phase transformer with hexa-phase rectification, mmf imbalance
11.3.7 Three-phase transformer mmf imbalance cancellation – zig-zag winding
11.3.8 Three-phase transformer full-wave rectifiers – zero core mmf

11.4 Voltage multipliers 462

11.4.1 Half-wave series multipliers
11.4.2 Half-wave parallel multipliers
11.4.3 Full-wave series multipliers
Example 11.9: Half-wave voltage multiplier
466
Example 11.10: Full-wave voltage multiplier
467
11.4.4 Three-phase voltage multipliers
11.4.5 Series versus parallel voltage multipliers

11.5 Marx voltage generator 467

11.6 Definitions 469

11.7 Output pulse number 470

11.8 AC-dc converter generalised equations 470


12
477
Naturally Commutating AC to DC Converters

- Controlled Rectifiers

Power Electronics
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12.1 Single-phase full-wave half-controlled converter 478

12.1.1i - Discontinuous load current
12.1.1ii - Continuous load current
12.1.2 Single-phase, full-wave, half-controlled circuit with R-L and emf load, E

12.2 Single-phase controlled thyristor converter circuits 485

12.2.1 Single-phase half-wave circuit with an R-L load
12.2.1i - Case 1: Purely resistive load
12.2.1ii - Case 2: Purely inductive load
12.2.1iii - Case 3: Back emf E and R-L load
Example 12.1: Half-wave controlled rectifier 489
12.2.2 Single-phase half-wave half-controlled

12.2.2i - discontinuous conduction
12.2.2ii - continuous conduction
12.2.3 Single-phase full-wave controlled rectifier circuit with an R-L load
12.2.3i -
, -
α
φβα π
><, discontinuous load current
12.2.3ii -
, -
α

φβα π
==, verge of continuous load current
12.2.3iii -
α
φ
< , β- π = α, continuous load current (and also purely inductive load)
12.2.3iv Resistive load, β

=

π
Example 12.2: Controlled full-wave converter – continuous and discontinuous conduction 495
12.2.4 Single-phase full-wave, fully-controlled circuit with R-L and emf load, E
12.2.4i - Discontinuous load current
12.2.4ii - Continuous load current
Example 12.3: Controlled converter - continuous conduction and back emf 502
Example 12.4: Controlled converter – constant load current, back emf, and overlap 503

12.3 Three-phase half-controlled converter 503

12.3i - α ≤ ⅓π
12.3ii - α ≥ ⅓π

12.4 Three-phase fully-controlled thyristor converter circuits 506

12.4.1 Three-phase half-wave, fully controlled circuit with an inductive load
12.4.2 Three-phase half-wave converter with freewheel diode

12.4.2i - α < π/6
12.4.2ii - α > π/6

12.4.2iii - α > 5π/6
Example 12.5: Three-phase half-wave rectifier with freewheel diode 508
12.4.3 Three-phase full-wave fully-controlled circuit with an inductive load
12.4.3i - Resistive load
12.4.3ii - Highly inductive load – constant load current
12.4.3iii - R-L load with load EMF, E
Example 12.6: Three-phase full-wave controlled rectifier with constant output current 514
12.4.4 Three-phase full-wave converter with freewheel diode
Example 12.7: Converter average load voltage
517

12.7 Overlap 518

12.6 Overlap – inversion 522

Example 12.8: Converter overlap 523

12.7 Summary 524

(i) Half-wave and full-wave, fully-controlled converter
(ii) Full-wave, half-controlled converter
(iii) Half-wave and full-wave controlled converter with load freewheel diode

12.8 Definitions 526

12.9 Output pulse number 526

12.10 AC-dc converter generalised equations 528

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xiii
13
537
AC Voltage Regulators

13.1 Single-phase ac regulator 537

13.1.1 Single-phase ac regulator – phase control with line commutation
Case 1:
α
φ
>

Case 2:
α
φ
≤

13.1.1i - Resistive Load
13.1.1ii - Pure inductive Load
13.1.1iii - Load sinusoidal back emf
13.1.1iv - Semi-controlled single-phase ac regulator
Example 13.1a: Single-phase ac regulator – 1 547
Example 13.1b: Single-phase ac regulator - 2
549
Example 13.1c: Single-phase ac regulator – pure inductive load

549
Example 13.1d: Single-phase ac regulator – 1 with ac back emf composite load 551

13.1.2 Single-phase ac regulator – integral cycle control – line commutated
Example 13.2: Integral cycle control
554
13.1.3 The solid-state relay (SSR)
13.1.3i Principle of operation
13.1.3ii Key power elements in solid-state relays
13.1.3iii Solid-state relay overvoltage fault modes
13.1.3iv Standard transient voltage protection devices, reviewed in terms of SSR requirements
13.1.3v Solid-state relay internal protection methods
13.1.3vi Application considerations
Example 13.3: Solid-state relay turn-on 563
Example 13.4: Solid-state relay heatsink requirements
563
13.1.3vii DC output solid-state relays

13.2 Single-phase transformer tap-changer – line commutated 565

Example 13.5: Tap changing converter 567

13.3 Single-phase ac chopper regulator – commutable switches 568

13.4 Three-phase ac regulator 570

13.4.1 Fully-controlled three-phase ac regulator with wye load and isolated neutral
Purely resistive load

i. 0 ≤ α ≤ ⅓π [mode 3/2]
ii. ⅓π ≤ α ≤ ½π [mode 2/2]
iii. ½π ≤ α ≤


π [mode 2/0]
Inductive-resistive load
Purely inductive load
i. ½π ≤ α ≤ ⅔π [mode 3/2]
ii. ⅔π ≤ α ≤

π

[mode 2/0]
13.4.2 Fully-controlled three-phase ac regulator with wye load and neutral connected
13.4.3 Fully-controlled three-phase ac regulator with delta load
13.4.4 Half-controlled three-phase ac regulator
Resistive load
i. 0 ≤ α ≤½π
ii. ½π ≤ α ≤ ⅔π
iii. ⅔π ≤ α ≤ 7π/6
Purely inductive load
13.4.5 Other thyristor three-phase ac regulators
i. Delta connected fully controlled regulator
ii. Three-thyristor delta connected regulator
Example 13.6: Star-load three-phase ac regulator
– untapped neutral 583
13.4.6 Solid-state soft starters
13.4.6i The induction motor
13.4.6ii Background to induction machine starting
13.4.6iii Solid-state soft-starter
13.4.6iv Soft-starter control and application

13.5 Cycloconverter 599
Power Electronics

xiv

13.6 The matrix converter 601

13.6.1 High frequency resonant dc to ac matrix converter

13.7 Power Quality: load efficiency and supply current power factor 607

13.7.1 Load waveforms
13.7.2 Supply waveforms
Example 13.7: Power quality - load efficiency 609
Example 13.8: Power quality -
sinusoidal source and constant current load 610
Example 13.9: Power quality - sinusoidal source and non-linear load 610



14
613
DC Choppers

14.1 DC chopper variations 613

14.2 First Quadrant dc chopper 614

14.2.1 Continuous load current
Steady-state time domain analysis of first quadrant chopper
- with load back emf and continuous output current
i. Fourier coefficients
ii. Time domain differential equations

14.2.2 Discontinuous load current
Steady-state time domain analysis of first quadrant chopper
- with load back emf and discontinuous output current
i. Fourier coefficients
ii. Time domain differential equations
Example 14.1: DC chopper (first quadrant) with load back emf 622
Example 14.2: DC chopper with load back emf - verge of discontinuous conduction
626
Example 14.3: DC chopper with load back emf - discontinuous conduction
627

14.3 Second Quadrant dc chopper 630

14.3.1 Continuous load inductor current
14.3.2 Discontinuous load inductor current
Example 14.4: Second quadrant DC chopper - continuous inductor current
635

14.4 Two quadrant dc chopper - Q I and Q II 637

Example 14.5: Two quadrant DC chopper with load back emf 640

14.5 Two quadrant dc chopper – Q 1 and Q IV 644

14.5.1 dc chopper: – Q I and Q IV – multilevel output voltage switching (three level)
14.5.2 dc chopper: – Q I and Q IV – bipolar voltage switching (two level)
14.5.3 Multilevel output voltage states, dc chopper
Example 14.6: Asymmetrical, half H-bridge, dc chopper
649

14.6 Four quadrant dc chopper 651

14.6.1 Unified four quadrant dc chopper - bipolar voltage output switching
14.6.2 Unified four quadrant dc chopper - multilevel voltage output switching
Example 14.7: Four quadrant dc chopper 658





Power Electronics

xv
15
661
DC to AC Inverters - Switched Mode

15.1 dc-to-ac voltage-source inverter bridge topologies 661

15.1.1 Single-phase voltage-source inverter bridge
15.1.1i - Square-wave (bipolar) output
15.1.1ii - Quasi-square-wave (multilevel) output
Example 15.1: Single-phase H-bridge with an L-R load 657
Example 15.2: H-bridge inverter ac output factors
668
Example 15.3: Harmonic analysis of H-bridge with an L-R load
670
Example 15.4: Single-phase half-bridge with an L-R load
671

15.1.1iii - PWM-wave output
15.1.2 Three-phase voltage-source inverter bridge
15.1.2i - 180° (π) conduction
15.1.2ii - 120° (⅔π) conduction
15.1.3 Inverter ac output voltage and frequency control techniques
15.1.3i - Variable voltage dc link
15.1.3ii - Single-pulse width modulation
Example 15.5: Single-pulse width modulation 681
15.1.3iii - Multi-pulse width modulation
15.1.3iv - Multi-pulse, selected notching modulation – selected harmonic elimination
15.1.3v - Sinusoidal pulse-width modulation (pwm)
1 - Natural sampling
2 - Regular sampling
3 - Frequency spectra of pwm waveforms
15.1.3vi - Phase dead-banding
15.1.3vii - Triplen Injection modulation
1 - Triplens injected into the modulation waveform
2 - Voltage space vector pwm
15.1.4 Common mode voltage
15.1.5 DC link voltage boosting

15.2 dc-to-ac controlled current-source inverters 698

15.2.1 Single-phase current source inverter
15.2.2 Three-phase current source inverter

15.3 Multi-level voltage-source inverters 702

15.3.1 Diode clamped multilevel inverter
15.3.2 Flying capacitor multilevel inverter

15.3.3 Cascaded H-bridge multilevel inverter
15.3.4 Capacitor clamped multilevel inverter
15.3.5 PWM for multilevel inverters
15.3.4i - Multiple offset triangular carriers
15.3.4ii - Multilevel rotating voltage space vector

15.4 Reversible dc link converters 712

15.4.1 Independent control
15.4.2 Simultaneous control
15.4.3 Inverter regeneration

15.5 Standby inverters and uninterruptible power supplies 715

15.5.1 Single-phase UPS
15.5.2 Three-phase UPS

15.6 Power filters 717





Power Electronics
xvi
16
719
DC to AC Inverters - Resonant Mode

16.1 Resonant dc-ac inverters 719

16.2 L-C resonant circuits 720
16.2.1 - Series resonant L-C-R circuit
16.2.2 - Parallel resonant L-C-R circuit

16.3 Series resonant inverters 724
16.3.1 - Series resonant inverter – single inverter leg
1 - Lagging operation (advancing the switch turn-off angle)
2 - Leading operation (delaying the switch turn-on angle)
16.3.2 - Series resonant inverter – H-bridge voltage-source inverter
16.3.3 - Circuit variations

16.4 Parallel-resonant voltage-source inverter – single inverter leg 728

16.5 Series-parallel-resonant voltage-source inverter – single inverter leg 729

Summary of voltage source resonant inverters

16.6 Parallel resonant current-source inverters 731

16.6.1 - Parallel resonant inverter – single inverter leg
16.6.2 - Parallel resonant inverter – H-bridge current-source inverter
Example 16.1: Half-bridge with a series L-C-R load 733

16.7 Single-switch, current source, series resonant inverter 736


17
739
DC to DC Converters - Switched Mode

17.1 The forward converter 740

17.1.1 Continuous inductor current
17.1.2 Discontinuous inductor current
17.1.3 Load conditions for discontinuous inductor current
17.1.4 Control methods for discontinuous inductor current
17.1.4i - fixed on-time t
T
, variable switching frequency f
var

17.1.4ii - fixed switching frequency f
s
, variable on-time t
Tvar

17.1.5 Output ripple voltage
Example 17.1: Buck (step-down forward) converter
745
17.1.6 Underlying operational mechanisms of the forward converter
Example 17.2: Hysteresis controlled buck converter
752

17.2 Flyback converters 753

17.3 The boost converter 754

17.3.1 Continuous inductor current
17.3.2 Discontinuous capacitor charging current in the switch off-state

17.3.3 Discontinuous inductor current
17.3.4 Load conditions for discontinuous inductor current
17.3.5 Control methods for discontinuous inductor current

17.3.5i - fixed on-time t
T
, variable switching frequency f
var

17.3.5ii - fixed switching frequency f
s
, variable on-time t
Tvar

17.3.6 Output ripple voltage
Example 17.3: Boost (step-up flyback) converter
758
Example 17.4: Alternative boost (step-up flyback) converter
760
Power Electronics

xvii

17.4 The buck-boost converter 762

17.4.1 Continuous choke (inductor) current
17.4.2 Discontinuous capacitor charging current in the switch off-state
17.4.3 Discontinuous choke current

17.4.4 Load conditions for discontinuous inductor current

17.4.5 Control methods for discontinuous inductor current
17.4.5i - fixed on-time t
T
, variable switching frequency f
var

17.4.5ii - fixed switching frequency f
s
, variable on-time t
Tvar

17.4.6 Output ripple voltage
17.4.7 Buck-boost, flyback converter design procedure
Example 17.5: Buck-boost flyback converter
767

17.5 Flyback converters – a conceptual assessment 769

17.6 The output reversible converter 772

17.6.1 Continuous inductor current
17.6.2 Discontinuous inductor current
17.6.3 Load conditions for discontinuous inductor current
17.6.4 Control methods for discontinuous inductor current
17.6.4i - fixed on-time t
T
, variable switching frequency f
var

17.6.4ii - fixed switching frequency f

s
, variable on-time t
Tvar

Example 17.6: Reversible forward converter 775
17.6.5 Comparison of the reversible converter with alternative converters


17.7 The Ćuk converter 777

17.7.1 Continuous inductor current
17.7.2 Discontinuous inductor current

17.7.3 Optimal inductance relationship
17.7.4 Output voltage ripple
Example 17.7: Cuk converter 779

17.8 Comparison of basic converters 780

17.8.1 Critical load current
17.8.2 Bidirectional converters
17.8.3 Isolation

17.8.3i - The isolated output, forward converter
17.8.3ii - The isolated output, flyback converter
Example 17.8: Transformer coupled flyback converter 786
Example 17.9: Transformer coupled forward converter
788

17.9 Multiple-switch, balanced, isolated converters 790

17.9.1 The push-pull converter
17.9.2 Bridge converters

17.10 Basic generic smps transfer function mapping 793

17.11 Appendix: Analysis of non-continuous inductor current operation 795

Operation with constant input voltage, E
i

Operation with constant output voltage, v
o




18
813
DC to DC Converters - Resonant Mode

18.1 Series loaded resonant dc to dc converters 814

18.1.1 Modes of operation - series resonant circuit
18.1.2 Circuit variations

Power Electronics
xviii
18.2 Parallel loaded resonant dc to dc converters 819

18.2.1 Modes of operation- parallel resonant circuit
18.2.2 Circuit variations

18.3 Series–parallel load resonant dc to dc converters 822
18.3.1 LCC resonant tank circuit
18.3.2 LLC resonant tank circuit

18.4 Resonant coupled-load configurations 825

Example 18.1: Transformer-coupled, series-resonant, dc-to-dc converter 827

18.5 Resonant switch, dc to dc step-down voltage converters 829

18.5.1 Zero-current, resonant-switch, dc-to-dc converter
-½ wave, C
R
parallel with load version
18.5.1i - Zero-current, full-wave resonant switch converter
18.5.2 Zero-current, resonant-switch, dc-to-dc converter
-
½ wave, C
R
parallel with switch version
18.5.3 Zero-voltage, resonant-switch, dc-to-dc converter
-½ wave, C
R
parallel with switch version
18.5.3i - Zero-voltage, full-wave resonant switch converter
18.5.4 Zero-voltage, resonant-switch, dc-to-dc converter
-½ wave, C

R
parallel with load version
Example 18.2: Zero-current, resonant-switch, dc-to-dc converter - ½ wave
842
Example 18.3: Zero-current, resonant-switch, dc-to-dc converter - full-wave
844
Example 18.4: Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave
845

18.6 Resonant switch, dc to dc step-up voltage converters 846

18.6.1 ZCS resonant-switch, dc-to-dc step-up voltage converters
18.6.2 ZVS resonant-switch, dc-to-dc step-up voltage converters

Summary and comparison of ZCS and ZVS Converters

18.7 Appendix: Matrices of resonant switch buck, boost, and buck/boost converters 850




19
855
HV Direct-Current Transmission

19.1 HVDC electrical power transmission 855

19.2 HVDC Configurations 856

19.2i - Monopole and earth return

19.2ii - Bipolar
19.2iii - Tripole
19.2iv - Back-to-back
19.2v - Multi-terminal

19.3 Typical HVDC transmission system 857

19.4 Twelve-pulse ac line frequency converters 858

19.4.1 Rectifier mode
19.4.2 Inverter mode

19.5 Twelve-pulse ac line frequency converter operation control 866

19.5.1 Control and protection
19.5.2 HVDC Control objectives

Power Electronics

xix
19.6 Filtering and power factor correction 870

Example 19.1: Basic six-pulse converter based hvdc transmission 870
Example 19.2: 12-pulse hvdc transmission 871

19.7 VSC-Based HVDC 873

19.7.1 VSC-Based HVDC control
19.7.2 Power control concept

19.8 HVDC Components 877

Example 19.3: HVDC transmission with voltage source controlled dc-link 878

19.9 Twelve-pulse transformer based HVDC 880

19.10 HVDC VSC Features 881

19.11 Features of conventional HVDC and HVAC transmission 881




20
883
FACTS Devices and Custom Controllers


20.1 Flexible AC Transmission Systems - FACTS 883

20.2 Power Quality 884

20.3 Principles of Power Transmission 884

Example 20.1: AC transmission line VAr 886

20.4 The theory of instantaneous power in three-phase 887

20.5 FACTS Devices 890

20.6 Static Reactive Power Compensation 891

20.7 Static Shunt Reactive Power Compensation 892

20.7.1 - Thyristor controlled reactor TCR
20.7.2 - Thyristor switched capacitor TSC
20.7.3 - Shunt Static VAr compensator SVC (TCR//TSC)
Example 20.2: Shunt thyristor controlled reactor specification
898

20.8 Static Series Reactive Power Compensation 899

20.8.1 - Thyristor switched series capacitor TSSC
20.8.2 - Thyristor controlled series capacitor TCSC
20.8.3 - Series Static VAr compensator SVC (TCR//C)
Example 20.3: Series thyristor controlled reactor specification – integral control
903
Example 20.4: Series thyristor controlled reactor specification – Vernier control
905
20.8.4 Static series phase angle reactive power compensation/shift SPS

20.9 Custom Power 909

20.9.1 - Static synchronous series compensator or Dynamic Voltage Restorer - DVR
20.9.2 - Static synchronous shunt compensator –
STATCOM
20.9.3 - Unified power flow controller - UPFC

Power Electronics
xx

20.10 Combined Active and Passive Filters 924

20.10.1 - Current compensation – shunt filtering
20.10.2 - Voltage compensation – series filtering
20.10.3 – Hybrid Arrangements
20.10.4 - Active and passive combination filtering


20.11 Summary of Compensator Comparison and Features 928

20.12 Summary of General Advantages of AC Transmission over DC Transmission 928




21
929
Inverter Grid Connection for Embedded Generation

21.1 Distributed generation 929

21.1.1 DG Possibilities
21.1.2 Integration and Interconnection Requirements

21.2 Interfacing conversion methods 933




22

937
Energy Sources and Storage - Primary Sources

22.1 Hydrocarbon attributes 937

22.2 The fuel cell 939

22.3 Materials and cell design 941

22.3.1 Electrodes
22.3.2 Catalyst
22.3.3 Electrolyte
22.3.4 Interconnect
22.3.5 Stack design

22.4 Fuel Cell Chemistries 944

22.4.1 Proton H
+
Cation Conducting Electrolyte
22.4.2 Anion (OH
-
, CO
3
2-
, O
2-
) Conducting Electrolyte

22.5 Six different Fuel Cells 947

22.6 Low-temperature Fuel Cell Types 947

22.6.1 Polymer exchange membrane fuel cell
22.6.2 Alkaline fuel cell
22.6.3 Direct-methanol fuel cell

22.7 High-temperature Fuel Cell Types 950

22.7.1 Phosphoric-acid fuel cell
22.7.2 Molten-carbonate fuel cell
22.7.3 Solid oxide fuel cell

22.8 Fuel Cell Summary 954
Power Electronics

xxi

22.9 Fuels 954

22.10 Fuel Reformers 956

22.10.1 Natural gas reforming

22.11 Hydrogen storage and generation from hydrides 958

22.12 Fuel Cell Emissions 960

22.13 Fuel Cell Electrical characteristics 960

22.14 Thermodynamics 961

Example 22.1: Formation of water vapour 962
Example 22.2: Derivation of Ideal Fuel Cell Voltage
963
Example 22.3: Carbon fuel cell
965

22.15 Fuel Cell features 966

22.16 Fuel Cell Challenges 967

22.16.1 Chemical Technology Challenges
22.16.2 System Technology Challenges

22.17 Fuel cell summary 968

22.18 Photovoltaic Cells: Converting Photons to Electrons 971

22.19 Silicon structural physics 971

22.20 Semiconductor materials and structures 972

22.20.1 Silicon
22.20.2 Polycrystalline thin films
22.20.3 Single-Crystalline Thin Film
22.20.4 Nanocrystalline

22.21 PV Cell Structures 982

22.21.1 Homojunction Device
22.21.2 Heterojunction Device
22.21.3 p-i-n and n-i-p Devices
22.21.4 Multi-junction Devices

22.22 Equivalent circuit of a PV cell 985

22.22.1 Ideal PV cell model
22.22.2 Practical PV cell model
22.22.3 Maximum-power point

22.23 Photovoltaic cell efficiency factors 987

Example 22.4: Solar cell characteristics 988

22.24 Module (or array) series and parallel PV cell connection 989

Example 22.5: PV cell and module characteristics 990

22.25 Battery storage 991

22.26 The organic photovoltaic cell 992

22.27 Summary of PV cell technology 994

Power Electronics
xxii

23
999
Energy Sources and Storage - Secondary Sources

23.1 Batteries 999

23.2 The secondary electro-chemical cell 1000

23.2.1 REDOX Galvanic Action
23.2.2 Intercalation Action

23.3 Characteristics of Secondary Batteries 1004

23.4 The lead-acid battery 1007

23.4.1 Basic lead-acid cell theory
23.4.2 Cell/battery construction
23.4.3 Characteristics of the flooded lead-acid cell
23.4.4 Different lead-acid cell and battery arrangements
23.4.5 Lead acid battery charging and storage regimes
23.4.6 Valve-regulated battery discharge characteristics
Example 23.1: Lead-acid battery discharge characteristics
1023
Example 23.2: Lead acid battery life
1025
23.4.7 Gassing and internal recombination
23.4.8 User properties and cell type comparisons

23.5 The nickel-cadmium battery 1033

Example 23.3: NiCd battery electrolyte life 1038
Example 23.4: NiCd battery requirement
1040
23.5.1 Nickel-Cadmium battery properties

23.6 The nickel-metal-hydride battery 1042

23.6.1 Nickel-metal-hydride battery properties
23.6.2 Nickel-metal-hydride battery characteristics
23.6.3 Comparison between NiCd and NiMH Cells

23.7 The lithium-ion battery 1049

23.7.1 Cathode variants cells
23.7.2 General Lithium-ion Cell characteristics

23.7.3 General Lithium-ion Cell properties
23.7.4 Cell protection circuits

23.8 Battery Thermodynamics 1061

Example 23.5: Electrochemistry – battery thermodynamics 1063

23.9 Summary of key primary and secondary cell technologies 1064

23.10 The Electrochemical Double Layer Capacitor - supercapacitor 1065

23.10.1 Double layer capacitor model
Example 23.6: Ultracapacitor module design using a given cell
1069
23.10.2 Cell parameter specification and measurement methods
23.10.3 Cell characteristics
23.10.4 Thermal Properties
23.10.5 Estimated life duration
23.10.6 Cell Voltage Equalization in a Series Stack of Ultracapacitors
23.10.7 Supercapacitor general properties
23.10.8 Pseudocapacitors
Example 23.7: Ultracapacitor constant current characteristics
1079

23.11 Thermoelectric modules 1081

23.11.1 Background
Power Electronics

xxiii
23.11.2 Thermoelectric materials
23.11.3 Mathematical equation for a thermoelectric module
23.11.4 Features of Thermoelectric Cooling - Peltier elements
23.11.5 TE cooling design
Example 23.8: Thermoelectric cooler design
1093
23.11.6 Thermoelectric power generation
Example 23.9: Thermoelectric generator design
1097
23.11.7 Thermoelectric performance

23.12 Appendix: Primary cells 1100

23.13 Appendix: Empirical Battery Model 1102


24
1103
Capacitors

24.1 Capacitor general properties 1104

24.1.1 Capacitance
24.1.2 Volumetric efficiency
24.1.3 Equivalent circuit
24.1.4 Lifetime and failure rate
Example 24.1: Failure rate
1108
Example 24.2: Capacitor reliability
1109
24.1.5 Self-healing
24.1.6 Temperature range and capacitance dependence
24.1.7 Dielectric absorption

24.2 Liquid (organic) and solid, metal oxide dielectric capacitors 1111

24.2.1 Construction
24.2.2 Voltage ratings
24.2.3 Leakage current
24.2.4 Ripple current
Example 24.3: Capacitor ripple current rating

1115
24.2.5 Service lifetime and reliability

24.2.5i - Liquid, oxide capacitors
Example 24.4: A1
2
0
3
capacitor service life 1117
24.2.5ii - Solid, oxide capacitors
Example 24.5: Lifetime of tantalum capacitors 1118

24.3 Plastic film dielectric capacitors 1119

24.3.1 Construction
24.3.1i - Metallised plastic film dielectric capacitors
24.3.1ii - Foil and plastic film capacitors
24.3.1iii - Mixed dielectric capacitors
24.3.2 Insulation
24.3.3 Electrical characteristics

24.3.3i - Temperature dependence
24.3.3ii - Humidity dependence
24.3.3iii - Time dependence
24.3.3iv - Dissipation factor and impedance
24.3.3v - Voltage derating with temperature
24.3.3vi – Voltage and current derating with frequency
Example 24.6: Power dissipation limits - ac voltage 1129
24.3.3vii - Pulse dV
R

/dt rating
24.3.4 Non-sinusoidal repetitive voltages
Example 24.7: Capacitor non-sinusoidal voltage rating
1131
Example 24.8: Capacitor power rating for non-sinusoidal voltages
1131
Power Electronics
xxiv
24.3.5 DC plastic capacitors

24.4 Emi suppression capacitors 1134

24.4.1 Class X capacitors
24.4.2 Class Y capacitors
24.4.3 Feed-through capacitors

24.5 Ceramic dielectric capacitors 1136

24.5.1 Class I dielectrics
24.5.2 Class II dielectrics
24.5.3 Applications

24.6 Mica dielectric capacitors 1139

24.6.1 Properties and applications

24.7 Capacitor type comparison based on key properties 1141

24.8 Appendix: Minimisation of stray capacitance 1141

24.9 Appendix: Capacitor lifetime derating 1142





25
1145
Resistors

25.1 Resistor types 1146

25.2 Resistor construction 1146

25.2.1 Film resistor construction
25.2.2 Carbon composition film resistor construction

Example 25.1: Carbon film resistor 1148
25.2.3 Solid Carbon ceramic resistor construction
25.2.4 Wire-wound resistor construction

25.3 Electrical properties 1149

25.3.1 Resistor/Resistance coefficients

25.3.1i - Temperature coefficient of resistance
Example 25.2: Temperature coefficient of resistance for a thick film resistor 1152
25.3.1ii - Voltage coefficient of resistance
25.3.2 Maximum working voltage
25.3.3 Residual capacitance and residual inductance

Example 25.3: Coefficients of resistance for a solid carbon ceramic resistor
1155

25.4 Thermal properties 1155

25.4.1 Resistors with heatsink
Example 25.4: Derating of a resistor mounted on a heatsink
1158
25.4.2 Short time or overload ratings
Example 25.5: Non-repetitive pulse rating
1159

25.5 Repetitive pulsed power resistor behaviour 1159

Example 25.6: Pulsed power resistor design 1160
25.5.1 Empirical pulse power
25.5.2 Mathematical pulse power models
Power Electronics

xxv
Example 25.7: Solid carbon ceramic resistor power rating 1161

25.6 Stability and endurance 1163

Example 25.8: Power resistor stability 1164

25.7 Special function power resistors 1164

25.7.1 Fusible resistors
25.7.2 Circuit breaker resistors

25.7.3 Temperature sensing resistors
25.7.4 Current sense resistors

25.7.5 Thermistors
25.7.6 Other specialised resistors

25.8 Appendix: Carbon ceramic electrical and mechanical data and formula 1172

25.9 Appendix: Characteristics of resistance wire 1172

25.10 Appendix: Preferred resistance values of resistors (and capacitors) 1172


26
1175
Soft Magnetic Materials - Inductors and Transformers

26.1 Inductor and transformer electrical characteristics 1176

26.1.1 Inductors
26.1.2 Transformers or magnetically coupled circuits

26.2 Magnetic material types 1178

26.2.1 Ferromagnetic materials

26.2.1i - Steel
26.2.1ii - Iron powders
26.2.1iii - Alloy powders
26.2.1iv - Nanocrystalline

26.2.2 Ferrimagnetic materials- soft ferrites

26.3 Comparison of material types 1179

26.4 Ferrite characteristics 1180

26.4.1 Dimensions and parameters
26.4.2 Permeability

26.4.2i - Initial or intrinsic permeability, µ
i

26.4.2ii - Amplitude permeability, µ
a
and maximum permeability,
µ
∧

26.4.2iii - Reversible or incremental permeability, µ
rev
, µ
∆
26.4.2iv - Effective permeability, µ
e

26.4.2v - Complex permeability,
µ

26.4.3 Coercive force and remanence
26.4.4 Core losses

26.4.4i - Core losses at low H
26.4.4ii - Core losses at high H
26.4.5 Temperature effects on core characteristics
26.4.6 Inductance stability

26.4.6i - Parameter effects
26.4.6ii - Time effects
Example 26.1: Inductance variation with time 1190

26.4.6iii - Temperature effects
Example 26.2: Temperature effect on inductance 1190
26.4.7 Stored energy in inductors
Power Electronics
xxvi

26.5 Ferrite inductor and choke design, when carrying dc current 1192

26.5.1 Linear inductors and chokes
Example 26.3: Inductor design with Hanna curves
1194
26.5.1i - Core temperature and size considerations
Example 26.4: Inductor design including copper loss 1197
26.5.2 Saturable inductors
26.5.3 Saturable inductor design
Example 26.5: Saturable inductor design
1201

26.6 Power ferrite transformer design 1201

26.6.1 Ferrite voltage transformer design

Example 26.6: Ferrite voltage transformer design
1205
26.6.2 Ferrite current transformer
26.6.3 Current transformer design requirements
26.6.4 Current transformer design procedure
Example 26.7: Ferrite current transformer design
1211
26.6.5 Current measurement: closed loop ferrite transformer
26.6.6 Current measurement: Rogowski Coil

26.7 Auto-transformers 1217

26.8 Appendix: Soft ferrite general technical data 1221

26.9 Appendix: Technical data for a ferrite applicable to power applications 1221

26.10 Appendix: Technical data for iron, nickel, and cobalt applicable to power applications 1222

26.11 Appendix: Cylindrical inductor design 1223

Example 26.8: Wound strip air core inductor 1223
Example 26.9: Multi-layer air core inductor
1224

26.12 Appendix: Copper wire design data 1225

26.13 Appendix: Minimisation of stray inductance 1225

26.11.1 Reduction in wiring residual inductance
26.11.2 Reduction in component residual inductance

26.11.2i - Capacitors
26.11.2ii - Capacitors - parallel connected
26.11.2iii - Transformers

26.14 Appendix: Laminated bus bar design 1228

26.15 Appendix: Insulating material for between bus bar conductors 1231

26.16 Appendix: Materials by types of magnetization 1231




27
1235
Hard Magnetic Materials - Permanent Magnets

27.1 Magnetic properties 1239

27.2 Classification of magnetic materials 1240

27.2.1 Alloys
27.2.2 Ceramics
27.2.3 Bonded
Power Electronics

xxvii
27.2.4 Flexible (rubber)

27.3 Properties of hard magnetic materials 1253

27.4 Permanent Magnet Magnetization Curve (hysteresis loop) and recoil 1258

27.5 Permanent Magnet model 1260

27.6 Load lines 1263

27.6.1 Magnetic Circuit Equations
27.6.2 Intrinsic permeance coefficient
Example 27.1: Magnet load dependant operating point 1267
27.6.3 Demagnetizing field

27.7 Generalising equivalent magnetic circuits 1272

27.8 Permanent magnet stability - Loss of magnetism 1274

27.9 Recoil operation and associated losses 1277

27.9.1 Losses due to reverse magnetic fields
27.9.2 Demagnetisation due to temperature increase
Example 27.2: Magnet load and temperature dependant operating point 1281

27.10 Energy transfer 1283

27.11 Force of attraction within an air gap 1286

27.12 Appendix: Magnet processing and properties 1287

27.13 Appendix: Magnetic Basics 1289

27.14 Appendix: Magnetic properties for Sintered NdFeB and SmCo Magnets 1289

27.15 Appendix: Magnetic Axioms 1291


28
1293
Contactors and relays

28.1 Mechanical requirements for relay operation 1293

28.2 Relay Contacts 1294

28.2.1 Contact characteristics
28.2.2 Contact materials
28.2.3 Contact life – material loss and transfer

28.3 Defining relay performance 1298

28.4 AC and DC relay coils 1300

28.5 Temperature consideration of the coils in dc relays 1301

Example 28.1: Relay coil thermal properties 1302

28.6 Relay voltage transient suppression 1303

28.6.1 Types of transient suppression utilized with dc relay coils
28.6.2 Relay contact arc suppression protection with dc power switching relays

Power Electronics
xxviii
28.7 DC power switching 1308

28.8 The physics of vacuum high-voltage relays 1312

28.9 Gas filled relays 1313

28.9.1 SF6 as a dielectric
28.9.2 Hydrogen as a dielectric

28.10 High voltage relay designs 1314

28.11 Contact ratings 1317

28.12 High voltage relay grounding 1318

28.13 A LV voltage, 750V dc, high-current, 350A dc, make and break relay 1320

28.14 X-ray emissions in vacuum relays 1321

28.15 Power reconstitution conservation method 1321

28.16 MV AC vacuum Interrupts for contactor, switch, and circuit-breaker application 1323

28.16.1 Basic Interruption Principle
28.16.2 Medium-Voltage AC Vacuum circuit breaker characteristics
28.16.3 Altitude derating
Example 28.2: Vacuum circuit breaker altitude properties 1330

28.17 Corona 1331

28.19 Appendix: Contact metals 1333




Nomenclature and symbols 1335

Degrees of protection 1350
IP codes according to IEC 60529 standard

IEC 947 and IEC 947-3 Standards 1351
Selecting contactors according to IEC 947-3 standard

Glossary of terms
1352

Glossary of Wafer Processing terminology 1352
Glossary of Fuselink terminology (Fuseology) 1356
Glossary of Relay terminology 1360
Glossary of Varistor terminology 1370
Glossary of PTC and NTC Thermistor terminology 1371
Glossary of Electrochemical Battery terminology 1374

Glossary of Fuel Cell terminology 1379
Glossary of Solar Electric terminology 1382
Glossary of Capacitor terminology 1388
Glossary of Thermoelectric terminology 1392

Glossary of Fan Cooling and other Heating and Cooling terminology 1395
Glossary of Magnetic terminology 1402


Bibliography 1413

Physical constants 1424

INDEX 1425
Power Electronics

xxix







PREFACE






The book is in four parts.

Part 1 covers power semiconductor switching devices, their static and dynamic electrical and thermal
characteristics and properties. Part 2 describes device driving and protection, while Part 3 presents a

number of generic applications. The final part, Part 4, introduces capacitors, magnetic components,
resistors, and dc relays and their characteristics relevant to power electronic applications.


1 Basic Semiconductor Physics and Technology
2 The pn Junction
3 Power Switching Devices and their Static Electrical Characteristics
4 Electrical Ratings and Characteristics of Power Semiconductor Switching Devices
5 Cooling of Power Switching Semiconductor Devices

6 Load, Switch, and Commutation Considerations
7 Driving Transistors and Thyristors
8 Protecting Diodes, Transistors, and Thyristors
9 Switching-aid Circuits with Energy Recovery
10 Series and Parallel Device Operation, Protection, and Interference

11 Naturally Commutating AC to DC Converters – Uncontrolled Rectifiers
12 Naturally Commutating AC to DC Converters – Controlled Rectifiers
13 AC Voltage Regulators
14 DC Choppers
15 DC to AC Inverters – Switched Mode
16 DC to AC Inverters – Resonant Mode
17 DC to DC Converters - Switched-mode
18 DC to DC Converters - Resonant-mode
19 HV Direct-Current Transmission
20 FACTS Devices and Custom Controllers
21 Inverter Grid Connection for Embedded Generation
22 Energy Sources and Storage: Primary Sources
23 Energy Sources and Storage: Secondary Sources

24 Capacitors
25 Resistors
26 Soft Magnetic Materials: Inductors and Transformers
27 Hard Magnetic Materials: Permanent Mmagnets
28 Contactors and Relays


The 156 non-trivial worked examples cover the key issues in power electronics.



BWW
April 2010
BWW







CHAPTER 1

Basic Semiconductor Physics
and Technology



The majority of power electronic circuits utilise power semiconductor switching devices which ideally
present infinite resistance when off, zero resistance when on, and switch instantaneously between those

two states. It is necessary for the power electronics engineer to have a general appreciation of the
semiconductor physics aspects applicable to power switching devices so as to be able to understand the
vocabulary and the non-ideal device electrical phenomena. To this end, it is only necessary to attempt a
qualitative description of switching devices and the relation between their geometry, material
parameters, and physical operating mechanisms.
Typical power switching devices such as diodes, thyristors, and transistors are based on a
monocrystalline group
IV silicon semiconductor structure or a group IV polytype, silicon carbide. These
semiconductor materials are distinguished by having a specific electrical conductivity, σ, somewhere
between that of good conductors (>10
20
free electron density) and that of good insulators (<10
3
free
electron density). Silicon is less expensive, more widely used, and a more versatile processing material
than silicon carbide, thus the electrical characteristics and processing properties of silicon are
considered first, in more detail.
In pure silicon at equilibrium, the number of electrons is equal to the number of holes. The silicon is
called intrinsic and the electrons are considered as negative charge-carriers. Holes and electrons both
contribute to conduction, although holes have less mobility due to the covalent bonding. Electron-hole
pairs are continually being generated by thermal ionization and in order to preserve equilibrium
previously generated pairs recombine. The intrinsic carrier concentrations n
i
are equal, small (1.4x10
10
/cc), and highly dependent on temperature. In order to fabricate a power-switching device, it is
necessary to increase greatly the free hole or electron population. This is achieved by deliberately
doping the silicon, by adding specific impurities called dopants. The doped silicon is subsequently
called extrinsic and as the concentration of dopant N
c

increases, the resistivity ρ

=

1/σ decreases.

n-type:- Silicon doped with group
V elements, such as As, Sb or P, will be rich in electrons compared to
holes. Four of the five valence electrons of the group
V dopant will take part in the covalent
bonding with the neighbouring silicon atoms, while the fifth electron is only weakly attached
and is relatively 'free'. The semi-conductor is called n-type because of its free negative charge-
carriers. A group
V dopant is called a donor, having donated an electron for conduction. The
resultant electron impurity concentration is denoted by N
D
- the donor concentration.
p-type:- If silicon is doped with atoms from group
III, such as B, Aℓ, Ga or In, which have three valence
electrons, the covalent bonds in the silicon involving the dopant will have one covalent-bonded
electron missing. The impurity atom can accept an electron because of the available thermal
energy. The dopant is thus called an acceptor, which is ionised with a net positive charge.
Silicon doped with acceptors is rich in holes and is therefore called p-type. The resultant hole
impurity concentration is denoted by N
A
- the acceptor concentration.
Chapter 1 Basic Semiconductor Physics and Technology
2
Electrons in n-type silicon and holes in p-type are called majority carriers, while holes in n-type and
electrons in p-type are called minority carriers. In a given silicon material, at equilibrium, the product of

the majority and minority carrier concentration is a constant:

2
oo i
pn n
×=
(1.1)
where p
o
and n
o
are the hole and electron equilibrium carrier concentrations.

Therefore, the majority and minority concentrations are given by:

2
2
For an -type therefore and
For a -type therefore
i
oD o
D
i
oA o
A
n
nnN p
N
n
ppN n

N
==
==
(1.2)
These equations show that the number of minority carriers decreases as the doping level increases.
The resistivity, ρ, of doped silicon is

()
11
np
q
np
ρ
σ
µµ
==
+
(1.3)
where: σ = 1/ρ = conductivity, Ω
-1
.cm
-1

ρ = 1/σ = resistivity, Ω.cm
µ
n
= electron mobility, cm
2
/V-s
µ

p
= hole mobility, cm
2
/V-s
q = electron charge, 1.602x10
-19
C
n = electron concentration, cm
-3

p = hole concentration, cm
-3






Figure 1.1. Elemental doped silicon.


Resistance of semiconductor materials is usually expressed in terms of sheet resistance R
s
, which is
related to resistance as follows. The impurity depth x
j
, mobility µ, and impurity distribution N(x) are
related to sheet resistance by

0

1
Ω/square
()
j
s
x
R
qNxdxµ
=
∫
(1.4)
The average resistivity is
sj
Rx
ρ
= and given a length L and width w, as defined in figure 1.1, the
resistance is given by

Ω
s
LL L
RR
Atw w
ρ
ρ
== = (1.5)
For consecutive n-doped profiles, the resistance can be estimated by treating each layer independently:

()
111 11

11 11
12 12
1
11 11

total ss niDii
i
wt wt t t
ww
RRR RR qNt
LL L L
µ
ρρ ρρ
−−− −−
=

=++= + += ++= ++=


∑
(1.6)


Example 1.1: Resistance of homogeneously doped silicon

Silicon doped with phosphorous (N
D
=

10

17

/cm
3
) measures 100µm by 10µm by 1µm. Calculate the sheet
resistance and resistance between opposite faces, assuming the electron mobility at this doping level is
µ
n
= 720cm
2
/

V-s. Doping to produce a p-type material has a hole mobility of 40% that for electrons.
Recalculate sheet resistance and resistance values.

Solution

From equation (1.3), the resistivity, ρ, of doped silicon is

()
11
np
q
np
ρ
σ
µµ
==
+

Since n

>>

p in the n-type silicon

19 17
11
0.086Ωcm
1.6 10 720 10
n
qn
ρ
µ
−
== =
×××

t
area

A
=W×
t

len
g
th L

w

i
d
t
h




W

Power Electronics
3
For a length of 100µm, the resistance is

4
44
100 10
0.086 8.6kΩ
10 10 1 10
Length L
R
Area w t
ρρ
−
−−
×
=× =× = × =
××××

From equation (1.5) the sheet resistance is given by

4
4
10 10
8.6kΩ 860 Ω/square
100 10
s
W
RR
L
−
−
×
== × =
×

If the length is assumed to be one of the shorter dimensions, then for a length 10µm or 1µm, the
resistance is 86Ω or 0.86Ω, respectively, while the sheet resistance possibilities, depending on
the thickness reference axis, are 86 Ω/square and 8.6 Ω/square.
For a p-type material, the 40% decrease in mobility of holes µ
p
increases resistivity by a factor of
1/0.4

=

2.5. Each aspect resistance therefore increases by a factor 2.5, viz., increases to
21.5kΩ, 215Ω, and 2.15Ω for lengths 100µm, 10µm, and 1µm, respectively. From equation (1.4)
the sheet resistances are increased to 2.15kΩ/square, 215Ω/square, and 21.5Ω/square.
♣

The carrier concentration equilibrium can be significantly changed by irradiation by photons, the
application of an electric field or by heat. Such carrier injection mechanisms create excess carriers.
If n-type silicon is irradiated by photons with enough energy to ionise the valence electrons, electron-
hole pairs are generated. There is already an abundance of majority electrons in the n-type silicon, thus
the photon-generated excess minority holes are of more relative and detectable importance. If the light
source is removed, the time constant associated with recombination, or decay of excess minority
carriers, is called the minority carrier hole lifetime,
τ
h
. For a p-type silicon, exposed to light, excess
minority electrons are generated and after the source is removed, decay at a rate called the minority
carrier electron lifetime,
τ
e
. The minority carrier lifetime is often called the recombination lifetime.

A difficulty faced by manufacturers of high-voltage, large-area semiconductor devices is that of
obtaining uniformity of n-type phosphorus doping throughout the usual high-resistivity silicon starting
material. Normal crystal growing (by liquid encapsulated, contactless, Czochralski crystal growth – see
section 1.19.3i) and doping techniques give no better than ±10 per cent fluctuation around the wanted
resistivity at the required low concentration levels (<10
14
/cc). Final device electrical properties will
therefore vary widely in all lattice directions. Tolerances better than ±1 per cent in resistivity and
homogeneous distribution of phosphorus can be attained by neutron radiation, commonly called neutron
transmutation doping,
NTD. The neutron irradiation flux transmutes silicon atoms first into a silicon
isotope with a short 2.62-hour half-lifetime, which then decays into phosphorus. Subsequent thermal
annealing removes any crystal damage caused by the irradiation. Neutrons can penetrate over 100mm

into silicon, thus large silicon crystals can be processed using the
NTD technique.

A p-n junction is the location in a semiconductor where the doping changes from p to n while the
monocrystalline lattice continues undisturbed. A bipolar diode is thus created, which forms the basis of
any bipolar semiconductor device.
The donor-acceptor doping junction is formed by any one of a number of process techniques, namely
alloying, diffusion, epitaxy, ion implantation or the metallization for ohmic contacts.

Power semiconductor device processing involves most of the following range of process possibilities.

• Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer.
Available technologies consist of physical vapour deposition (PVD), chemical vapour deposition
(CVD), electrochemical deposition, molecular beam epitaxy (MBE) and atomic layer deposition
among others.
• Removal processes are any that remove material from the wafer either in bulk or selective form
and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch.
• Patterning covers the series of processes that shape or alter the existing shape of the deposited
materials and is generally referred to as lithography. In conventional lithography, the wafer is
coated with a chemical called a photoresist. The photoresist is exposed by a ‘stepper’, a machine
that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength
UV light. The unexposed regions are washed away by a developer solution. After etching or other
processing, the remaining photoresist is removed by oxygen plasma ashing or stripping.
• Modification of electrical properties consists of doping transistor sources and drains in diffusion
furnaces and by ion implantation. These doping processes are followed by furnace annealing or in
advanced devices, by rapid thermal annealing which serve to activate the implanted dopants.
Modification of electrical properties extends to reduction of dielectric constant in low-k insulating
materials via exposure to ultraviolet light.

Chapter 1 Basic Semiconductor Physics and Technology

4
n
(a) (b)
step
junction
n
(a) (b)
1.1 Processes forming and involved in forming semiconductor devices

1.1.1 Alloying

At the desired region on an n-type wafer, a small amount of p-type impurity is deposited. The wafer is
then heated in an inert atmosphere and a thin film of melt forms on the interface. On gradual, slow
cooling, a continuous crystalline structure results, having a step or abrupt pn junction as shown in figure
1.2. This process is not employed to form modern p-n junctions but can be used at the metallisation
stage of wafer fabrication.













Figure 1.2. N-Si to Aℓ metal alloy junction:

(a) cross-section where x
j
is the junction depth below the metal-semiconductor boundary and
(b) doping profile of the formed step junction.


1.1.2 Diffusion

Diffusion, the movement of a chemical species from an area of high concentration to an area of lower
concentration, is one of the two major processes by which chemical dopants are introduced into a
semiconductor (the other process being ion implantation). The controlled diffusion of dopants into
silicon to alter the type and level of conductivity of semiconductor materials is the foundation of forming
a p-n junction and formation of devices during wafer fabrication, as shown in figure 1.3. It is used to form
bases, emitters, and resistors in bipolar devices, as well as drains and sources in MOS devices. It is
also used to dope polysilicon layers.

Figure 1.3. Diffused pn junction: (a) cross-section where x
j
is the junction depth below the silicon
surface and (b) doping concentration profile.


The mathematics that govern the mass transport phenomena of diffusion are based on two concepts.

First Concept
Whenever an impurity concentration gradient, ∂C/∂x, exists in a finite volume of a matrix substance (the
silicon substrate in this context), the impurity material has a natural tendency to move in order to
distribute itself more evenly within the matrix and decrease the concentration gradient.
Given time, this flow of impurities eventually results in homogeneity within the matrix, causing the net
flow of impurities to stop. The mathematics of this transport mechanism is based on the flux of material
across a given plane is proportional to the concentration gradient across the plane. That is:
Power Electronics
5

()
,

Nxt
JD
x
∂
=−
∂
(1.7)
where J is the flux,
D

=

µkT is the diffusion constant or diffusivity for the material that is diffusing the solvent, m/s,
∂N(x,t)/∂x is the concentration gradient. k is Boltzmann’s constant and µ is ionic mobility.
The diffusion constant of a material is also referred to as diffusion coefficient or diffusivity and is related
to mobility by D

=

µkT. It is expressed in units of length
2
/time, such as µm
2
/hour. The negative sign of
the right side of the equation indicates that the impurities flow to the lower concentration.

Second Concept
Equation (1.7) does not account for the fact that the gradient and local concentration of the impurities in
a finite volume of material decreases with an increase in time, an aspect that is important to diffusion
processes.
The flux J
1
of impurities entering a section of a material with a concentration gradient is different from
the flux J
2
of impurities leaving the same section. From the law of conservation of matter, the difference
between J
1
and J

2
must result in a change in the concentration of impurities within the section, assuming
that no impurities are formed or consumed in the section.
The second concept states that the change in impurity concentration over time is equal to the change in
local diffusion flux, or

()
,

Nxt
J
tx
∂
∂
=−
∂∂

or, from the first concept, equation (1.7)

()
()
,
,

Nxt
D
x
Nxt
tx


∂
∂


∂
∂

=
∂∂
(1.8)
If the diffusion coefficient is independent of position, such as when the impurity concentration is low,
then the second concept may be simplified to:

() ()
2
2
,,

Nxt Nxt
D
tx
∂∂
=
∂∂
(1.9)

There are two major ways by which to deposit impurities into a substance by thermal diffusion. In the
first method, known as predeposition, a flux of impurities continuously arrives at the surface of the
substrate such that the concentration gradient of the impurity remains constant at the surface of the
substrate, as shown in figure 1.4b. In the second method, known as redistribution or drive-in diffusion, a

thin layer of the impurity material is deposited on the substrate. In this case, the impurity gradient at the
surface of the substrate decreases with time, as shown in figure 1.4c.

The semiconductor diffusion process is usually performed in two steps: predeposition and then drive-in.
During predeposition, the impurity dopant is added to the wafer n-type silicon substrate.
Predeposition is done in a diffusion furnace at temperatures around 1000 to 1250ºC. The dopant is
introduced into the furnace, and may be in the form of a gas, solid, or liquid. Gaseous dopants are
mixed with an inert carrier gas, such as nitrogen or argon, and introduced into the furnace. Solid
dopants are often applied in a powder form. The solid is heated and a stream of carrier gas moves
the dopant into the furnace. Liquid sources are used by bubbling an inert carrier gas through the
liquid dopant, and the gas saturated with the liquid is added to the furnace. This compound breaks
down as a result of the high temperature, and is slowly diffused into the substrate. The maximum
impurity concentration occurs at the surface, tailing off towards the inside.
The wafers are then put into a second furnace at higher temperatures (about 1300ºC) to drive-in the
dopant. The drive-in process usually occurs in an oxidizing atmosphere so that a protective layer of
Si0
2
is grown over the diffused layer.

Table 1.1: Dopants and chemical reactions

Dopant state Dopant type dopant chemistry
p-type diborane B
2
H
6
B
2
H
6

+

30
2
→

B
2
0
3
+

3H
2
0
gas
n-type
arsine AsH
3

phosphine PH
3

2PH
3
+

40
2
→

B
2
0
5
+

3H
2
0
p-type BBr
3
4BBr
3
+

30
2
→

2B
2
0
3
+

6Br
2

liquid

n-type AsCℓ
3
, P0Cℓ
3
4P0Cℓ
3
+

30
2
→

2P
2
0
5
+

6Cℓ
2

p-type BN, B
2
O
3
2B
2
O
3
+3Si

4
→

4B+3SiO
2

solid
n-type As
2
0
3
, P
2
0
5

2As
2
0
3
+

3Si →

4As

+

3Si0
2

2P
2
O
5
+5Si
4
→

4P+5SiO
2

Chapter 1 Basic Semiconductor Physics and Technology
6
Typical dopants and silicon chemical reactions are shown in Table 1.1, while common diffusion
coefficients and activation energies, referenced to 0K, are shown in Table 1.2.
The diffusion process is the only junction forming technique that is not applicable to silicon carbide wafer
processing.

Figure 1.4. Diffusion processes:
(a) pictorial representation of mechanism; (b) predeposition diffusion; and (c) drive in diffusion.


The doping profile is mathematically defined and is varied by controlling the vapour mixture
concentration, the furnace temperature, and time of diffusion.
If the source concentration is continuously replenished – predeposition dose, thus maintained
constant, the surface concentration is N(0,t)

=

N
s
, and the initial concentration is N(x,0)=0, then the
doping profile is given by a complementary error function, erfc.

()
()
()
0
2
,

2
2
111
2
where
difussion length
2
s
u
sss
x
Nxt Nerfc
Dt
x
N erf N erf u N e d
Dt
xx
u
Dt
ν
ν
π
−

=







=− =− =−






==
∫
(1.10)
The area under the diffusion profile is the total amount of dopant diffused into the wafer:

() ( )
2
,1.13
ss
o
Q
tNxtdx NDt NDt
π
∞
===
∫
(1.11)
The junction depth is where the doping profile N(x,t) equals the background doping N
B
level, that is

()

,
2
j
js B
x
Nx t Nerfc N
Dt

==



Rearranging, gives the junction depth x
j
as

1
2
B
j
s
N
xDterfc
N
−
=× (1.12)
If natural depletion of dopant occurs – drive in, that is the initial dose S at the surface is not replenished,
then the profile is an exponential function, which gives a Gaussian diffusion distribution.

()

2
4
,
x
Dt
S
Nxt e
Dtπ
=
−
(1.13)
where

()
, non-replenished inital surface dose
o
Nxtdx S
∞
==
∫
(1.14)
The diffusion length, x

=

2√Dt, is an approximate measure of how far the dopant has diffused, which is
the distance from the surface to where the concentration has fallen to 1/e.
Impurity diffusion
silicon dioxide silicon wafer

(a) (b) (c)
background
substrate
N
o
or N
s


N
o

Predeposition Drive in

Power Electronics
7
The surface concentration, which is not replenished (dN(0,t)/dx

=

0), diminishes with time, according to

()
0,
S
Nt
Dt
π
= (1.15)
The junction depth is where the doping profile N(x,t) equals the background doping N

B
level, that is

()
2
4
,
x
Dt
jB
S
Nx t e N
Dtπ
==
−

Rearranging, gives the junction depth x
j
as

()
0,
2n 2n
j
B
B
Nt
S
xDt Dt
N

Dt Nπ


=× =×






½
½
AA (1.16)
In both processing cases, N(∞,t)

=

0.

Diffusivity D varies with temperature according to

e
a
E
kT
o
DD
−
=
(1.17)

where D
o
= diffusion coefficient (in cm
2
/s) extrapolated to infinite temperature
E
a
= activation or threshold energy in eV, which is not particularly temperature dependant.

Table 1.2: Typical diffusion coefficients and activation energies at 0K


D
o
E
a

Element
0K
cm
2
/s
eV
boron
B 1.0 3.50
phosphorous
P 4.7 3.68
antimony
At 4.58 3.88
arsenic

As 9.17 3.99
indium
In 1.20 3.50


Example 1.2: Constant Surface Concentration diffusion - predepostion

For a constant-source boron diffusion into n-type 10
15
cm
-3
silicon at 1000°C, the surface concentration
is maintained at 10
19
cm
-3
and the diffusion time is 1 hour. Find
i. Total amount of dopant diffused, Q(t) and the gradient at x = 0 and
ii. The gradient and location (junction depth) where the dopant concentration reaches 10
15
cm
-3
.

Solution

Using data for boron in Table 1.2, equation (1.17) gives the diffusion coefficient of boron at
1000°C as

5

3.05
14 2
8.614 10 1273
24 1.39 10 cm /s
a
E
kT
o
DDe e
−
−
−
−
××
== =×
so the diffusion length is

14 6
1.39 10 3600 7.07 10 cm
Dt
−−
=××=×


i. The area under the diffusion profile from equation (1.11) is

(
)
19 6 13 -2
19

23 -4
6
0
1.13 1.13 10 7.07 10 8.0 10 cm
10
7.98 10 cm
7.07 10
s
s
x
Qt N Dt
N
dN
dx
Dtππ
−
−
=
==×××=×
=− =− =− ×
××


ii. From equation (1.10) rearranged, when N
B
= 10
15
cm
-3
, x

j
is given by

15
11
19
6
10
22
10
2 7.07 10 2.75 0.389µm
B
j
s
N
x Dterfc Dterfc
N
−−
−


=× =×




=× × × =


2

20 -4
4
0.389µm
4.0 10 cm
x
s
Dt
x
N
dN
e
dx
Dtπ
−
=
=− =− ×
♣
Chapter 1 Basic Semiconductor Physics and Technology
8
Example 1.3: Constant Total Dopant diffusion – drive in - 1

Arsenic was pre-deposited by arsine gas, and the resulting dopant per unit area was 10
14
cm
-2
. How
long would it take to drive the arsenic in to x
j
= 1 µm? Assume a background doping of N
sub

= 10
15
cm
-3
,
and a drive-in temperature of 1200°C. For As, assume D
o
= 24 cm
2
/s, and E
a
= 4.08 eV at 1200°C.

Solution

From equation (1.17) the diffusion coefficient for arsenic at 1200°C is

5
4.08
13
8.614 10 1473
24 2.602 10
a
E
kT
o
DDe e
−
−
−

−
××
== =×
Rearranging equation (1.13) gives

5
28 12
1.106 10
10 4 n 1.04 10 n
j
B
S
xDt t
NDt tπ
−−


×
== =×





AA
That is

n 23.22 19230 0
tt t
×− + =A

An iterative solution gives t

=1191.7s or approximately 19.9 minutes.
♣


Example 1.4: Constant Total Dopant diffusion – drive in - 2

An arsenic constant-dose diffusion is performed with an initial dose of S=10
14
cm
-2
. The diffusion
temperature is 1100°C for 2 hours. The starting wafer had a p-type substrate background doping of 10
17

cm
-3
. Find the concentration of the As at the surface and find the junction depth.

Solution

From Table 1.2

5
3.99
14 2
8.614 10 1100 273
9.17 2.07 10 cm /s

a
E
kT
o
DDe e
−
−
−
−
××+
== =×
Then the diffusion length is

14 5
2.07 10 7200 1.22 10 cm
Dt
−−
=××=×
The surface concentration is

18
18 -3
5
0
10
4.6 10 cm
1.22 10
s
o
x

N
dN
N
dx
Dtππ
−
=
== = =×
××

From equation (1.13) rearranged, the junction depth for Gaussian diffusions is

18 -3
5
17 -3
2n
4.6 10 cm
21.2210cmn
10 cm
0.467µm
o
j
B
N
xDt
N
−

=




×
=× ×


=
½
½
A
A
♣


1.1.3 Epitaxy growth - deposition

Epitaxy or epitaxial growth is the process of depositing a non-volatile, thin solid layer typically 0.5 to 100
µm, of single crystal material over a single crystal substrate, usually through chemical vapour deposition
(CVD). The semiconductor deposited film is often the same material as the substrate, and the process
is known as homoepitaxy, or simply, epi, as with silicon deposition on a silicon substrate. If the substrate
is an ordered semiconductor crystal (that is mono-silicon, gallium arsenide), the process continues
building on the substrate with the same crystallographic orientation, with the substrate acting as a seed
for the deposition. If an amorphous/polycrystalline substrate surface is used, the film will also be
amorphous or polycrystalline. A key feature of epitaxy is that a lightly doped layer of epitaxial silicon can
be grown on top of a heavily doped silicon substrate, thus creating a layer of differing conductivity that
can serve as an insulating layer or intrinsic buffer region.
The chemical vapour deposition CVD (see section 1.2.1) of silicon epitaxy occurs in an epitaxial reactor
that consists of a quartz induction heated reaction chamber into which a susceptor is placed. The
susceptor provides two features:
• mechanical support for the wafers and

• an environment with uniform thermal distribution.
Power Electronics
9
The technological method of introducing reactant gases with only the substrates heated inside a reactor
is called Vapour Phase Epitaxy, a schematic of which is shown in figure 1.5.
A possible fabrication process is as follows. A pre-cleaned, polished, almost perfect silicon crystal
surface acts as a substrate for subsequent deposition. Usually hydrogen chloride is first used to etch the
wafers. The pre-doped silicon is heated to about 1150°C in a quartz reactor tube at atmospheric
pressure. A hydrogen gas flow carrying a compound of silicon such as silicon tetrachloride SiCℓ
4
or
silane SiH
4
is passed over the hot substrate surface, and silicon atoms are deposited, growing a new
continuous lattice. If phosphine (PH
3
) arsine (AsH
3
) or diborane (B
2
H
6
) is included in the silicon
compound carrier gas flow of H
2
and N
2
, a layer of the required type and resistivity occurs. Up to 100µm
of doped silicon can be grown on substrates for power devices at a high growth rate of about 1 µm/min
at 1200°C. A very low crystalline fault rate is essential if uniform electrical properties are to be attained.

Selective deposition, depending on the surface masking of the substrate, is possible.













Figure 1.5. Typical cold-wall vapour phase epitaxial reactor.


There are four major chemical sources of silicon for epitaxial deposition:
• silane, SiH
4

• silicon tetrachloride, SiCℓ
4
;
• trichlorosilane, SiHCℓ
3
; and
• dichlorosilane, SiH
2
Cℓ

2
.
Chemical reactions equations can describe the growth of epitaxial layers. Each of the chemical sources
mentioned can be described by an over-all reaction equation that shows how the vapour phase
reactants form the silicon epitaxial film. For example, the over-all pyrolytic reaction for silicon epitaxy by
silane decomposition reaction is:

()
42
2 1000°C to 1100°C
SiH Si H
→+ (1.18)
Hydrogen reduction of trichlorosilane is

32
3
SiHC H Si HC
+→+AA (1.19)
Reduction of dichlorosilane is

22
2
SiH C Si HC
→+AA (1.20)

However, such over-all reaction equations do not describe the complete CVD process in regard to how
the gas phase reactants interact or how the epi species are adsorbed on the substrate surface. For
instance, the over-all reaction for the hydrogen reduction of silicon tetrachloride SiCℓ
4
to form a silicon

epitaxial layer is as follows:

()
42
2 4 1150°C to 1300°C
SiC H Si HC
+→+AA (1.21)
Yet, the intermediate chemical species such as SiHCℓ
3
and SiH
2
Cℓ
2
are present during the silicon
epitaxial growth:

42 3
32 22


SiC H SiHC HC
SiHC H SiH C HC
+↔ +
+↔ +
AAA
AAA


22 2 2
32

22


2
SiH C SiC H
SiHC SiC HC
SiC H Si HC
↔+
↔+
+↔+
AA
AAA
AA

These equations confirm that even if a given process is described by a single over-all reaction, the
process is actually a combination of many simultaneous chemical reactions.
The growth rate of an epitaxial layer depends on several factors:
• the chemical sources;
• the deposition temperature; and
• the mole fraction of reactants.
gas
inlet
vent
RF induction heating coils
graphite susceptor
wafers
Chapter 1 Basic Semiconductor Physics and Technology
10
Silicon epitaxy improves the performance of bipolar devices. By growing a lightly doped epi-layer over a
heavily-doped silicon substrate, a higher breakdown voltage across the collector-substrate junction is

achieved while maintaining low collector resistance. Lower collector resistance allows a higher
operating speed with the same current. Epitaxy is also used in IC fabrication. By fabricating a CMOS
device on a thin (3 to 7 microns) lightly doped epi layer grown over a heavily-doped substrate, latch-up
occurrence is minimized – a phenomena applicable to power devices such as the
MOSFET and IGBT.
As well as improving the performance of devices, epitaxy also allows better control of doping
concentrations of the devices. The layer can also be made oxygen and carbon free. The disadvantages
of epitaxy include higher cost of wafer fabrication, additional process complexities, and problems
associated with defects in the epi-layer.

1.1.4 Ion-implantation and damage annealing

Ion Implantation is the process of depositing chemical dopant species (atoms stripped of electrons) into
a substrate by directly bombarding the substrate with high-energy ions of the chemical being deposited,
as shown in figure 1.6.
Diffusion and ion implant are the two major processes by which chemical species or dopants are
introduced into a semiconductor such as silicon to form electronic structures. The advantage of ion
implant over diffusion is its more precise control for depositing dopant atoms into the substrate (10
11
to
10
18
cm
-2
), giving excellent doping level uniformity and production repeatability.
The implanted profile shown in figure 1.6b, where two junctions may be formed, can be approximated by
a Gaussian distribution function:

22
22

() ()
22
() e e
2
pp
pp
xR xR
p
p
S
Nx N
σσ
πσ
−−
−−
== (1.22)
where S is the ion dose per unit area
, cm
-2

σ
p
is the symmetrical standard deviation in the projected range of the implanted ions, cm

Figure 1.6. Ion implantation:
(a) pictorial representation of mechanism; (b) implanted ion distribution; and (c) implanting system.

X
p

N
p

0.61 N
p

distance into the material x
X
p
+σ
p
X
p
-σ
p


impurity concentration n
2
2
()
2
() e
p
p
xX

p
Nx N
σ
−
−
=

ion
beam
wafer
Si0
2

Si0
2

implant




gas source
ion source
ion source
power supply
source
diffusion pump
ion beam
analyse
r

ma
g
net
resolving
aperture
acceleration
tube
Y scan plates
X scan plates
wafer
targeting position
wafer
feeder
Faraday
cage
beam- line and
end station diffusion
pumps
V



ground
(a) (b)


(c)
Power Electronics
11
The depth of average or mean projected range (peak) is at X

p
along the axis of incidence, where the
maximum concentration occurs.

()
ion beam current (A)
implant time
1
''
implant area
t
beam
o
q
SItdt
q
×
==
∫
(1.23)
The point where the diffused impurity profiles intersects the background concentration N
B
is the
metallurgical junction depth, x
j
, where the net impurity concentration is zero. From equation (1.22)

2
2
()

2
e
2n
jp
p
xX
Bp
p
jpp
B
NN
N
xX
N
σ
σ
−
−
=
=±
A
(1.24)
where
/2
p
p
NS
π
σ
= .

Doping, which is the primary purpose of ion implanting, is used to alter the type and level of conductivity
of semiconductor materials. It is used to form bases, emitters, and resistors in bipolar devices, as well
as drains and sources in MOS devices. It is also used to dope polysilicon layers.
Typically, a gaseous dopant is ionized by electric discharge or by heat from a hot filament. The ions are
separated using an electromagnetic field that bends the positively-charged particles to a selected band.
This ion band is then passed through a high-current accelerator. The high-velocity beam of ions is
focused on the wafer, causing the dopant ions to strike the wafer surface and penetrate. Sometimes a
mask is used to implant a designated pattern on the wafer. As with diffusion, ion implantation allows the
formation of junctions by changing the conductivity characteristics of precise regions in the wafer.
The basic procedure for ion implantation into silicon is as follows:
Ion impurities (B, P or As) are vaporised and accelerated by an electric field in a vacuum at high
keV energies at the pre-doped silicon substrate, which is at room temperature. The ions
penetrate the lattice to less than a few microns, typically 1µm at about ½

MeV. The resultant
implanted doping profile is Gaussian, with the smaller ion like boron, penetrating deeper.
These high-energy atoms enter the crystal lattice and lose their energy by colliding with some
silicon atoms before finally coming to rest at some depth. Adjusting the acceleration energy
controls the average deposition depth of the impurity atoms. Heat treatment is subsequently
used to anneal or repair the crystal lattice disturbances caused by the atomic collisions.
Every implanted ion collides with several target atoms before it comes to rest. Such collisions may
involve the nucleus of the target atom or one of its electrons. The total power of a target to stop an ion,
or its total stopping power S, is the sum of the stopping power of the nucleus and the stopping power of
the electron. Stopping power is described as the energy loss of the ion per unit path length of the ion.
Implantation energies are typically 10keV to 1MeV, giving ion distributions with depths of 10 nm to 10
µm from doses vary from 10
12
ions/cm
2
for threshold voltage adjustment in MOSFETs to 10

18
ions/cm
2

for formation of buried insulating layers.
The damage caused by atomic collisions and bombardment during high-energy ion implantation
changes the material structure therefore electrical characteristics of the target substrate. Many target
atoms are displaced, creating deep electron and hole traps which capture mobile carriers and increase
resistivity. Annealing is therefore needed to repair the lattice damage and put dopant atoms in
substitutional sites where they can be electrically active again.
Silicon damage caused by ion implantation includes:
• the formation of crystal defects such as Frenkel defects, vacancies, di-vacancies, higher-
order vacancies, and interstitials;
• the creation of local zones of amorphous material within the supposedly crystalline
structure; and
• formation of continuous amorphous layers as the localized amorphous regions grow and
overlap.

The first two damage types are categorized as 'primary crystalline damage'. Restoring the ion-implanted
substrate to its pre-implant condition requires the substrate being subjected to a reparative thermal
process known as annealing.
Ion implantation damage annealing has five major components:
• electrical activation of the implanted impurities;
• primary crystalline damage annealing;
• annealing of continuous amorphous layers;
• dynamic annealing; and
• diffusion of implanted impurities.
Annealing is conducted in a neutral environment, such as in Ar or a N
2
atmosphere in a stack furnace.

Electrical activation of the implanted impurities refers to the process of increasing the electrical activity of
newly implanted impurity atoms during annealing, which usually do not occupy substitutional sites after
Chapter 1 Basic Semiconductor Physics and Technology
12
being implanted. Temperatures up to 500°C remove trapping defects, releasing carriers to the valence
or conduction bands in the process. Electrical activity decreases again at 500 to 600°C, because of the
formation of dislocations. Beyond 600°C, electrical activation increases until a peak at 800 to 1000°C.
In summary, primary crystalline damage annealing consists of:
• recombination of vacancies and self-interstitials in the low temperature range, up to 500°C;
• formation of dislocations at 500 to 600°C which can capture impurity atoms; and
• dissolution of these dislocations at 900 to 1000°C.
Annealing of the continuous amorphous layers that extend to the surface occur by solid-phase epitaxy
between 500 to 600°C. The crystalline substrate beneath the amorphous layers initiates the
recrystallization of the amorphous layers, with the regrowth proceeding towards the substrate surface.
Factors affecting the recrystallization rate include crystal orientation and the implanted impurities.
Amorphous layers that do not extend to the surface anneal differently, with the solid-phase epitaxy
occurring at both amorphous-single crystal interfaces and the regrowth interfaces meeting below the
surface.
Dynamic annealing effects refers to the healing of implant damage while the implantation process is
occurring. This takes place because the heat applied to the wafer during implantation makes the point
defects more mobile.
Diffusion of implanted impurities relates to the mass transport of implanted species across a
concentration gradient within an implanted layer during the annealing process. The presence of implant
damage makes this diffusion process more complex than what occurs in an undamaged single-crystal
substrate. Diffusion of implanted impurities during annealing degrades devices that have shallow
junctions or narrow base and emitter regions if the thermal processing is not rapid enough, particularly in
the case of boron ion implantation.


Example 1.5: Ion implantation

For a 100 keV boron implant with a dose of S=5×10
14
cm
-2
, calculate
i. the peak concentration if this concentration occurs at a depth of X
p
= 0.31 µm and the ion
implant standard deviation is σ
p
= 0.07 µm,
ii. the junction depth, if the substrate phosphorus background doping level is 10
15
/cm
3
, and
iii. the surface concentration.

Solution

i. From equation (1.22)

2
2
()
2
() e
2
p

p
xX
p
S
Nx
σ
πσ
−
−
=
Differentiation gives

2
2
()
2
2
2( )
e0
2
2
p
p
xX
p
p
p
xX
dn S
dx

σ
σ
πσ
−
−
−
=− =

which confirms that the maximum concentration occurs when x

=

X
p
.
Substitution into equation (1.22) gives the concentration N(x = X
p
= 0.31 µm) = 2.85×10
18
cm
-3
.

ii. The junction depth is given by equation (1.24), that is

18
15
2n
2.85 10
0.31 0.07 2 n 0.31 0.28µm

10
p
jpp
B
N
xX
N
σ
=±
×
=± =±
A
A

Two junctions are created, at 0.03 µm and 0.59 µm.

iii. Since the ion implant has formed two junctions within the n-substrate, the surface
concentration is dominated by the background doping level of the substrate, 10
15
/cm
3
. The
surface ion implant doping is given by equation (1.22)

2
2
2
2
0.31
2

18 14 3
20.07
( 0) e 2.85 10 e 1.57 10 /cm
2
p
p
X
p
S
Nx
σ
πσ
−
−
×
== = × × = ×
The n-type surface concentration is 10
15
/cm
3
– 1.57×10
14
/cm
3
= 8.4×10
14
/cm
3
.
♣

Power Electronics
13
1.2 Thin Film Deposition

A thin film is a layer with a high surface-to-volume ratio. Thin films are extensively used to apply
dopants and sealants to wafers and microelectronic parts, and can be a resistor, a conductor, an
insulator, or a semiconductor. Thin films can be deposited with a thickness of between a few
nanometres to about 100µm. The film can subsequently be locally etched using processes described in
the Lithography and Etching sections of this chapter, sections 1.5 and 1.6, respectively.
Thins films behave differently from bulk materials of the same chemical composition in several ways.
Thin films are sensitive to surface properties while bulk materials generally are not. Thin films are also
more sensitive to thermo-mechanical stresses. Thin film integrity is influenced by the quality of its
adhesion to and conformal coverage of the underlying layer, residual or intrinsic stresses after
deposition, and the presence of surface imperfections such as pinholes.
The adhesion of a thin film to the substrate or underlying layer is paramount to ensuring thin film
reliability. A thin film that is initially adhering to the underlying layer may lift off after the device is
subjected to thermo-mechanical stresses. Reliable thin film adhesion depends on the cleanliness of the
surface upon which it is deposited. Optimum substrate roughness also affects thin film adhesion. An
ultra-smooth substrate decreases adhesion tendency. A rough substrate on the other hand can result in
coating defects, which can also lead to thin film adhesion failures.
Regardless of the deposition process, thin films always have an intrinsic stress that can be either tensile
or compressive. High residual stresses can lead to adhesion problems, corrosion, cracking, and
deviations in electrical properties. Thus, proper deposition is critical to minimize intrinsic stresses in thin
films.

Deposition technology is classified into two reaction types, viz. chemical and physical:

i. Deposition that results because of a chemical reaction:
• Chemical Vapour Deposition (CVD)
• Electrodeposition

• Epitaxy
• Thermal oxidation

These processes exploit the creation of solid materials directly from chemical reactions in gas and/or
liquid compositions or with the substrate material. The solid material is usually not the only product
formed by the reaction. By-products can include gases, liquids and other solids.

ii. Deposition that results because of a physical reaction:
• Physical Vapour Deposition (PVD)
• Casting

Common for these processes is that the material deposited is physically moved onto the substrate. In
other words, there is no chemical reaction that forms the material on the substrate. This is not
completely correct for casting processes, though it is more convenient to classify them as such.

Whether the process is physical or chemical, the processing deposition reactor uses either:
• A cold wall system, where the heating process uses radio frequency or infra red heating, while
• A hot wall system uses a thermal heating resistive element or series of elements forming
heating zones.

1.2.1 Chemical Vapour Deposition (CVD)

A fluid precursor undergoes a chemical change at a solid surface, leaving a solid layer.
In this process, the substrate is placed inside a reactor to which a number of gases are supplied, as
shown in figure 1.7. The fundamental principle of the process is that a chemical reaction takes place
between the source gases. The product of that reaction is a solid material that condenses on all
surfaces inside the reactor.
CVD is capable of producing thick, dense, ductile, and good adhesive coatings on metals and non-
metals such as glass and plastic. In contrast to PVD coating in the ‘line of sight’, CVD can
simultaneously coat all surfaces of the substrate. The thin films from chemical deposition techniques

tend to be conformal, rather than directional.
CVD processes are used to produce a thin film with good step coverage. A variety of materials can be
deposited, however, some form hazardous by-products during processing. The quality of the material
varies from process to process, however generally a higher process temperature yields a material with
higher quality and fewer defects. They are generally not suitable for mixtures of materials. CVD
processing is not possible for some materials; there simply is no suitable chemical reaction.
Chapter 1 Basic Semiconductor Physics and Technology
14



















Figure 1.7. Typical CVD processing reactor system.

Chemical deposition is categorized by the phase of the precursor:

• Plating relies on liquid precursors, often a solution of water with a salt of the metal to be
deposited. Some plating processes are driven only by reagents in the solution (usually for noble
metals), but the most important process is electroplating. It was not commonly used in
semiconductor processing, but has resurfaced with the use of chemical-mechanical polishing
techniques.
1. Conventional CVD coating processing requires a metal compound that will volatilize at a low
temperature and decompose to a metal when it contacts the substrate at higher
temperature. An example of CVD is the nickel carbonyl (NiC0
4
) coating as thick as 2.5 mm
on glass windows and containers to make them explosion or shatter resistant.
2. Diamond CVD coating processing is used to increase the surface hardness of cutting tools.
The process is performed at the temperatures higher than 700ºC which softens most tool
steels. Thus, the application of diamond CVD is limited to materials which do not soften at
this temperature, such as cemented carbides.
3. Plasma-assisted CVD coating processing is performed at lower temperature than diamond
CVD coating. Diamond coatings or silicon carbide barrier coatings are applied on plastic
films and semiconductors, including sub-¼µm semiconductors.

• Chemical solution deposition uses a liquid precursor, usually a solution of organometallic powders
dissolved in an organic solvent. This is a relatively inexpensive, simple thin film process that is
able to produce stoichiometrically accurate crystalline phases.

Figure 1.8. Typical PECVD reactor.
electrode
wafer
electrode
heater
RF power input
gas outlet
gas inlet
SiH
4
0
2

plasma

Chemical vapour deposition

Power Electronics
15
outlet
exhaust
water cooled
end ca
p
assembl
y
3 zone resistive heater
pressure
gauge
wafer load

unload end cap
gas inlet
N
2
0
2
PH
3
SiH
4

silica reactor tube
wafer boat
• Chemical vapour deposition generally uses a gas-phase precursor, often a halide or hydride of
the element to be deposited. In the case of metal-organic CVD, an organometallic gas is used.

The two most important CVD technologies are Low Pressure CVD (LPCVD) and Plasma
Enhanced CVD (PECVD). The key features are:
1. The LPCVD process produces layers with uniformity of thickness and material characteristics.
The main processing problems are the high deposition temperature, greater than 600°C,
and the relatively slow deposition rate. The PECVD process can operate at lower
temperatures, down to 300° C, due to the extra energy supplied to the gas molecules by the
ionised vapour precursor, or plasma in the reactor. However, the quality of the films tend to
be inferior to processes running at higher temperatures. PECVD relies on electromagnetic
means (electric current, microwave excitation), rather than a chemical reaction, to produce
a plasma, as shown in figure 1.8.
2. Most PECVD deposition systems can only deposit the material on one side of the wafers, on
1 to 4 wafers at a time. LPCVD systems deposit films on both sides of at least 25 wafers,
simultaneously. A schematic diagram of a typical LPCVD reactor is shown in figure 1.9.
PECVD films are conformal and deposited at lower temperatures than for LPCVD, although
the film is not stoichiometric, prone to cracking and peeling, with by-products formed.

Figure 1.9. Typical horizontal hot-wall LPCVD reactor.


CVD is accomplished by placing the substrate wafers in a reactor chamber and heating them to a
specific temperature. Controlled amounts of silicon or nitride source gases, usually carried by either
nitrogen and/or hydrogen, are added to the reactor. Dopant gases may also be added if desired. A
reaction between the source gases and the wafer occurs, thereby depositing the desired layer. Reaction
temperatures between 500 to 1100ºC and pressures ranging from atmospheric to low pressure are
used, depending on the specific deposition performed. Heating is usually accomplished with radio
frequency, infrared, or thermal resistance heating. Common source gases include silane SiH
4
, silicon
tetrachloride SiCℓ
4
, ammonia NH
3
, and nitrous oxide N
2
O. Some dopant gases that are used include
arsine AsH
3
, phosphine PH
3
, and diborane B
2
H
6
. The major categories of silicon CVD are shown in the
following equations.

LPCVD Atmospheric or low pressure

Medium temperature (600 to 1100°C)
Silicon Nitride, Si
3
N
4
: H
2
carrier gas (900 to 1100°C)
3 SiH
4
+ 4 NH
3
→ Si
3
N
4
+ 12 H
2


Poly Silicon, Poly-Si, H
2
carrier gas (850 to 1000°C), N
2
carrier gas (600 to 700°C)
SiH
4
+ Heat → Si + 2 H

2


Silicon Dioxide, Si0
2
:
SiH
4
+ 4 C0
2
→ Si0
2
+ 4 C0 + 2 H
2
0 N
2
carrier gas (500 to 900°C)
2 H
2
+ SiCℓ
4
+ C0
2
→ Si0
2
+ 4 HCℓ H
2
carrier gas (800 to 1000°C)
SiH
4

+ C0 → Si0
2
+ 2 H
2
H
2
carrier gas (600 to 900°C)

Low Temperature (<

600°C)
Silicon Dioxide, Si0
2
or p-doped Si0
2
, N
2
carrier gas (<

600°C)
SiH
4
+ 2 0
2
+ Dopant → Si0
2
+ 2 H
2
0

Chapter 1 Basic Semiconductor Physics and Technology
16
Silicon Nitride, Si
3
N
4
, N
2
carrier gas (600 to 700°C)
3 SiH
4
+ 4 NH
3
→ Si
3
N
4
+ 12 H
2

3 SiH
4
+ 2 N
2
O → Si
3
N
4
+ 4 H
2

+ 2 H
2
O

PECVD Low Temperature Plasma Enhance (passivation) (<

600°C), RF or reactive sputtering

Silicon Dioxide, Si0
2
:
SiH
4
+ 2 0
2
→ Si0
2
+ 2 H
2
0 SiH
4
+ 0
2
→ Si0
2
+ 2 H
2


Silicon Nitride, Si

3
N
4
:
3 SiH
4
+ 4 NH
3
→ Si
3
N
4
+ 12 H
2

3 SiH
4
+ 2 N
2
0 → Si
3
N
4
+ 4 H
2
+ 2 H
2
0

1.2.2 Physical Vapour deposition (PVD)

Physical deposition uses mechanical or thermodynamic means to produce a thin film of solid. Physical
deposition covers a number of deposition technologies in which material is released from a source and
transferred to the substrate. Physical deposition coatings involve atom-by-atom, molecule-by-molecule,
or ion deposition of various materials on solid substrates in vacuum systems. Since most engineering
materials are held together by relatively high energies, and chemical reactions are not used to store
these energies, physical deposition systems tend to require a low-pressure vapour environment to
function properly.
The material to be deposited is placed in an energetic, entropic environment, so that particles of material
escape its surface. Facing this source is a cooler surface which draws energy from these particles as
they arrive, allowing them to form a solid layer. The system process is in a vacuum deposition chamber,
to allow the particles to travel freely. Since particles tend to follow a straight path, films deposited by
physical means are commonly directional, rather than conformal.
PVD comprises the standard technologies for deposition of metals. It is more common than CVD for
metals since it can be performed with lower process risk and cheaper materials costs. The film quality is
inferior to CVD, which for metals means higher resistivity and for insulators more defects and traps. The
step coverage is also not as good as with CVD.
The choice of deposition method (specifically evaporation versus sputtering) may be arbitrary, and may
depend more on what technology is available for the specific material.
Physical deposition includes:
• A thermal evaporator uses an electric resistance heater to melt the material and raise its vapour
pressure to a useful range, where it starts to boil and evaporate. An atomic cloud is formed by
the evaporation of the coating metal in a vacuum environment to coat all the surfaces in the line
of sight between the substrate and the target (source). The vacuum allows the vapour to reach
the substrate without reacting with or scattering against other gas-phase atoms in the chamber,
and reduces the incorporation of impurities from the residual gas in the vacuum chamber. Only
materials with a higher vapour pressure than the heating element can be deposited without
contamination of the film. It is often used in producing thin, ½ µm, decorative shiny coatings on
plastic parts. The thin coating, however, is fragile and wears poorly. The thermal evaporation

process can also coat a thick, 1

mm, layer of heat-resistant materials, such as MCrAℓY - a
metal, chromium, aluminium, and yttrium alloy, on jet engine parts. Molecular beam epitaxy is a
particular sophisticated form of thermal evaporation. A schematic diagram of a typical system
for e-beam evaporation is shown in figure 1.10.
















Figure 1.10. Typical system for e-beam evaporation of materials.
vacuum
pump
wafers
wafer
caroussel
vacuum
source material

to be evaporated
thermoionic
heate
r

water cooled
crucible
e-beam
atom
flux
Power Electronics
17
The principle is the same for all evaporation technologies, only the method used to the heat
(evaporate) the source material differs. There are two popular evaporation technologies, which
are e-beam evaporation and resistive evaporation, each referring to the heating method.
o An electron beam evaporator fires a high-energy beam from an electron gun to boil a
small spot of material; since the heating is not uniform but local, lower vapour pressure
materials can be deposited. The beam is usually bent through a 270° angle in order to
ensure that the gun filament is not directly exposed to the evaporant flux. Typical
deposition rates for electron beam evaporation range from 1 to 10 nm/s.
o In resistive evaporation, a tungsten boat, containing the source material, is heated
electrically with a high current to make the material evaporate. Many materials are
restrictive in terms of what evaporation method can be used (that is, aluminium is quite
difficult to evaporate using resistive heating), which typically relates to the phase
transition properties of that material.
• Sputtering relies on a plasma (usually a noble gas, such as Argon) to knock material from a
target or source, a few atoms at a time, at a much lower temperature than with evaporation. The
coatings, such as ceramics, metal alloys, organic and inorganic compounds, involve connecting
the work-piece and the substance to a high-voltage DC power supply in an argon vacuum
system at 10

-2
to 10
-3
mmHg. The gas plasma is established between the substrate (work-piece)
and the target (donor) and transposes the sputtered-off target ionised atoms to the surface of
the substrate. Because the target is kept at a relatively low temperature, unlike evaporation, this
is a flexible deposition technique. It is especially useful for compounds or mixtures, where
different components would otherwise tend to evaporate at different rates. Sputtering's step
coverage is virtually conformal, producing thin, less than 3 µm, hard thin-film coatings; for
example, titanium nitride (TiN) which is harder than the hardest metal. Sputtering is widely
applied on cutting tools, injection moulding tools, and common tools such as punches and dies,
to increase wear resistance and service life. When the substrate is non-conductive, for example,
a polymer, radio-frequency (RF) sputtering is used. A schematic diagram of a typical RF
sputtering system is shown in figure 1.11a. As for evaporation, the same basic principle applies
to all sputtering technologies. The differences typically relate to the manner in which the ion
bombardment of the target is realized. Magnetron splutter disposition, figure 1.11b, is used to
deposit Aℓ, titanium, and tungsten, although CVD is difficult for alloys, Aℓ-Cu-Si.
• Pulsed laser deposition systems work by an ablation process. Pulses of focused laser light
vaporize the surface of the target material and convert it to plasma; this plasma usually reverts
to a gas before it reaches the substrate.
• Cathodic Arc Deposition or Arc-PVD is a kind of ion beam deposition where an electrical arc is
created that literally blasts ions from the cathode. The arc has an extremely high power density
resulting in a high level of ionization (30 to 100%), multiply charged ions, neutral particles,
clusters, and macro-particles (droplets). If a reactive gas is introduced during the evaporation
process, dissociation, ionization, and excitation occurs during interaction with the ion flux and a
compound film is deposited.

Figure 1.11. Typical sputtering systems: (a) RF (ac) plasma and (b) dc plasma magnetron.


1.3 Thermal oxidation and the masking process

The oxide of silicon, silica, or silicon dioxide (Si0
2
), is an important planar processing ingredient and a
widely used dielectric in semiconductor manufacturing because it facilitates stable insulation and
plasma
(glow
discharge)
-V
dc
or
RF signal

deposited
layer anode
cathode
shield
water cooled
sputter target
cathode
wafer
Gas inlet
vacuum pump
counter
electrode
target
atom
Ar
+

Ar
+



-ve
(a) (b)
Chapter 1 Basic Semiconductor Physics and Technology
18
3 zone
resistance heated furnace
outlet
exhaust

silicon
wafers
Silica
reactor tube
quartz
boat
HCl N
2
0
2
H
2


flowmeters
conformal passivation layers, with a high electric field breakdown strength of 10MV/cm, a resistivity of up
to 10
20
Ωcm, and a 9eV energy band gap. It is a useful and convenient deposition process, used many
times on the silicon wafer surface during device fabrication. Besides the passivation and glass layer
deposited over the surface of the die to protect it from mechanical damage and corrosion, dielectric
layers are also used for isolating components or structures in the active circuit from each other, and as
dielectric structures for MOS transistors and capacitors. Silicon dioxide is used extensively as an
insulating barrier between the gate metal and channel of insulated gate semiconductor switching
devices.
The formation of Si0
2
on a silicon surface is accomplished through a process called thermal oxidation,
which is a technique that uses high temperatures, usually between 700 to 1300°C, to promote the
growth rate of oxide layers. The thermal oxidation of Si0

2
consists of exposing the silicon substrate to a
rich oxidizing atmosphere of oxidisers, 0
2
or H
2
0, at elevated temperature, producing oxide films with
thicknesses ranging from 6nm to 1µm. Oxidation of silicon is not difficult, since silicon naturally tends to
form a stable oxide even at room temperature, provided an oxidizing environment is present. The
elevated temperature used in thermal oxidation accelerates the oxidation process, resulting in thicker
oxide layers per unit of time. This process affords control over the thickness and properties of the Si0
2

layer.
The silicon wafers placed in a furnace containing oxygen gas for three to four hours at 1000°C to
1200°C, form a surface oxide layer of Si0
2,
usually less than 1µm thick. Wet oxidation, with water added,
is about 20 times faster (100nm to 120nm per hour) than dry oxidation (14nm to 25nm per hour) but the
oxide quality is lower. The wafer is effectively encapsulated by silica glass, which prevents penetration
by impurity atoms, except gallium atoms. Selective diffusions or implanting are made in the silicon by
opening windows through the oxide by selective etching with hydrofluoric HF acid following a photo-
resist lithography masking process - see section 1.5.
The oxidation furnace (or diffusion furnace, since oxidation is a diffusion process involving oxidant
species), provides the heat needed to elevate the oxidizing temperature and the typical furnace consists
of:
• a heating system;
• a temperature measurement and control system;
• fused quartz process tubes where the wafers undergo oxidation;
• a system for moving process gases into and out of the process tubes; and

• a loading station used for loading (or unloading) wafers into (or from) the process tubes.
The heating system usually consists of several heating coils that control the temperature around the
furnace tubes. The wafers are placed in quartz glassware called boats, which are supported by fused
silica paddles inside the process tube. A boat can contain many wafers, typically 50 or more. The
oxidizing agent (oxygen or steam) then enters the process tube through its source end, subsequently
diffusing to the wafers where the oxidation occurs. A schematic diagram of a typical wafer oxidation
furnace is shown in figure 1.12.
















Figure 1.12. Typical wafer oxidation furnace.


Depending on the oxidant species used, namely 0
2
or H
2

0, the thermal oxidation of Si0
2
may either be in
the form of dry oxidation, wherein the oxidant is 0
2
or wet oxidation, wherein the oxidant is H
2
0. The
reactions for dry and wet oxidation are characterised by:
In dry oxidation, the oxidising agent is oxygen, 0
2
:

() () ()
2
2
sg s
Si O SiO
+→ (1.25)
During dry oxidation, the silicon wafer reacts with the ambient oxygen (and hydrogen chloride at near
atmospheric pressure), forming a layer of silicon dioxide on its surface, usually less than 100nm thick.
Power Electronics
19
In wet oxidation, used for thick oxides, the oxidising agent is water vapour, H
2
0:

() () () ()
2
22

22
sg sg
Si H O SiO H
+→+ (1.26)
Hydrogen and oxygen gases are introduced into a torch chamber where they react to form water
molecules, which are then made to enter the reactor under high pressure where they diffuse toward the
wafers. The water molecules react with the silicon to produce the oxide and hydrogen gas byproduct.

The oxidation reactions occur at the Si-Si0
2
interface, that is, silicon at the interface is consumed as
oxidation takes place. As the oxide grows, the Si-Si0
2
interface moves into the silicon substrate.
Consequently, the Si-Si0
2
interface will always be below the original Si wafer surface. Si0
2
formation
therefore proceeds in two directions relative to the original wafer surface. Oxidation is the only
deposition technology which actually consumes some of the substrate as it proceeds. The amount of
silicon consumed by silicon dioxide formation is predictable from the relative densities and molecular
weights of Si and Si0
2
. The thickness of silicon consumed is 44% of the final thickness of the oxide
formed, thus an oxide that is 100nm thick will consume about 44nm of silicon from the substrate.
Oxidation processes that have short durations (and during the first 50nm of oxide growth), may be
modelled by a Linear Growth Law equation: x
o
= C (t + τ), where x

o
is the growing oxide thickness, C is
the linear rate constant, t is the oxidation time, and τ is the initial time displacement to account for the
initial oxide layer in situ at the start of the oxidation process. As the process proceeds the oxide growth
rate decreases.

For oxidation processes that have long durations (where the oxide thickness reaches 100nm), the rate
of oxide formation may be modelled by a Parabolic Growth Law equation: x
o
2
= B×t, where x
o
is the
growing oxide thickness, B is the parabolic rate constant, and t is the oxidation time. This equation
shows that the oxide thickness grown is proportional to the square root of the oxidizing time, which
confirms that the oxide growth is hampered as the oxide thickness increases. This is because the
oxidizing species diffusion rate decreases as it has to travel a greater distance through the oxide to the
Si-Si0
2
interface as the oxide layer thickens.

Together the Linear and Parabolic Growth equations are known as the Linear-Parabolic Model. This
oxide growth model is accurate over a wide temperature range (700 to 1,300°C), oxide thicknesses
(20nm to 2µm), and oxidant partial pressures (0.2 to 2.5 atmospheres). An increase in pressure
increases the oxide growth rate, but importantly, allows the temperature to be decreased for a given
growth rate. For every 10 atmospheres of pressure, the temperature can be reduced by 30°C.

Oxide growth is accelerated by an increase in oxidation time, oxidation temperature, or oxidation
pressure. Other factors that affect thermal oxidation growth rate for Si0
2

include:
• the crystallographic orientation of the wafer;
• the wafer's doping level;
• the presence of halogen impurities in the gas phase;
• the presence of plasma during growth; and
• the presence of a photon flux during growth.

Other uses for dielectric layers include:
• masking for diffusion and ion implant processes;
• diffusion from doped oxides;
• overcoating of doped films to prevent dopant loss;
• gettering of impurities (see section 1.12); and
• mechanical and chemical protection.

There are other commonly-used dielectric and isolation materials besides Si0
2
.
Silicon dioxide doped with phosphorus (commonly referred to as P-glass, phospho-silicate glass, or
PSG) is used because it inhibits sodium impurity diffusion and exhibits a smooth topography. Adding
boron to PSG results in boro-phospho-silicate glass. BPSG, flows at lower temperatures than PSG,
850°C to 950°C for BPSG as opposed to 950°C to1100°C for PSG.
Polysilicon Si0
2
with enough oxygen content is also semi-insulating and is used in circuit and surface
junction passivation. Alternately, silicon nitride is an excellent moisture barrier while stoichiometric
silicon nitride is used in oxidation masks and for MOS gate dielectric. These dielectric layers are usually
deposited by sputtering or chemical vapour deposition (CVD). The layer material deposited depends on
the processing reactants.

The oxidising process is restricted to materials that can be oxidized, and only films that are oxides or

nitrides of that material are possible. Silicon nitride, like silicon dioxide, is an amorphous insulating
material that is an excellent moisture and contamination barrier, highly resistant to diffusion, not prone to
delamination or cracking, and forms a progressive conformal layer on silicon. The oxidant is pure
Chapter 1 Basic Semiconductor Physics and Technology
20
ammonia gas NH
3
or an ammonia plasma. Although vastly superior to silicon dioxide, it has a much
higher dielectric constant 7.5 as opposed to 3.85 for silicon dioxide, so is not favoured for power device
insulated gate oxide structures. The disadvantages of silicon nitride are thermal related, namely higher
processing temperatures are needed (950 to 1200C) and the thermal expansion of silicon nitride is twice
that of silicon dioxide. The relative properties of silicon dioxide, Si0
2
, and silicon nitride, Si
3
N
4
, at 300K,
are shown in Table 1.3.


Table 1.3: Properties of silicon dioxide (SiO
2
) and silicon nitride (Si
3
N
4
) at 300K

Properties Si0

2
Si
3
N
4

Structure amorphous amorphous
Melting Point °C ≈ 1600 -
Density g/cm
3
2.2 3.1
Refractive Index 1.46 2.05
Dielectric Constant 3.9 7.5
Dielectric Strength V/cm 10
7
10
7

Infrared Absorption Band µm 9.3 11.5 - 12.0
Energy Gap at 300K eV 9 ≈ 5.0
Linear Coefficient of Thermal Expansion, ∆L/L/∆T 1/K
5 x 10
-7

-
Thermal Conductivity at 300 K λ
W/cm-K 0.014 -
DC Resistivity at 25°C Ohm-cm
10
14

- 10
16
≈ 10
14

DC Resistivity at 500°C Ohm-cm -
2 x 10
13

Etch Rate in Buffered HF nm/min 100 ½ - 1


1.4 Polysilicon deposition

Polysilicon Deposition is the process of depositing a thin-film layer of polycrystalline silicon on a
semiconductor wafer, similar to epi-deposition but processed at much lower temperatures.

Polysilicon, poly-Si is compatible with high temperature processing and interfaces with thermal Si0
2
.
One of its primary uses is as gate electrode material for metal-oxide type devices because it is more
reliable than Aℓ. A polysilicon gate's electrical conductivity may be enhanced by depositing a metal
(such as tungsten) or a metal silicide (such as tungsten silicide) over the gate. It can also be deposited
conformally over steep topography. Heavily-doped poly thin-films are used in bipolar emitter structures.
Lightly-doped poly-Si films may be employed as a resistor, a conductor, or as an ohmic contact for
shallow junctions, with the desired electrical conductivity attained by doping the polysilicon material.
Polysilicon deposition is achieved by thermal decomposition, called pyrolysis of silane, SiH
4
, inside a
low-pressure reactor at a temperature of 580 to 650°C, with the deposition rate exponentially increasing

with temperature. This pyrolysis process involves the basic reaction: SiH
4 (g)
→ Si
(s)
+2H
2 (g)
.
There are two common low-pressure processes for depositing polysilicon layers:
• using 100% silane at a pressure of 25 to 130 Pa; and
• using 20 to 30% silane (diluted in nitrogen) at the same total pressure.
Both of these processes can deposit polysilicon on 10 to 200 wafers per run, at a rate of 10 to 20
nm/min and with thickness uniformities of ± 5%. The critical process variables for polysilicon deposition
include temperature, pressure, silane concentration, and dopant concentration. Wafer spacing and load
size have only minor effects on the deposition process.
The rate of polysilicon deposition R
d
increases rapidly with temperature, since it follows the Arrhenius
equation:

/

a
qE kT
ddo
RRe
−
= (1.27)
where R
d
is the deposition rate,

E
a
is the activation energy in electron volts, eV,
T is the absolute temperature in degrees Kelvin, K,
k is the Boltzmann constant, q is the electron charge, and
R
do
is a constant.
The activation energy for polysilicon deposition is about 1.7eV.
Based on equation (1.27), the rate of polysilicon deposition increases as the deposition temperature
increases. There will be a minimum temperature at which the rate of deposition becomes faster than the
rate at which unreacted silane arrives at the surface. Beyond this temperature, the deposition rate can
no longer increase with temperature, since it is now hampered by the lack of silane from which the