Giáo trình tn kỹ thuật số 402062

TON DUC THANG UNIVERSITY
FACULTY OF ELECTRICAL-ELECTRONICS ENGINEERING
DIVISION OF ELECTRONICS-TELECOMMUNICATIONS

DIGITAL FUNDAMENTAL
Laboratory Manual
Source: Lab-Volt Systems, Inc
Edited by Division of Electronics-Telecommunication

1


Table of Contents
1.

Unit 1 - Fundamental Logic Elements ........................................................................................... 5
EXERCISE 1-1: AND/NAND Logic Functions ................................................................................... 8
EXERCISE OBJECTIVE ............................................................................................................... 8
DISCUSSION ............................................................................................................................... 8
PROCEDURE ............................................................................................................................. 11
REVIEW QUESTIONS ................................................................................................................ 14
EXERCISE 1-2: OR/NOR Logic Functions ..................................................................................... 15
EXERCISE OBJECTIVE ............................................................................................................. 15
DISCUSSION ............................................................................................................................. 15
PROCEDURE ............................................................................................................................. 18
REVIEW QUESTIONS ................................................................................................................ 21

2.

Unit 2 - EXCLUSIVE-OR/NOR Gates.......................................................................................... 22
EXERCISE 2-1: EXCLUSIVE-OR (-NOR) Gate Functions.............................................................. 24

EXERCISE OBJECTIVE ............................................................................................................. 24
DISCUSSION ............................................................................................................................. 24
PROCEDURE ............................................................................................................................. 25
REVIEW QUESTIONS ................................................................................................................ 27
EXERCISE 2-2: Dynamic Response of XOR/ XNOR Logic Gates .................................................. 28
EXERCISE OBJECTIVE ............................................................................................................. 28
DISCUSSION ............................................................................................................................. 28
PROCEDURE ............................................................................................................................. 30
REVIEW QUESTIONS ................................................................................................................ 31

3.

Unit 3 - Flip-Flops........................................................................................................................ 32
EXERCISE 3-1: S/R Flip-Flop ........................................................................................................ 35
EXERCISE OBJECTIVE ............................................................................................................. 35
DISCUSSION ............................................................................................................................. 35
PROCEDURE ............................................................................................................................. 38
REVIEW QUESTIONS ................................................................................................................ 41
EXERCISE 3-2: D Flip-Flop ............................................................................................................ 42
EXERCISE OBJECTIVE ............................................................................................................. 42
DISCUSSION ............................................................................................................................. 42
PROCEDURE ............................................................................................................................. 44
REVIEW QUESTIONS ................................................................................................................ 47

2


4.

Unit 4 - JK Flip-Flop .................................................................................................................... 48

EXERCISE 4-1: Static Operation .................................................................................................... 51
PROCEDURE ............................................................................................................................. 51
REVIEW QUESTIONS ................................................................................................................ 54
EXERCISE 4-2: Dynamic Operation ............................................................................................... 55
EXERCISE OBJECTIVE ............................................................................................................. 55
DISCUSSION ............................................................................................................................. 55
PROCEDURE ............................................................................................................................. 57
REVIEW QUESTIONS ................................................................................................................ 59

5.

Unit 5 - The MULTIPLEXER and DEMULTIPLEXER .................................................................. 60
EXERCISE 5-1: MULTIPLEXER .................................................................................................... 66
EXERCISE OBJECTIVE ............................................................................................................. 66
DISCUSSION ............................................................................................................................. 66
PROCEDURE ............................................................................................................................. 68
REVIEW QUESTIONS ................................................................................................................ 70
EXERCISE 5-2: DEMULTIPLEXER................................................................................................ 71
EXERCISE OBJECTIVE ............................................................................................................. 71
DISCUSSION ............................................................................................................................. 71
PROCEDURE ............................................................................................................................. 74
REVIEW QUESTIONS ................................................................................................................ 76

6.

Unit 6 - ASYNCHRONOUS RIPPLE COUNTER ......................................................................... 77
EXERCISE 6-1: Basic Counter Control Functions .......................................................................... 79
EXERCISE OBJECTIVE ............................................................................................................. 79
DISCUSSION ............................................................................................................................. 79
PROCEDURE ............................................................................................................................. 82

REVIEW QUESTIONS ................................................................................................................ 84
EXERCISE 6-2: Ripple Counter Waveforms ................................................................................... 85
EXERCISE OBJECTIVE ............................................................................................................. 85
DISCUSSION ............................................................................................................................. 85
PROCEDURE ............................................................................................................................. 87
REVIEW QUESTIONS ................................................................................................................ 89

7.

Unit 7 - 4-BIT COMPARATOR .................................................................................................... 90
EXERCISE 7-1: Fundamental Binary Comparisons ........................................................................ 94
EXERCISE OBJECTIVE ............................................................................................................. 94
DISCUSSION ............................................................................................................................. 94
3


PROCEDURE ............................................................................................................................. 96
REVIEW QUESTIONS ................................................................................................................ 99
EXERCISE 7-2: Comparators And Counter Modulus Control ....................................................... 100
EXERCISE OBJECTIVE ........................................................................................................... 100
DISCUSSION ........................................................................................................................... 100
PROCEDURE ........................................................................................................................... 102
REVIEW QUESTIONS .............................................................................................................. 104

4


1. Unit 1 - Fundamental Logic Elements
UNIT OBJECTIVE
At the completion of this unit, you will be able to determine the input/output relationship of logic elements

on the DIGITAL LOGIC FUNDAMENTALS circuit board.

DISCUSSION OF FUNDAMENTALS
In TTL digital circuits, there are two fundamental voltage levels, or logic states: a high state, called a
logic high and equal to +5 Vdc, and a low state, called a logic low and equal to 0 volts.
For practical circuits, each state consists of a minimum and a maximum voltage level. Outside of this
range, the logic circuit cannot reliably determine which logic state to assign. Figure 1-1 illustrates the
operating limits of typical TTL circuits.

Figure 1-1. Operating levels of TTL circuits

In the figure, a voltage level between 0.8 and 2 volts represents an unknown logic state. Logic levels
that operate near the threshold can generate intermittent results because any noise that adds to the
signal will move the input of the gate to the unknown logic state.
Logic high values, represented by 1, range between 2 and 5 Vdc. Logic low values, represented by 0,
range between zero and 0.8 Vdc.
Ones (1) and zeros (0) are used to define the operational tables of standard logic gates and circuits.
Figure 1-2 illustrates two fundamental logic concepts.

Figure 1-2. Logic Concepts

5


In Figure 1-2(a), switches A and B must be closed to illuminate the lamp. Switch A AND switch B must
be activated. If either switch is opened (not activated), the lamp goes off.
In Figure 1-2(b), either switch A or switch B can be closed to illuminate the lamp. Switch A OR switch B
must be activated. Both switches must be opened (not activated) to turn the lamp off.
Switch positions can be related to logic levels. Logic levels are represented by highs (1) or lows (0);
therefore, the standard AND and OR logic functions can be stated with highs and lows (ones and zeros).

This relationship is illustrated by Table 1-1.
Table 1-1

Switch state
OFF
ON

Logic
Level
State
LOW
0
HIGH
1

Boolean equations used to define the input/ output relationships of logic circuits. In place of ones and
zeros, Boolean equations take the form of A and B = C. Figure 1-3 illustrates this circuit notation.

Figure 1-3. Boolean form of notation

In the figure, the Boolean equation A and B = C defines the circuit operation. The expression states that
both switches A and B must be activated (on or high) to illuminate the lamp (C). If a lamp-on condition
is considered a logic high, then both A and B must be high to generate a high output.
Basic logic functions can be complemented. The complement of a logic state is its opposite state. Logic
high and low levels (1 and 0) are complements of each other. Zero (0) is the ones complement of one
(1), while 1 is the ones complement of 0.
The complexity of an IC package determines its classification. In general, IC packages having 12 or less
logic gates are classified as Small Scale Integration (SSI) devices.
IC classification types range from SSI to Very Large Scale Integration (VLSI) and beyond. The
relationship between gate count and classification is illustrated in Figure 1-4.

6


Figure 1-4. IC classification and gate count

7


EXERCISE 1-1: AND/NAND Logic Functions
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operation of an AND and a
NAND logic gate. You will verify your results by generating truth tables for each function.

DISCUSSION
Figure 1-5 shows the schematic symbols of two-input AND and NAND gates.

Figure 1-5. AND and NAND gates

Signal inputs are labeled A and B. Gate outputs are labeled C. The output of the NAND gate is the
complement of the AND operation.
The Boolean equation for the AND gate states that C is high when A and B are high. The AND operation
is indicated by the dot between A and B.
NOTE: A·B and AB without the "·" are identical.
The Boolean equation for the NAND gate states that C is low when A and B are high. The bar over AB
represents the complement of AB.
The NAND gate function has a bubble drawn at the output side of the gate. This bubble indicates a
complement.
Figure 1-6 shows the pin-out configuration for the 74LS00 NAND, SSI IC used in this exercise.

Figure 1-6. 74LS00 NAND, SSI IC

8


In the figure, pins 14 and 7 supply power to the IC. The IC provides four separate two-input NAND gates,
labeled A through D. Each gate provides one output.
For the 74LS00 IC, inputs may be tied to other inputs or outputs may be connected to inputs; however,
outputs cannot be connected to one another.
Unused inputs generally are pulled high (connected to Vcc) through a pull-up. The nominal value of pullup resistors used in LS devices is 18 K-Ohms.
Two NAND gates can be cascaded (connected in series) to generate an AND operation. This
configuration is represented by Figure 1-7.

Figure 1-7. AND gate operation

In the figure, output C provides a NAND response to the circuit inputs (A and B). Output C is
complemented by the action of GATES 2 and 3. In turn, these gates generate AND operations (outputs
D and E) for the same circuit inputs (A and B).
Table 1-2 provides the circuit truth table.
Table 1-2

Inputs
B
1
1
0
0

A
1

0
1
0

Outputs
NAND
AND
C
D or E
0
1
1
0
1
0
1
0

In the table, the outputs are complements of each other. Output column C provides the NAND function
truth table, and output columns D and E provide the AND function truth table.
There are two circuit inputs (A and B). Four unique input conditions test all possible combinations.
A low level at any input disables an AND or a NAND gate. A high level at one input of a two-input AND
or NAND gate enables the gate.
Figure 1-8 illustrates the disable and enable combinations for an AND and a NAND gate.
9


Figure 1-8. AND/NAND gate control combinations.

The truth tables in the figure show that a disabled AND gate locks out its other input and generates a

low level (0) output. A disabled NAND gate also locks out its other input but generates a high level (1)
output.
Enabled AND or NAND gates allow their outputs to be determined by the circuit inputs, as demonstrated
in Figure 1-8.
The operating principles of a two-input AND or NAND gate apply to gates having more than two inputs.
Figure 1-9 shows an eight-input NAND gate (74LS30).

NOTE: Remember that a high
logic level turns on an LED. You
can verify the state of a signal,
as indicated by a circuit LED, by
connecting your multimeter to
the appropriate test point.

Figure 1-9. 8-input NAND gate.

The output of this gate is low only when all inputs are high. Any input at a low level locks out the other
inputs (and output is high).

10


PROCEDURE
1. Locate the AND/NAND circuit block, and connect the circuit shown in Figure 1-10. Activate
BLOCK SELECT. Place both toggle switches in the DOWN position.

Figure 1-10

2. What are the logic levels at the AND gate inputs?
NOTE: In Figure 1-10, circuit input A is connected

to one input (A) of the AND gate and one input (A)
of the NAND gate. Circuit input B is connected to
the other input of each gate.
3. What are the logic levels at the NAND gate inputs?
A= ___________

B= ____________

4. Do the circuit input LEDs confirm your answers to steps 2 and 3?
A= ___________

B= ____________

5. What is the logic level at the output of each gate?
AB = _________

AB = _________

6. Do the output LEDs confirm your answer to step 5?

7. If either toggle switch A or B (not both) were placed in the UP position, what would the effect on
the output be?

8. Place toggle switch A in the UP position. Observe the circuit outputs. Do your results agree with
your step 7 answer?
9. Place toggle switch A in the DOWN position and switch B in the UP position. Observe the circuit
outputs. Do your results agree with your step 7 answer?

10. With the current switch settings, which gate is enabled and which is disabled?
11

11. Place switch A in the UP position. Observe the circuit output LEDs. Are both gates enabled?

12. Does your observation of the AND gate output indicate that the inputs are high or low?

13. Does your observation of the NAND gate output indicate that the inputs are high or low?

14. Based on your data, are the AND and NAND gates used to detect high or low logic levels?
15. Use the toggle switches and LEDs of your circuit board to complete the truth tables of Figure
1-11.

Figure 1-11. AND and NAND truth tables.

16. Are the outputs of the AND and NAND gates complements of each other?

17. Modify your test circuit as shown in Figure 1-12. Connect channel 1 of your oscilloscope to circuit
input B. Use channel 2 to monitor other circuit points as required.
NOTE: LEDs will appear to be constantly on
due to the pulse train input signal. This action
does not alter the expected circuit operation.
You may disable the circuit block LEDs by
removing BLOCK SELECT

12


Figure 1-12

18. Place switch A in the DOWN position. Circuit input signal B is a square wave pulse train

(oscilloscope channel 1 ). Are the gates enabled or disabled? Are the AND and NAND outputs
high or low?

19. Place switch A in the UP position. Monitor the output of each gate. Are the gates allowing the
input signal to pass through because the gates are disabled or enabled by the high input at A?

20. Compare the circuit outputs with the circuit input. What are the signal phase relationships? Refer
to Figure 1-13.

WITH AN INPUT AT A
HIGH LEVEL IGATES
ENABLED)

Figure 1-13

13


REVIEW QUESTIONS
1.

The output of an AND gate is high
a. all of the time.
b. when any input is low.
c. when any input is high.
d. when all inputs are high.

2.

The output of a NAND gate is low

a. all of the time.
b. when any input is low.
c. when any input is high.
d. when all inputs are high.

3.

In the circuit of Figure 1-14, output levels A through D are, respectively,
a. low, high, low, and low.
b. low, high, low, and high.
c. high, low, low, and low.
d. disabled due to the circuit pull-ups and to common connection on the last gate.

Figure 1-14

14


EXERCISE 1-2: OR/NOR Logic Functions
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operation of an OR and a
NOR logic gate. You will verify your results by generating truth tables for each function.

DISCUSSION
Figure 1-15 shows the schematic symbols of two-input OR and NOR gates.

Figure 1-15. OR and NOR gates

Signal inputs are labeled A and B. Gate outputs are labeled C. The output of the NOR gate is the
complement of the OR operation.

The Boolean equation for the OR gate states that C is high when A or B is high. In the equation, the +
symbol indicates OR.
The Boolean equation for the NOR gate states that C is high when A and Bare high. The bar over A+B
indicates the complement of A+B. The NOR gate function has a bubble at the output side of the gate.
This bubble indicates a complement.
Figure 1-16 shows the pin out configuration for the 74LS02 NOR, SSI IC used in this exercise.

Figure 1-16. Typical 74LS02

In the figure, pins 14 and 7 supply power to the IC. The IC provides four separate two-input NOR gates,
labeled A through D. Each gate provides one output.
15


For the 74LS02 IC, inputs may be tied to other inputs, and an output may be connected to inputs;
however, outputs cannot be connected to one another.
Unused inputs are generally pulled low (connected to ground).
Two NOR gates can be cascaded (connected in series) to generate an OR operation, as shown in
Figure 1-17.

Figure 1-17. OR circuit operation

In the figure, outputs D and E both represent OR functions because of the complementary action of
GATES 2 and 3. Each configuration provides the OR circuit function.
Table 1-3 provides the circuit truth table.
Table 1-3. OR/NOR circuit truth table

INPUTS
B
1

1
0
0

A
1
0
1
0

OUTPUTS
NOR
OR
C
D or E
0
1
0
1
0
1
1
0

In the table, the outputs are complements of each other. Output column C provides the NOR function
truth table, and output columns D and E provide the OR function truth table.
Figure 1-18 illustrates the disable and enable combinations for an OR and a NOR gate.
The operating principles of a two-input OR or NOR gate apply to gates having more than two inputs.
Figure 1-19 shows a three-input NOR gate (74LS27).

16


Figure 1-18. OR/NOR gate control combinations

Figure 1-19. 3-input NOR gate

The output of this gate is low when any one input is high. Any one input at a high level locks out the
other inputs (output low).

17


PROCEDURE
1. Locate the OR/NOR circuit block, and connect the circuit shown in Figure 1-20. Activate BLOCK
SELECT. Place both toggle switches in the DOWN position.
NOTE: Remember that a high logic level turns on an LED. You can verify
the state of a signal, as indicated by a circuit LED, by connecting your
multimeter to the appropriate test point.

Figure 1-20

2. What are the logic levels at the OR gate inputs?
NOTE: In Figure 1-20, circuit input A is connected to one input (A)
of the OR gate and one input (A) of the NOR gate. Circuit input B
is connected to the other input of each gate.

A = _________

B = _________

3. What are the logic levels at the NOR gate inputs?
A= __________

B = _________

4. Do the circuit input LEDs confirm your answers to steps 2 and 3?

5. What is the logic level at the output of each gate?
A+B = __________

A+B = __________

6. Do the circuit output LEDs confirm your answer to step 5?

7. If either toggle switch A or B (not both) were placed in the UP position, would the OR and NOR outputs
be locked high or low?
18


8. Place toggle switch A in the UP position. Observe the circuit outputs. Do your results agree with your
step 7 answer?
9. Place toggle switch A in the DOWN position and switch Bin the UP position. Observe the circuit
outputs. Do your results agree with your step 7 answer?

10. With the current switch settings, which gate is enabled and which is disabled?

11. Place switch A in the UP position. Observe the circuit output LEDs. Are both gates disabled?

12. Observe the OR gate output. Does a high on any input lock out the other input? Is the gate output

forced to a high or a low level?

13. Observe the NOR gate output. Does a high on any input lockout the other input? Is the gate output
forced to a high or a low level?

14. Based on your data, are the OR and NOR gates used to detect high or low logic levels?

15. Use the toggle switches and LEDs on your circuit board to complete the truth tables of Figure 1-21.

Figure 1-21. OR and NOR truth tables

16. Are the outputs of the OR and NOR gates complements of each other?

17. Modify your test circuit as shown in Figure 1-22. Connect channel 1 of your oscilloscope to circuit
input B. Use channel 2 to monitor other circuit points as required.

19


Figure 1-22

18. Place switch A in the DOWN position. The circuit input signal is a square wave pulse train
(oscilloscope channel 1). Are the gates enabled or disabled? Does input B pass through to the output?

19. Place switch A in the UP position. Monitor the output of each gate. Are the gates allowing input B to
pass through? Are the gates enabled or disabled?

20. Compare the circuit outputs with the circuit input. What are the signal phase relationships?

20