O''''Reilly Network For Information About''''s Book part 193 pps

power, just like ROM. Two of the hybrid devices, EEPROM and Flash, are
descendants of ROM devices; the third, NVRAM, is a modified version of SRAM.
EEPROMs are electrically-erasable-and-programmable. Internally, they are similar
to EPROMs, but the erase operation is accomplished electrically, rather than by
exposure to ultraviolet light. Any byte within an EEPROM can be erased and
rewritten. Once written, the new data will remain in the device forever—or at least
until it is electrically erased. The tradeoff for this improved functionality is mainly
higher cost. Write cycles are also significantly longer than writes to a RAM, so you
wouldn't want to use an EEPROM for your main system memory.
Flash memory is the most recent advancement in memory technology. It combines
all the best features of the memory devices described thus far. Flash memory
devices are high density, low cost, nonvolatile, fast (to read, but not to write), and
electrically reprogrammable. These advantages are overwhelming and the use of
Flash memory has increased dramatically in embedded systems as a direct result.
From a software viewpoint, Flash and EEPROM technologies are very similar. The
major difference is that Flash devices can be erased only one sector at a time, not
byte by byte. Typical sector sizes are in the range of 256 bytes to 16 kilobytes.
Despite this disadvantage, Flash is much more popular than EEPROM and is
rapidly displacing many of the ROM devices as well.
The third member of the hybrid memory class is NVRAM (nonvolatile RAM).
Nonvolatility is also a characteristic of the ROM and hybrid memories discussed
earlier. However, an NVRAM is physically very different from those devices. An
NVRAM is usually just an SRAM with a battery backup. When the power is
turned on, the NVRAM operates just like any other SRAM. But when the power is
turned off, the NVRAM draws just enough electrical power from the battery to
retain its current contents. NVRAM is fairly common in embedded systems.
However, it is very expensive—even more expensive than SRAM—so its
applications are typically limited to the storage of only a few hundred bytes of
system-critical information that cannot be stored in any better way.
Table 6-1 summarizes the characteristics of different memory types.
Table 6-1. Memory Device Characteristics

Memory
Type
Volatile?

Writeable?
Erase
Size
Erase
Cycles
Relative
Cost
Relative
Speed
SRAM yes yes byte unlimited expensive fast
DRAM yes yes byte unlimited moderate moderate
Masked
ROM
no no n/a n/a inexpensive

fast
PROM no
once, with
programmer
n/a n/a moderate fast
EPROM no
yes, with
programmer
entire
chip
limited

(see specs)

moderate fast
EEPROM

no yes byte
limited
(see specs)

expensive
fast to read,
slow to
write
Flash no yes sector
limited
(see specs)

moderate
fast to read,
slow to
write
NVRAM no yes byte none expensive fast
6.2 Memory Testing
One of the first pieces of serious embedded software you are likely to write is a
memory test. Once the prototype hardware is ready, the designer would like some
reassurance that she has wired the address and data lines correctly and that the
memory chips are working properly. At first this might seem like a fairly simple
assignment, but as you look at the problem more closely you will realize that it can
be difficult to detect subtle memory problems with a simple test. In fact, as a result
of programmer naiveté, many embedded systems include memory tests that would

detect only the most catastrophic memory failures. Some of these might not even
notice that the memory chips have been removed from the board!
Direct Memory Access
Direct memory access (DMA) is a technique for transferring blocks of
data directly between two hardware devices. In the absence of DMA, the
processor must read the data from one device and write it to the other, one
byte or word at a time. If the amount of data to be transferred is large, or
the frequency of transfers is high, the rest of the software might never get
a chance to run. However, if a DMA controller is present it is possible to
have it perform the entire transfer, with little assistance from the
processor.
Here's how DMA w
orks. When a block of data needs to be transferred, the
processor provides the DMA controller with the source and destination
addresses and the total number of bytes. The DMA controller then
transfers the data from the source to the destination automatically. After
each byte is copied, each address is incremented and the number of bytes
remaining is reduced by one. When the number of bytes remaining reaches
zero, the block transfer ends and the DMA controller sends an interrupt to
the processor.
In a typical DMA scenario, the block of data is transferred directly to or
from memory. For example, a network controller might want to place an
incoming network packet into memory as it arrives, but only notify the
processor once the entire packet has been received. By using DMA, the
processor can spend more time processing the data once it arrives and less
time transferring it between devices. The processor and DMA controller
must share the address and data buses during this time, but this is handled
automatically by the hardware and the processor is otherwise uninvolved
with the actual transfer.
The purpose of a memory test is to confirm that each storage location in a memory

device is working. In other words, if you store the number 50 at a particular
address, you expect to find that number stored there until another number is
written. The basic idea behind any memory test, then, is to write some set of data
values to each address in the memory device and verify the data by reading it back.
If all the values read back are the same as those that were written, then the memory
device is said to pass the test. As you will see, it is only through careful selection
of the set of data values that you can be sure that a passing result is meaningful.
Of course, a memory test like the one just described is unavoidably destructive. In
the process of testing the memory, you must overwrite its prior contents. Because it
is generally impractical to overwrite the contents of nonvolatile memories, the tests
described in this section are generally used only for RAM testing. However, if the
contents of a hybrid memory are unimportant—as they are during the product
development stage—these same algorithms can be used to test those devices as
well. The problem of validating the contents of a nonvolatile memory is addressed
in a later section of this chapter.
6.2.1 Common Memory Problems
Before learning about specific test algorithms, you should be familiar with the
types of memory problems that are likely to occur. One common misconception
among software engineers is that most memory problems occur within the chips
themselves. Though a major issue at one time (a few decades ago), problems of
this type are increasingly rare. The manufacturers of memory devices perform a
variety of post-production tests on each batch of chips. If there is a problem with a
particular batch, it is extremely unlikely that one of the bad chips will make its way
into your system.
The one type of memory chip problem you could encounter is a catastrophic
failure. This is usually caused by some sort of physical or electrical damage
received by the chip after manufacture. Catastrophic failures are uncommon and
usually affect large portions of the chip. Because a large area is affected, it is
reasonable to assume that catastrophic failure will be detected by any decent test
algorithm.

In my experience, a more common source of memory problems is the circuit board.
Typical circuit board problems are:
 Problems with the wiring between the processor and memory device
 Missing memory chips
 Improperly inserted memory chips
These are the problems that a good memory test algorithm should be able to detect.
Such a test should also be able to detect catastrophic memory failures without
specifically looking for them. So let's discuss circuit board problems in more
detail.
6.2.1.1 Electrical wiring problems
An electrical wiring problem could be caused by an error in design or production
of the board or as the result of damage received after manufacture. Each of the
wires that connect the memory device to the processor is one of three types: an
address line, a data line, or a control line. The address and data lines are used to
select the memory location and to transfer the data, respectively. The control lines
tell the memory device whether the processor wants to read or write the location
and precisely when the data will be transferred. Unfortunately, one or more of
these wires could be improperly routed or damaged in such a way that it is either
shorted (i.e., connected to another wire on the board) or open (not connected to
anything). These problems are often caused by a bit of solder splash or a broken
trace, respectively. Both cases are illustrated in Figure 6-2.
Figure 6-2. Possible wiring problems

Problems with the electrical connections to the processor will cause the memory
device to behave incorrectly. Data might be stored incorrectly, stored at the wrong
address, or not stored at all. Each of these symptoms can be explained by wiring
problems on the data, address, and control lines, respectively.
If the problem is with a data line, several data bits might appear to be "stuck
together" (i.e., two or more bits always contain the same value, regardless of the
data transmitted). Similarly, a data bit might be either "stuck high" (always 1) or

"stuck low" (always 0). These problems can be detected by writing a sequence of
data values designed to test that each data pin can be set to and 1, independently of
all the others.
If an address line has a wiring problem, the contents of two memory locations
might appear to overlap. In other words, data written to one address will instead
overwrite the contents of another address. This happens because an address bit that
is shorted or open will cause the memory device to see an address different from
the one selected by the processor.
Another possibility is that one of the control lines is shorted or open. Although it
is theoretically possible to develop specific tests for control line problems, it is not
possible to describe a general test for them. The operation of many control
signals is specific to the processor or memory architecture. Fortunately, if there is
a