Chương 7 - Bộ nhớ pps

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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Computer Architecture and
Organization
Miles Murdocca and Vincent Heuring
Chapter 7 – Memory
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Chapter Contents
7.1 The Memory Hierarchy
7.2 Random-Access Memory
7.3 Memory Chip Organization
7.4 Case Study: Rambus Memory
7.5 Cache Memory
7.6 Virtual Memory
7.7 Advanced Topics
7.8 Case Study: Associative Memory in Routers
7.9 Case Study: The Intel Pentium 4 Memory System
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
The Memory
Hierarchy
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Functional Behavior of a RAM Cell
Static RAM cell (a) and dynamic RAM cell (b).
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Simplified RAM Chip Pinout
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
A Four-Word
Memory with
Four Bits per
Word in a 2D
Organization
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
A Simplified Representation of the
Four-Word by Four-Bit RAM
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
2-1/2D Organization of a 64-Word by
One-Bit RAM
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Two Four-Word by Four-Bit RAMs are
Used in Creating a Four-Word by
Eight-Bit RAM
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring

Two Four-Word by Four-Bit RAMs Make
up an Eight-Word by Four-Bit RAM
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Single-In-Line
Memory
Module
• 256 MB dual in-line
memory module organized
for a 64-bit word with 16
16M × 8-bit RAM chips
(eight chips on each side
of the DIMM).
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Single-In-
Line Memory
Module
• Schematic diagram of
256 MB dual in-line
memory module.
(Source: adapted from
http://www-
s.ti.com/sc/ds/tm4en64
kpu.pdf.)
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring

A ROM Stores Four Four-Bit Words
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
A Lookup Table (LUT) Implements an
Eight-Bit ALU
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Flash Memory
• (a) External view of flash memory module and (b) flash module
internals. (Source: adapted from HowStuffWorks.com.)
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Cell Structure for Flash Memory
• Current flows from source to drain when a sufficient negative charge is
placed on the dielectric material, preventing current flow through the
word line. This is the logical 0 state. When the dielectric material is not
charged, current flows between the bit and word lines, which is the
logical 1 state.
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Rambus Memory
• Comparison of DRAM and RDRAM configurations.
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Rambus Memory

• Rambus technology on the Nintendo 64 motherboard (left)
enables cost savings over the conventional Sega Saturn
motherboard design (right).
• Nintendo 64 game console:
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Placement of Cache Memory in a
Computer System
• The locality principle: a recently referenced memory location is likely to
be referenced again (temporal locality); a neighbor of a recently
referenced memory location is likely to be referenced (spatial locality).
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
An Associative Mapping Scheme for a
Cache Memory
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Associative Mapping Example
• Consider how an access to memory location (A035F014)
16
is mapped to
the cache for a 2
32
word memory. The memory is divided into 2
27
blocks
of 2

5
= 32 words per block, and the cache consists of 2
14
slots:
• If the addressed word is in the cache, it will be found in word (14)
16
of a
slot that has tag (501AF80)
16
, which is made up of the 27 most
significant bits of the address. If the addressed word is not in the
cache, then the block corresponding to tag field (501AF80)
16
is brought
into an available slot in the cache from the main memory, and the
memory reference is then satisfied from the cache.
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Associative Mapping Area Allocation
• Area allocation for associative mapping scheme based on bits stored:
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Replacement Policies
• When there are no available slots in which to place a block, a
replacement policy is implemented. The replacement policy governs
the choice of which slot is freed up for the new block.
• Replacement policies are used for associative and set-associative
mapping schemes, and also for virtual memory.

• Least recently used (LRU)
• First-in/first-out (FIFO)
• Least frequently used (LFU)
• Random
• Optimal (used for analysis only – look backward in time and reverse-
engineer the best possible strategy for a particular sequence of
memory references.)
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
A Direct Mapping Scheme for Cache
Memory
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Chapter 7 - Memory
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Direct Mapping Example
• For a direct mapped cache, each main memory block can be mapped to
only one slot, but each slot can receive more than one block. Consider
how an access to memory location (A035F014)
16
is mapped to the
cache for a 2
32
word memory. The memory is divided into 2
27
blocks of
2
5
= 32 words per block, and the cache consists of 2
14

slots:
• If the addressed word is in the cache, it will be found in word (14)
16
of slot
(2F80)
16
, which will have a tag of (1406)
16
.