DEPpart2 pptx
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2/1
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Course contents
•
Digital design
Combinatorial circuits: without status
•
Sequential circuits: with status
•
FSMD design: hardwired processors
•
Language based HW design: VHDL
2/2
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Design of Combinatorial Circuits
•
Minimization of Boolean functions
•
Technology mapping
•
Correct timing behavior
•
Basic RTL building blocks (Adder, ALU,
MUX, …)
2/3
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Design of Combinatorial Circuits
•
Minimization of Boolean functions
Karnaugh map
Minimization with the Karnaugh map
Don’t care conditions
Quine-McCluskey
•
Technology mapping
•
Correct timing behavior
•
Basic RTL building blocks (Adder, ALU,
MUX, …)
2/4
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Design of Combinatorial Circuits
•
Minimization of Boolean functions
Karnaugh map
Minimization with the Karnaugh map
Don’t care conditions
Quine-McCluskey
•
Technology mapping
•
Correct timing behavior
•
Basic RTL building blocks (Adder, ALU,
MUX, …)
2/5
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
•
Motivation:
Assume: F=xy’z+xy’z’
Cost = Σ(fan-in)
complete circuit
= (2)+(3)+(3)+(2) = 10
Delay
Assume: relative gate delay NAND or
NOR or NOT = 0.6 + fan-in * 0.4
Delay = Σ(gate-delay)
critical path
= 1 +
(1.8+1) + (1.4+1) = 6.2
x y z
F=xy’z+xy’z’
2/6
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
•
Motivation:
F=xy’z+xy’z’
=xy’(z+z’)
=xy’
The value of z hence does not matter
Cost = Σ(fan-in)
complete circuit
= (1+2) = 3 i.o. 10
Delay
Assume: relative gate delay NAND or
NOR or NOT = 0.6 + fan-in * 0.4
Delay = Σ(gate-delay)
critical path
= 1 +
(1.4+1) = 3.4 i.o. 6.2
x y z
F
2/7
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
•
Minimization via manipulation of Boolean
expressions is clumsy: no method exists
to select the theorems such that we are
sure to obtain the minimum cost
•
Is it possible to see in the truth table
which input value does not matter?
x y z F
0 0 0 0 -
0 0 1 0 -
0 1 0 0 -
0 1 1 0 -
1 0 0 1 xy’z’
1 0 1 1 xy’z
1 1 0 0 -
1 1 1 0 -
We indeed see easily that the
value of F equals 1 for x=1 and y=0
irrespective of the value of z
We however see this easily only
for z, since only for z the lines
z=0 and z=1 for equal x and y
are consecutive
2/8
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
•
A Karnaugh map contains the same
information as a truth table (each square is
a minterm), but…
•
neighboring squares differ only in the value
of 1 variable!!
x’ x
x
0 1
x’y’ x’y
xy’ xy
x
0
1
y
0 1
x’y’z’ x’y’z
xy’z’ xy’z
x
0
1
yz
00 01
x’yz x’yz’
xyz xyz’
11 10
x
y
z
x’z (y does not matter)
x’y’z x’yz
xy’z’ xyz’
xz’ (y does not matter)
xy’z’ xy’z
xy’ (z does not matter)
2/9
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
m
0
m
1
x
0 1
m
0
m
1
m
2
m
3
x
0
1
y
0 1
0 1
4 5
x
0
1
yz
00 01
3 2
7 6
11 10
x
y
z
2/10
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Karnaugh map
0 1
4 5
xy
00
01
zw
00 01
3 2
7 6
11 10
x
z
w
12 13
8 9
15 14
11 10
11
10
y
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0 1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
Fill out from truth table
2/11
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
1 0
0 1
xy
00
01
zw
00 01
0 0
1 0
11 10
x
z
w
0 1
1 0
1 0
0 1
11
10
y
Minimize
F=x’y’z’w’+x’yz’w+x’yzw+xy’z’w’+xy’zw’+xyz’w+xyzw
F= yw
+xy’w’
+y’z’w’
2/12
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
Implement
F=x’y’z’w’+x’yz’w+x’yzw+xy’z’w’+xy’zw’+xyz’w+xyzw
x y z w
F
Cost = 4*(1) + 7*(4) + 1*(7)
= 39
Delay = 1 + (2.2+1) + (3.4+1)
= 8.6
2/13
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
Implement
F=yw+xy’w’+y’z’w’
x y z w
Cost = 3*(1) + {1*(2)+2*(3)} + 1*(3)
= 14 i.p.v. 39
Delay = 1 + (1.8+1) + (1.8+1)
= 6.6 i.p.v. 8.6
F
2/14
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
0
xy
00
01
zw
00 01 11 10
1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
18 19 17 16
22 23 21 20
30 31 29 28
26 27 25 24
xy
11
10
10 11 01 00
00
01
11
10
x
y
z
w
x
z
w
v
y
Differs from course book
F(v,x,y,z,w)
2/15
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Karnaugh map
0
xy
00
01
zw
00 01 11 10
1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
18 19 17 16
22 23 21 20
30 31 29 28
26 27 25 24
xy
11
10
10 11 01 00
00
01
11
10
x
y
z
w
x
z
w
v
y
40 41 43 42
44 45 47 46
36 37 39 38
32 33 35 34
58 59 57 56
62 63 61 60
54 55 53 52
50 51 49 48
10
11
01
00
x
y
10
11
01
00
x
y
u
F=(u,v,x,y,z,w)
Differs from course book
2/16
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Design of Combinatorial Circuits
•
Minimization of Boolean functions
Karnaugh map
Minimization with the Karnaugh map
Don’t care conditions
Quine-McCluskey
•
Technology mapping
•
Correct timing behavior
•
Basic RTL building blocks (Adder, ALU,
MUX, …)
2/17
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
Determine all prime implicants
Determine all essential
prime implicants
Search for minimal coverage
Create the Karnaugh map
Truth table or
canonical form
2/18
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
Step 1: Create Karnaugh map
w
x
y
z
1
1
F=x’y’z’+wz+xyz+w’yF=x’y’z’+wz+xyz+w’yF=x’y’z’+wz+xyz+w’y
1
1
1 1
11
F=x’y’z’+wz+xyz+w’y
1 1
11
1
1
F=x’y’z’+wz+xyz+w’y
1
1
1 1
11
Rule:
- Take product term per product
term and indicate where in the
Karnaugh map it equals 1
2/19
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
Step 2: Determine all prime implicants
1 1 1
1 1
1 1
1 1 1
w
x
y
z
11
w’x’z’
x’y’z’
1 1
w’y
yz
1 1
1
1
1 11
1
wz
1 11
1
wx’y’
1 11 1
Rule:
- Analyze each 1-minterm
- Determine the largest sub-cube(s)
that contain(s) the minterm and
add them to the list of prime
implicants (without adding an
already listed sub-cube)
2/20
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
Step 3: Determine all essential prime implicants
1 1 1
1 1
1 1
1 1 1
w
x
y
z
w’x’z’
x’y’z’
w’y
yz
wz
wx’y’
1
1
wz
w’y
Rule:
- Search for 1-minterms that are
only contained in 1 prime implicant
- Indicate this prime implicant as
essential
2/21
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
Step 4: Search minimal coverage
w’x’z’
x’y’z’
w’y
yz
wz
wx’y’
1 1 1
1 1
1 1
1 1 1
w
x
y
z
1 1
1 1
1 1
1 1
1
2
0
1
1
1
x’y’z’
F
min
=x’y’z’+w’y+wz
Rule:
- Goal: search for the smallest set of (as big as possible)
prime implicants that contain all 1-minterms
- Take all essential prime implicants as initial list
- Repeatedly add a prime implicant to the list that contains
the largest number of not yet covered 1-minterms. When
there are two that contain the same number of not yet
covered 1-minterms, make a random choice.
- Such a strategy is known as
Greedy strategy
: at each decision point,
take the best choice without looking to future implications
- This does not always lead to a global optimum
2/22
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
•
Original:
F=x’y’z’+w’y+xyz+wz
•
Minimal
F
min
=x’y’z’+w’y+wz
wxyz wxyz
Cost=4*1+2*3+2*2+1*4=18 Cost =4*1+1*3+2*2+1*3=14
=22% cheaper
Delay =(1)+(.6+3*.4+1)
+(.6+4*.4+1)=7
Delay =(1)+(.6+3*.4+1)
+(.6+3*.4+1)=6.6
=6% faster
2/23
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
•
Example 2: F(v,w,x,y,z)
v w x y z F
0 0 0 0 0 0
0 0 0 0 1 0
0 0 0 1 0 0
0 0 0 1 1 0
0 0 1 0 0 0
0 0 1 0 1 0
0 0 1 1 0 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 1 0
0 1 0 1 0 1
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 1 0
0 1 1 1 0 1
0 1 1 1 1 1
v w x y z F
1 0 0 0 0 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 1 1
2/24
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
•
Realisation as sum of 1-minterms:
F=Σ(6,7,10,11,14,15,21,23,25,27,29,31)
v
w
x
y
z
Cost=(5*1)+(12*(5+1))+(1*(12+1))=90
Delay=(.6+1*.4)+(.6+5*.4+1)+(.6+12*.4+1)=11
2/25
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Minimization with the Karnaugh
map
•
Minimisation
Step 1: Create Karnaugh map
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
w
x
y
z z
v
