accurate analog synthesis based on circuit matrix models

UNIVERSITY OF CINCINNATI
Date:
I, ,
hereby submit this original work as part of the requirements for the degree of:
in
It is entitled:
Student Signature:
This work and its defense approved by:
Committee Chair:
11/15/2009 172
8-Sep-2009
Almitra Pradhan
Doctor of Philosophy
Computer Science & Engineering
Accurate Analog Synthesis Based On Circuit Matrix Models
Ranganadha Vemuri, PhD
Harold Carter, PhD
Wen Ben Jone, PhD
Carla Purdy, PhD
Jintai Ding, PhD
Ranganadha Vemuri, PhD
Harold Carter, PhD
Wen Ben Jone, PhD
Carla Purdy, PhD
Jintai Ding, PhD
Almitra Pradhan
Accurate Analog Synthesis With Circuit Matrix Models
A dissertation submitted to the
Graduate School
at the University of Cincinnati
in partial fulfillment of the

requirements for the degree of
DOCTOR OF PHILOSOPHY
in the Department of
Electrical and Computer Engineering and Computer Science
of the College of Engineering
2009
by
Almitra Pradhan
Bachelor of Engineering (EE)
Veermata Jeejabai Technological Institute (V.J.T.I.), Mumbai University
June 2002
Thesis Advisor and Committee Chair: Dr. Ranga Vemuri
Abstract
Automated synthesis is imperative for the rapid design of analog circuits. Knowledge based and
optimization based methods have emerged to provide solutions for analog synthesis, especially for
device sizing. Posing analog sizing as a constrained optimization problem facilitates the application
of many well developed algorithms for this purpose. All optimization based sizing methods are
based on the common thread of design space exploration and performance evaluation. Design space
exploration is required for finding design solutions satisfying the given performance constraints.
During exploration a performance evaluator is required to determine the quality of the examined
solutions.
The efficiency of the sizing procedure is completely dependant upon the speed of the perfor-
mance evaluator. Some of the recently proposed techniques construct models for performance pa-
rameters in the circuits design space and use them for performance prediction. Methods based on
this principle can be collectively called Performance Macromodeling methods. Avoiding simulation
gives the advantage of fast synthesis to these methods at the expense of moderate modeling errors.
Performance macromodeling methods can rapidly explore the design space and offer sizing solu-
tions in a reasonable time. However, they are successful only for synthesizing those specifications
who models have been developed.
In this dissertation we propose performance prediction using Circuit Matrix Models to estimate

the performance of analog circuits. Using these models the entire a.c. behavior of the circuit is
captured. With the use of matrix models, the limitation that a circuit can by synthesized for the
modeled performance specifications is eliminated. Any linear performance characteristic can be
calculated from the models. Analog circuits need to be designed with high accuracy. With circuit
matrix models it is seen that performance prediction is precise and synthesized circuits are very
accurate.
We then develop techniques to expedite synthesis by making matrix model evaluation extremely
fast. The first technique uses hashing for obtaining the desired speedup. This technique takes
advantage of matrix elements being dependent on a subset of design variables. Design sub-spaces
are visited several times when the entire space is being explored in a synthesis run. Hash tables save
the matrix element values computed in the visited subspace and reuse them when that subspace is
visited again. This saves a large amount of recomputations and imparts speedup to the synthesis
procedure.
i
The second technique has a nearest neighbor searching algorithm at its core. It uses values at
design points visited to incrementally compute values at neighboring design points. A first order
Taylor series approximation is sufficient for such incremental computation and this makes per-
formance estimation procedure extremely fast. A balanced box decomposition tree data structure
makes detecting exact or approximate neighbors quite efficient. The circuit design variables form
the dimensions of the search space. The distance metric for neighbor computation is modified by
considering sensitivity of matrix elements to the search space dimensions. Using this method, very
few computations are required during the synthesis process.
Layout parasitics are detrimental to the performance of analog circuits. Considering their effects
early in the design flow is essential for achieving designs with parasitic closure. We have developed
circuit matrix models inclusive of parasitic effects. The models use area and perimeter as predictor
variables and can be used to compute parasitic inclusive matrix element values for many geometries.
Thus, the most suitable geometry for component modules is selected dynamically by the optimizer
as a part of synthesis. Operational amplifiers and filter topologies have been synthesized as a part
of this work.
The optimization objectives for analog circuits can be conflicting and often for improving a

particular performance several others have to be sacrificed. Considering the performance tradeoffs
is quite important for such multi-objective optimization problems. The developed circuit matrix
models have been used to generate parasitic-aware pareto-optimal performance curves. The method
stores an archive of non-dominated performance points and the corresponding design points that
achieve this performance. This can be used for determining the limits of achievable performance
for a given topology as well as for sizing.
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iii
Acknowledgments
I would like to thank Dr. Ranga Vemuri for his guidance that helped shape this dissertation. His
advice helped the research direction, explore several ideas, and refine experiments and publications
developed during the course of this work. My committee members, Dr. Wen-ben Jone, Dr. Hal
Carter, Dr. Carla Purdy and Dr. Jintai Ding, offered helpful suggestions which have further im-
proved this work and my sincere thanks to them. This work was funded in part by the grant from
National Science Foundation (CCF-0429717)which made this research work possible.
DDEL has been a great place to work and I would like to thank Angan, Shubhankar, Bala,
Vijay - my colleagues for the most part here, for allowing me to learn from their experience, the
encouragement when the going was rough and the discussions that sometimes helped put things
in perspective. Coffee breaks in the lab with Annie, Mike, Surya, Pritesh and others have given
moments of respite which were valuable, especially on difficult days. I would also like to thank Dr.
Anuradha Agarwal for responding to my queries even after graduating from the lab.
Cincinnati became a home away from home thanks to great support from my friends, the whole
of ’Cinci Friends’ group, Ketaki and many others. These times spent enjoying and arguing, cele-
brating or just relaxing will be cherished forever. I would also like to thank my colleagues from
the Graduate School office who have been a great bunch and with whom I really enjoyed working
during both my stints there.
I would never have been here but for my parents who always encouraged me to pursue higher
educational goals and have been a constant source of encouragement. My younger sister Asmita and
my extended family back home have been a great support system for me. I would also like to thank
my mother-in-law, Mrs. Anjali Salgaonkar for being encouraging about my educational aspirations.

Nothing has been more important in the completion of this dissertation than the support of my
husband, Dr. Vasant Salgaonkar. We were both enrolled in doctoral programs at the same time, but
things did not seem too difficult due to his patience, help and support. Vasant has been a constant
source of encouragement through the completion of this research work which had its ups and downs
but none that seemed overwhelming thanks to his support. We made it !!
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Contents
List of Figures x
List of Tables xiii
1 Introduction 1
1.1 Overview of the synthesis process . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Alternatives for analog circuit synthesis . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Desirable Macromodel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Research Approach and Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 Circuit Matrix Models for Accurate Performance Estimation 17
2.1 Introduction to Circuit Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Modeling Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Circuit Matrix Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2 Reducing number of models . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 Data Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.4 Fitting Models for the Matrix Elements . . . . . . . . . . . . . . . . . . . 24
2.4 Description of Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 Accuracy of the developed models . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.6 Estimation using Performance Macromodels . . . . . . . . . . . . . . . . . . . . . 31
v
2.7 Synthesis Using Circuit Matrix Models . . . . . . . . . . . . . . . . . . . . . . . 33
2.7.1 Synthesis with common performance specifications . . . . . . . . . . . . . 33
2.7.2 Synthesis with non-standard specifications . . . . . . . . . . . . . . . . . 34

2.7.3 Alternate forms of target specifications . . . . . . . . . . . . . . . . . . . 36
2.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 Hash Classes for Efficient Synthesis 38
3.1 Review of Hashing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1.1 R-B trees for implementing hash tables . . . . . . . . . . . . . . . . . . . 40
3.2 The Concept of Hash Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Partial Solutions in SA based search . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4 Proposed synthesis flow using hash tables . . . . . . . . . . . . . . . . . . . . . . 44
3.5 Hash Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6 Estimation of Speedup by Hashing . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.7 Integrating Hash Classes in the Synthesis Flow . . . . . . . . . . . . . . . . . . . 47
3.8 Experiments to determine speedup with hash tables . . . . . . . . . . . . . . . . . 48
3.8.1 Single Ended Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.8.2 High Gain Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . 52
3.9 Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4 Sensitivity Based Near Neighbor Search 57
4.1 Limitation of the hashing approach . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Calculation of matrix values by incremental updates . . . . . . . . . . . . . . . . . 58
4.3 Algorithms for Near(est) Neighbor Search . . . . . . . . . . . . . . . . . . . . . . 59
4.4 The Optimal Nearest Neighbor Search Algorithm . . . . . . . . . . . . . . . . . . 61
4.4.1 Distance Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5 Multi-dimensional Near Neighbor Search for Analog Synthesis . . . . . . . . . . . 62
4.6 Method for computing allowable perturbations . . . . . . . . . . . . . . . . . . . . 63
4.7 Algorithm for synthesis with sensitivity based near neighbor searches . . . . . . . 64
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4.8 Experiments to determine synthesis speedup . . . . . . . . . . . . . . . . . . . . . 65
4.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5 Layout-aware Synthesis with Module Geometry Selection 69
5.1 Need for Layout-Aware Circuit Models . . . . . . . . . . . . . . . . . . . . . . . 70

5.2 Parasitic Aware Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2.1 Schematic Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2.2 Device Parasitic Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.3 Models for Non-Device Parasitics . . . . . . . . . . . . . . . . . . . . . . 75
5.3 Synthesis with Dynamic Geometry Selection . . . . . . . . . . . . . . . . . . . . 77
5.4 Proposed Layout-Aware Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . 78
5.5 Experiments and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.5.1 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.5.2 Fourth Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.5.3 Dynamic Geometry Selection . . . . . . . . . . . . . . . . . . . . . . . . 82
5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 Pareto-optimal Circuit Performance Curves 85
6.1 Related work for Pareto-optimal performance curve generation . . . . . . . . . . . 86
6.2 Layout-aware Pareto-optimal curves using circuit matrix models . . . . . . . . . . 88
6.3 Extracting the Pareto-Optimal Performance Curves . . . . . . . . . . . . . . . . . 91
6.3.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.2 Front Generation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.3 Improving the Efficiency of Pareto Curve Generation . . . . . . . . . . . . 95
6.3.4 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.5 Sizing procedure using a generated Pareto Front . . . . . . . . . . . . . . 97
6.4 Experiments and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7 Additional applications of the efficient SA algorithm 104
7.1 SA description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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7.2 Problem characteristics suitable for using the new SA algorithm . . . . . . . . . . 105
7.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.1 Recursive determinant calculation . . . . . . . . . . . . . . . . . . . . . . 106
7.3.2 Circuit performance variability calculation . . . . . . . . . . . . . . . . . 109
7.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8 Conclusions and Future Work 112
8.1 Summary of Research Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.3.1 Combined circuit matrix models and symbolic performance models for syn-
thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.3.2 Reduced circuit matrices for fast performance evaluation . . . . . . . . . . 117
Bibliography 120
A Simulated Annealing Library for Circuit Synthesis 129
A.1 Generic SA optimizer description . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.2 Optimization results achieved through the SA library . . . . . . . . . . . . . . . . 130
A.2.1 Holder table Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
A.2.2 Cross in tray function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
A.2.3 Crown cross function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
A.2.4 Bukin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
A.2.5 Bird function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
A.2.6 Egg holder function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
A.2.7 Giunta function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
A.2.8 Styblinski-Tang function . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
A.2.9 Chichinadze function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
A.2.10 McCormick function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
A.2.11 Zettle function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
A.2.12 Levy function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
viii
A.2.13 Three hump camel back function . . . . . . . . . . . . . . . . . . . . . . . 138
B Benchmark circuits used for analog synthesis 139
B.1 Operational Transconductance Amplifier . . . . . . . . . . . . . . . . . . . . . . . 139
B.2 Two stage Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
B.3 High Gain Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
B.4 Single Ended Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 143

B.5 Fourth Order Sallen Key Low Pass Filter . . . . . . . . . . . . . . . . . . . . . . . 144
B.6 Second Order Band Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
ix
List of Figures
1.1 General description in an analog top-down design flow . . . . . . . . . . . . . . . 2
1.2 Bottom-up analog flow considering trade-offs . . . . . . . . . . . . . . . . . . . . 3
1.3 Optimization based analog sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Circuit synthesis alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Summary of the proposed approach . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 (a) Performance Modeling Approach (b) Matrix Modeling Approach . . . . . . . . 19
2.2 OTA circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Phase Margin vs. Device Width of OTA . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Matrix Element vs. Device Width of OTA . . . . . . . . . . . . . . . . . . . . . . 21
2.5 TSO schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6 DA schematic [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.7 Actual vs. Modeled Frequency Response of the OTA . . . . . . . . . . . . . . . . 29
2.8 Actual vs. Modeled Frequency Response of the TSO . . . . . . . . . . . . . . . . 30
2.9 Actual vs. Modeled Frequency Response of Differential Amplifier . . . . . . . . . 30
2.10 (i) Amplifier used in bpf (ii) Active band pass filter schematic . . . . . . . . . . . . 35
2.11 Synthesizing filter from Frequency Response . . . . . . . . . . . . . . . . . . . . 36
3.1 A Simple Two Stage Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 Proposed Approach: Fast SA based Circuit Synthesis with Hashing . . . . . . . . . 44
3.3 Table for a Hash Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 The Single Ended Operational Amplifier (SEO) . . . . . . . . . . . . . . . . . . . 50
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3.5 SEO Expt A: Speedup by hashing . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6 SEO Expt B: Speedup by Reinforced Hashing . . . . . . . . . . . . . . . . . . . . 52
3.7 SEO Expt C: Average and Best Speedup by Reinforced Hashing . . . . . . . . . . 53
3.8 DA Expt A: Speedup by hashing . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.9 DA Expt B: Speedup by Reinforced Hashing . . . . . . . . . . . . . . . . . . . . 55

3.10 DA Expt C: Average and Best case speedup by Reinforced Hashing . . . . . . . . 56
4.1 Neighbor detection using variable sensitivities . . . . . . . . . . . . . . . . . . . . 62
4.2 Convergence time for synthesized circuits . . . . . . . . . . . . . . . . . . . . . . 67
5.1 Effect of geometry on device parasitics (i) ad=48p pd=52.8u as=48p ps=52.8u (ii)
ad=24p pd=45.6u as=36p ps=68.4u . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2 Parasitic Estimation Error Ignoring Geometry . . . . . . . . . . . . . . . . . . . . 74
5.3 Proposed Flow - Synthesis using Parasitic Aware Circuit Matrix Models . . . . . . 79
5.4 Performance Prediction Accuracy using Proposed Models in SEO Synthesis . . . . 82
5.5 Performance Prediction Accuracy using Proposed Models in BSKF Synthesis . . . 83
6.1 Overview of the Proposed Approach . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.2 An Operational Amplifier Circuit (SEO) . . . . . . . . . . . . . . . . . . . . . . . 90
6.3 Effect of layout parasitics on Pareto-optimal performances . . . . . . . . . . . . . 90
6.4 Pareto-Optimal performance sets . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.5 Three MOSA algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6 Pareto front generated by the three MOSA methods . . . . . . . . . . . . . . . . . 94
6.7 Reduction in Hash Table Misses for MOSA run on SEO . . . . . . . . . . . . . . . 96
6.8 Accuracy comparison - Model v/s Simulation based Front . . . . . . . . . . . . . . 98
6.9 SEO: (i) PM (deg) vs UGF (KHz) (ii) BW (KHz) vs UGF (KHz) . . . . . . . . . . 99
6.10 Differential Amplifier Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.11 DA: (i) BW (kHz) vs PM (deg) (ii) UGF (KHz) vs BW (KHz) . . . . . . . . . . . 101
6.12 Bandpass Filter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.13 BPF:(i) Gain (dB) vs BW (Hz) (ii) Gain (dB) vs Q . . . . . . . . . . . . . . . . . 102
8.1 Performance estimation from a PRIMA reduced MNA matrix . . . . . . . . . . . . 118
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A.1 Holder Table Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
A.2 Cross in Tray Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
A.3 Crown Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
A.4 Bukin 6 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
A.5 Bird Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
A.6 Giunta Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

A.7 Styblinski Tang Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
A.8 Chichinadze Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
A.9 McCormick Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
A.10 Zettle Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A.11 Levy Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A.12 Three hump camel Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
B.1 Operational Transconductance Amplifier (OTA) . . . . . . . . . . . . . . . . . . . 140
B.2 Two stage Operational Amplifier (TSO) . . . . . . . . . . . . . . . . . . . . . . . 141
B.3 High Gain Differential Amplifier (DA) . . . . . . . . . . . . . . . . . . . . . . . . 142
B.4 Single Ended Operational Amplifier (SEO) . . . . . . . . . . . . . . . . . . . . . 143
B.5 Sallen Key Low Pass Filter (LPF) . . . . . . . . . . . . . . . . . . . . . . . . . . 144
B.6 Second Order Band Pass Filter (BPF) . . . . . . . . . . . . . . . . . . . . . . . . 145
xii
List of Tables
2.1 Entropy and Local Differential Variation of OTA . . . . . . . . . . . . . . . . . . 22
2.2 Reduction of Matrix Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Modeling Accuracy for OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 Design variable ranges for Benchmarks . . . . . . . . . . . . . . . . . . . . . . . 27
2.5 Worst Case Validation Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6 Performance Estimation Accuracy with Proposed Approach . . . . . . . . . . . . 31
2.7 Estimation Accuracy by Direct Performance Modeling . . . . . . . . . . . . . . . 32
2.8 Modeling and Estimation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.9 Differential Amplifier Synthesis with Partial Model Evaluation . . . . . . . . . . . 34
2.10 Synthesis results for the band pass filter . . . . . . . . . . . . . . . . . . . . . . . 35
3.1 Mapping between Matrix Elements and Design Variables . . . . . . . . . . . . . . 43
3.2 Hash Class Details for Benchmark Circuits . . . . . . . . . . . . . . . . . . . . . 50
3.3 Analog Circuit Synthesis With Matrix Models . . . . . . . . . . . . . . . . . . . . 56
4.1 Performance Estimation Accuracy for Allowable Variable Perturbation . . . . . . . 64
4.2 Speedup for Benchmark Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3 Results for Analog Circuit Synthesis using Proposed Method . . . . . . . . . . . . 68

5.1 Effect of Parasitics and Module Geometry on Performance for a Single Ended Op-amp 71
5.2 Accuracy of Device Parasitic Models for Various Layout Geometries . . . . . . . . 76
5.3 Device Parasitic Modeling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.4 Synthesis Result for SEO with Layout Parasitics . . . . . . . . . . . . . . . . . . . 81
xiii
5.5 Synthesis Result for BSKF with Layout Parasitics . . . . . . . . . . . . . . . . . . 83
5.6 Results for Dynamic Geometry Selection During Synthesis . . . . . . . . . . . . . 84
6.1 Validating Model Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2 Comparison of three MOSA algorithms . . . . . . . . . . . . . . . . . . . . . . . 95
6.3 Speedup using proposed method (compared to simulation) . . . . . . . . . . . . . 98
6.4 Circuit sizing from Pareto curve (SEO) . . . . . . . . . . . . . . . . . . . . . . . . 102
7.1 Optimizing matrix determinant through a Hashed SA algorithm . . . . . . . . . . . 109
7.2 Performace variation (UGF) due to perturbations in the nominal design variable value111
B.1 BM1: OTA details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
B.2 BM2 : TSO details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
B.3 BM3 : DA details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
B.4 BM4 : SEO details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
B.5 BM5 : LPF details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
B.6 BM6 : BPF details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
xiv
Chapter 1
Introduction
Integrating digital and analog components on a single chip has ushered in a new era towards the
design of innovative consumer applications. We see increasingly complex mixed signal designs in-
corporating high performance analog and RF blocks especially in telecom and multimedia. Analog
circuitry is unavoidable for interfacing and conditioning signals from the real world with digital and
DSP blocks. Since the success of competing products is strongly tied to their time-to-market, fast
design and manufacture is of critical importance. Arguably, the design on analog systems is set to
become even more challenging in the future [2].
Design automation and IP reuse have always formed the cornerstones of the fast growth of the IC

industry. The market for digital design tools is fairly mature and creating digital designs comprising
of million gates is not often considered a challenge. As opposed to that, analog circuits though
only a fraction of the size of their digital counterparts have not lent themselves easily to automation.
Analog circuits are many a times handcrafted and designer experience and expertise play a major
role in achieving a good design. Unfortunately, expert analog designers are always in short supply.
Moreover, a manual design process partially contributes towards analog and mixed-signal design
being a bottleneck in the design flow.
The need for good automation tools for the design of analog circuits and systems is undeniable.
EDA tools are required for various aspects in the design flow. Of particular importance are the areas
of analog circuit synthesis, behavioral model development, model order reduction, layout synthesis
and system level verification. The focus of our work is the development of robust tools for the
circuit synthesis problem.
1
1.1 Overview of the synthesis process
Circuit synthesis is a process where given a set of high level specifications, a detailed design
meeting the stated requirements is generated. An analog system may be designed flat or hierar-
chically using either a top-down flow or a bottom-up one. [3, 4] offer a good review of various
synthesis methods. This section presents an overview of the circuit synthesis flows available for
analog design.
In a top-down flow, starting from the system level specifications, an architecture is chosen com-
prising of hierarchical blocks optimized at the system level. Propagating constraints from the system
level hierarchically downwards to the block level is a vital task and forms an independent area of
study. Once the constraints are propagated downwards upto the analog cell level, an architecture is
chosen for each cell. This is known as topology selection.
Cell
Requirements
Technology
Parameters
Finished Cell
Design

Topology
Selection
Circuit Sizing
Layout
Generation
Extraction
Simulation and
Verfication
System Architecture
Design
Overall
System
Specs
Propagate Constraints
to sub-blocks
Block 1
Block 2
Block n
Verify System
Spec n
Spec 1
Figure 1.1: General description in an analog top-down design flow
At this stage, each cell or block is designed to meet the derived cell level specifications. Thus for
a given circuit topology, we need to size the individual components in order to meet the specifica-
tions. This is known as the circuit sizing problem. Sizing examines the circuit at the transistor level
and derives a satisfactory set of component values meeting the objective performance. This can be
2
an overwhelmingly time consuming process. In the event a cell design is infeasible or is unable to
meet the specifications, the hierarchy needs to be climbed up again to select a different architecture.
Most analog circuits that are designed in a top-down fashion use steps shown in fig 1.1.

A top-down flow does not easily yield to examining design tradeoffs which is very important in
any design process. A bottom-up procedure is more beneficial in this respect. In a bottom up flow,
each cell level block has its tradeoffs described in the form of a pareto optimal front. These tradeoffs
can be propogated hierarchically upwards to the system level and the designer can consider what
system-level tradeoffs are available by interchanging several lower-level blocks. Fig 1.2 shows the
performance tradeoff propagation.
System
Figure 1.2: Bottom-up analog flow considering trade-offs
After the entire analog system has been designed by following either an hierarchical or flat
design methodology, the verification step follows. Thus system level design, cell level synthesis,
verification form some of the important research problems in the field of analog synthesis. In this
dissertation work we are interested in the developing methods at the analog cell level. The next
section presents several alternative methodologies developed by researchers in the field of analog
synthesis and surveys some notable work in this domain.
3
1.2 Alternatives for analog circuit synthesis
Analog cell level synthesizers perform the task of obtaining a valid design solution at the transis-
tor level which satisfies the assigned specifications for a given process technology. Analog synthesis
tools are designed in two flavors,
Variable topology and sizing: These tools address two areas, topology selection and circuit siz-
ing, simultaneously. The only input provided is the target specifications the circuit should achieve.
Both the circuit assembly from device level components (topology) and device dimensions (size)
that satisfy the requirements are obtained at the output.
Some of the important contributions in topology selection and sizing are now reviewed. Maulik
et al. [5] proposed the first simultaneous topology selection and sizing algorithm. They formulate
synthesis as a Mixed-Integer Non-Linear Programming (MINLP) problem. Binary variables are
used to select the topology and integer variables for the device dimensions. Branch and bound
method was used to solve the MINLP and synthesize the final circuit. The technique found good
designs however obtaining the underlying performance equations in terms of topology and sizing
variables is an extremely arduous task. SEAS [6] and DARWIN [7] also tackle the topology and

sizing problem using evolutionary techniques. In the former many intermediate topologies are sized
resulting in a wasted effort while the later overcomes this problem by using a fast transfer function
estimator. MOJITO [8] is another evolutionary technique that performs a multi-topology and multi-
objective sizing in an effort to build a library of analog components.
Sizing for a fixed topology: In this set of synthesis methods, the focus is on the sizing problem.
Topology selection and circuit sizing are considered separately. The topology is chosen either based
on heuristics or may be application based. The circuit synthesis problem is then defined as, given
a circuit topology find device dimensions such that the target specifications are satisfied. This
problem, known as the circuit sizing problem, itself is a hard problem for which a lot of research
efforts have been invested since the past decade. With sizing itself being a hard task, the variable
topology and sizing problem severely compounds in complexity so far limiting research efforts in
that direction.
Several interesting research directions have been under investigation for the circuit sizing prob-
lem. Most of the circuit sizing techniques fall into two broad categories:
4
• Knowledge based synthesis
• Optimization based synthesis
Knowledge based synthesis: These methods largely rely on the domain-knowledge of experi-
enced analog designers in the development on synthesis tools. The underlying idea is to capture and
emulate the designers knowledge in the form of rules and thus automate the sizing process. Knowl-
edge based methods were notable contributors in the early automated synthesis tools. OASYS [9]
is a hierarchical circuit synthesis framework. Designer knowledge is used to consider tradeoffs and
explore the space of designable circuits. In OPASYN [10], topology selection is heuristic followed
by sizing employing designer derived analytical equations. IDAC [11] provides a framework to
integrate analog expertise in a software paradigm that stores knowledge of circuit schematic, of the
circuit class (e.g. cascode circuits) and function (e.g. amplifier stabilization), while BLADES [12]
uses an set of rules to organize the circuit equations.
The dependence on designer expertise limit such methods from being easily extensible. For
example, in order to design a new circuit or integrate a new component a large number of analytic
equations have to be manually derived. This makes such tools cumbersome for practical usage. The

desire to develop tools that are not overly reliant on the designer has produced the second class of
synthesis methods which are based on optimization.
Optimization based synthesis: These methods use robust optimization algorithms to develop
parametric optimization tools for analog synthesis. No a-priory knowledge is necessary for this
category of tools making them adaptable and attractive to any class of circuits. The synthesis flow
for optimization based methods is described in fig 1.3.
The circuit topology, process parameters and design requirements are provided as an input. De-
sign variables which include widths and lengths of transistors and bias voltage or current are iden-
tified for the circuit. The goal of the synthesis tool is to find numerical values for design variables
(sizes) such that the design requirements are satisfied.
The circuit synthesis problem is modeled as a constrained optimization problem. The goal is
to minimize the circuit area while satisfying some numerical constraints on characteristics such as
gain, bandwidth among others. Thus, the synthesis requirement is formulated as a cost function
given by:
5
Specifications
Topology,
Design
Variables
Specs Met ?
Y
N
Final Sizing
Figure 1.3: Optimization based analog sizing
minimize
x
k
∑
i=1
w

i
. f
i
(x) s.t.g(x) ≤ 0 (1.1)
Here f
i
(x) describes the objectives to be satisfied. Since the objectives may conflict with each
other, the set of weights w
i
is used to determine their relative importance. The synthesized circuit is
also required to meet the constraints represented by g(x). The constrained optimization problem is
often converted to that of unconstrained optimization such as
minimize
x
k
∑
i=1
w
i
. f
i
(x) + w
j
.g
j
(x) ≤ 0 (1.2)
Techniques such as simulated annealing, genetic algorithms, geometric programming can be
used to implement the optimizer. The synthesis procedure starts with a randomly selected (or user
supplied) starting solution. Any design solution supplied by the optimizer is called a candidate
solution. The quality of the design is evaluated for each candidate. The candidate satisfying all

design requirements is sought by the optimizer. Each new solution is a slight perturbation over the
current candidate solution. The synthesis loop iterates till a satisfactory design solution is obtained.
It is typical to visit several thousand unsatisfactory solutions before a candidate that fulfills the
design requirements can be found. Observing the optimization based synthesis flow of fig. 1.3
suggests that the design evaluator is a critical component in this method. The evaluator verifies
the quality of each candidate solution and thus is needed at each iteration of the flow. Optimiza-
6
tion based synthesis methods can be classified based on the class of evaluators they use. Design
evaluators may belong to one of the following classes:
• Numerical simulation based
• Partial simulation techniques
• Numerical model based
Numerical simulation based: Simulation based methods rely on a numerical simulator, usually
the ubiquitous SPICE program, to evaluate design solutions. Using spice for evaluation guarantees
that the design solution obtained is highly accurate. Additionally, since numerical analysis is used
for circuit evaluation manual derivation of performance equations are not required. Out of the
various methods available for synthesis, the simulation methods achieves the best accuracy with
limited set up time.
DELIGHT.SPICE [13], one of the earliest optimization based methods, has an interactive op-
timization algorithm (DELIGHT) combined with a numerical simulator (SPICE). Designer inter-
action is required making this approach somewhat knowledge based. A good initial solution is
provided to the synthesis tool. The tool also comprises of a library of good optimization functions.
The starting solution is fine tuned to obtain a satisfactory design. SPICE is used to numerically
analyze the design while it is being locally optimized. Medeiro et al. [14], relax the requirement of
a good starting solution and synthesize circuits starting from an arbitrary point in the design space
lending greater flexibility to the approach.
MAELSTROM [15] improves the numerical simulator based synthesis by adding some new fea-
tures targeted to make the environment user friendly and efficient. It offers the designer a choice of
various simulators by encapsulating them but hiding their implementation details. A robust com-
bined genetic/annealing algorithm helps better design space exploration. A network of parallel

workstations makes the tool more efficient. ANACONDA [16] and ASF [17] have some similar
features but uses improved optimizing algorithms such as stochastic pattern search and parallel re-
combinative simulated annealing respectively.
Simulation based methods have the advantage of a SPICE level accuracy of the results. However,
using a simulator at each iteration of the loop makes the synthesis procedure very time consuming.
With optimization based methods, a large part of the design space has to be explored in order to find
7
a good design solution. Using a slow performance evaluator results in requiring hours or even days
to find a good solution limiting the efficacy of simulator based synthesis.
Partial simulation based: This set of synthesis methods comprises those that attempt to over-
come the speed limitation of simulation based synthesis. Simulators are still used but in a restricted
manner. These include symbolic simulators and simulation-lite procedures. Symbolic simulators
such as ISSAC [18] are an improvement over knowledge based equation driven procedures. In
those the equations that determine the circuit performance are hand derived. This makes it difficult
to adapt them to new topologies and circuits. Symbolic simulators on the other hand automatically
derive performance equations parametric in circuit variables. Operating point analysis is still re-
quired however all modes of simulation are not required. OPTIMAN [19] combines a symbolic
simulator with an optimizer to automate the synthesis process. Symbolic analysis has also been
used in [20, 21, 22, 23, 24, 25, 26, 27].
Symbolic simulators are useful for viewing the circuit transfer function as symbolic expressions.
The effect of any element on the transfer function can be judged. However, most of the times the
symbolic terms are quite complex which makes interpreting them difficult. Moreover, the size of
the symbolic expression grows exponentially with circuit size. Thus symbolic expressions have
to be limited to relatively smaller circuits or some sort of approximation techniques have to be
incorporated.
Another synthesis procedure that uses a partial simulation based approach is ASTRX/OBLX [28].
Here a simplified numerical simulator (AWE) is used for analyzing the circuits. The asymptotic
waveform estimator, AWE, projects the circuit to a reduced subspace by matching only the first
2q-1 moments. The circuit response is approximated which enables a speedy but less accurate
simulation.

Numerical model based: The need for faster circuit evaluators cannot be undermined in the
design of efficient synthesis methods. Faster evaluators accelerate design exploration making the
optimization based procedures tractable. Model based methods are developed on the premise of pro-
viding a fast circuit analysis environment while compromising accuracy as little as possible. Models
generated using circuit simulation data are used to predict the circuit quality during optimization.
The need for numerical simulation is moved out of the synthesis loop which lends speedup to model
based techniques. Each differs in both accuracy and complexity depending on the fitting algorithms
used to generate the model. Some of the notable published techniques are reviewed here.
8
Wolfe et al. [29] as well as Doboli et al. [30] use Neural Networks for modeling the performance
parameters of the circuits. A Neural networks is constructed for each performance parameter and it
is extensively trained till it shows a good prediction accuracy in the design space.
Support Vector Machines (SVMs) have been incorporated as a classification mechanism when
modeling large design spaces. SVMs developed in the domain of machine learning are used to clas-
sify points based on whether or not they satisfy a complex and unknown property. Ding et al. [31]
used SVMs to predict whether a design point belongs to the feasible design space thus simplifying
the model generation. SVMs are also used by Bernardinis et al. [32] along with randomized test
procedures to limit the number of false positives (infeasible points falsely classified as feasible) and
by Kiely et al. [33].
Han et al. [34] used multivariate adaptive regression splines in the construction of the macro-
model. Here, the entire design space is not modeled at once. Instead a combination of simulation
and modeling is used for performance prediction. When a new candidate is generated an adaptive
sampling scheme is used to selectively update the response surface model. This makes the model
generation distributed over the synthesis process and reduces the initial setup time. Wolfe et al.
[35] also proposed the use of splines using an adaptive sampling grid. Their modeling is completed
before starting the synthesis. Boosted regressors [36], posynomials [37], krigging are some other
modeling methods that researchers have investigated.
In [38], McConaghy et al. have compared and contrasted a number of synthesis methods that
use numerical model generation. It is observed that constructing a good model for performance
parameters is a challenging task due to their non-linear nature. With increasing complexity of the

modeling methods, the macromodel generation time increases. Although some methods may give
better results than others, typically all macromodeling methods suffer from inaccuracies due to their
limitations in modeling a complex and non linear performance parameter space.
1.3 Desirable Macromodel Characteristics
A number of techniques are available for the synthesis of analog circuits. Due to limitations of
knowledge based techniques, optimization based procedures have gained preference for automatic
synthesis of analog circuits. In the presence of multiple alternatives in implementation, the question
arises as to what makes a good optimization based technique? Some of the desirable properties of
9