ECE 590: Digital Design Using HDL
IMAGE PROCESSING USING FPGA
Submitted by:
Sumitha Ajith
Saicharan Bandarupalli
Mahesh Borgaonkar
Contents
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2. Introduction
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3. Hardware and Software
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4. Phase 1: FPGA Implementation of VGA Display with SRAM as Video
Memory
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4.1 VGA Controller Design
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4.1.1 Introduction to VGA Controller
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4.1.2 VGA Signal Timing
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4.1.3 HDL Implementation of the VGA Controller
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4.1.4 Understanding the Interfacing details with FPGA
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4.1.5 Sync Signal Generation, Testing and Results
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4.1.6 Bitmap generation logic using Block RAM
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Using Block Ram as Video Memory to display Image on VGA Monitor
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4.1.8 Generating 16-bit VGA Color Output
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4.2 Memory Controller
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4.2.1 Role of SRAM Memory Controller
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• mem: is asserted to 1 to initiate a memory operation.
• rw: specifies whether the operation is a read (1) or write (0) operation.
• data_f2s: is the 16-bit data to be written to SRAM (the _f2s suffix stands for FPGA to
SRAM).
• data_s2f_r: is the 16-bit registered data retrieved from SRAM (the _s2f suffix stands for
SRAM to FPGA).
• data_s2f_ur: is 16-bit unregistered data retrieved from SRAM.
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• ready: is a status signal indicating whether the controller is ready to accept a new
command. This signal is needed since a memory operation may take more than one clock
cycle.
• ce_n (chip enable): disable or enable the chip
• we_n (write enable): disable or enables write operation.
• Oe_n (output enable): disables or enables the output.
• Lb_n (lower byte enable): disable or enable lower byte of the data bus.
• Ub_n (upper byte enable): disables or enables the upper byte of the data bus.
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4.2.2 Block Diagram of Memory Controller
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4.2.3 Timing Requirement
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4.2.4 Design 1: Safe Design – Back-to-back memory access time 60ns.
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4.2.5 Design 2: Using Xilinx ISE DCM for Faster Access Time
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