Ferroelectric gating of graphene chap 3

Chapter 3
Fabrication and experimental
setups
This chapter outlines the experimental techniques used in subsequent chapters. Sec-
tion 3.1 describes two different graphene film synthesis approaches which are used
in this dissertation; section 3.2 presents the process of fabricating GFET devices,
which will be the starting point for experiments covered from chapter 3 to chapter 7;
Section 3.3 presents the preparation of ferroelectric thin films, which will be used in
experiments from chapter 3 to chapter 6; Section 3.4 is devoted to charge transport
measurement schemes used throughout the rest of the thesis.
3.1 Graphene fabrication
Since its first discovery, the synthesis and growth of graphene films has been central
to graphene research and its potential applications. Here we introduce two different
approaches to graphene synthesis.
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26
Single layer
SiO
2
substrate
Multi-layer
Bilayer
Figure 3.1: Optical image of single layer, bilayer and multilayer graphene on Si/SiO
2
substrate. The scale-bar is 10 μm.
3.1.1 Mechanical exfoliated graphene
Graphene is obtained by the mechanical exfoliation method from Kish graphite sources.
Adhesive tape (Scotch tape) is used as a holder of the graphite source and repeti-
tive folding and peeling processes are required in order to split graphite crystals into
increasingly thinner pieces. When these graphite pieces are thin enough (optically
transparent), they are directly transferred onto Si/SiO

2
substrate by rubbing at the
back side of these graphite piece through the tape. Finally, the supporting tape is
gently peeled off from the Si/SiO
2
substrate, leaving tiny pieces of graphene as well
as small graphite randomly distributed on the top of the SiO
2
surface.
After cleaving, optical microscopy is used for preliminary identification of graphene
as shown in Fig. 3.1. Based on the contrast difference, one can distinguish single layer
and few layer graphene on SiO
2
substrates. Raman spectroscopy or atomic force
27
microscopy is used to further verify the exact graphene layer number and quality.
0.00
0.15
Thickness (nm)
Wavelength (nm)
b
a
0.05
0.10
0.15
0.00
100 300 4002000
Wavelength (nm)
Contrast
Figure 3.2: (a) Color plot of the contrast as a function of wavelength and SiO

2
thickness (reproduced using equals in [79]). (b) Extracted single contrast curve as a
function of SiO
2
thickness, the corresponding wavelength is 550 nm.
The reason why one can see monolayer graphene with the naked eye is due to the
interference effect induced by the SiO
2
layer. Indeed, the thickness of the SiO
2
layer
significantly affects the visibility of monolayer graphene, as shown in Fig. 3.2. As
we can see clearly, 285 nm and 90 nm thickness SiO
2
layer provide the best contrast
28
for the detection of graphene flakes with bare eyes. Using this model, one can also
identify the visibility of graphene on other substrates [79].
3.1.2 Chemical vapor deposition of graphene
Temperature ( C)
O
Time (min)
b
a
c
Figure 3.3: (a) Growth parameters of large-scale graphene using chemical vapor de-
position method; (b) Optical image of thermal furnace and copper foils for graphene
growing. (c) 30-inch large-scale graphene after transferred onto transparent substrates
[44, 50].
Although the mechanical exfoliation method can provide single crystal graphene

flakes, this method is not a scalable technique. The mechanically exfoliated graphene
films is limited to small sizes (usually ≈ 1000 μm
2
), thus incompatible with industrial
requirements. To address this challenge, significant efforts have been devoted to
29
Figure 3.4: Optical image of a graphene field effect transistor devices on Si/SiO
2
substrates.
develop graphene synthesis at a large scale. Among the different approaches, chemical
vapor deposition method exhibits very promising results. Using this method, thirty
inch graphene membranes with decent electronic quality have been demonstrated
recently, as shown in Fig. 3.3 [44].
The working principle of this method essentially follows the bottom up strategy.
The growth of graphene begins from the assemblage of carbon atoms at elevated
temperature under certain gas flows. Using a copper substrate, graphene is grown
by a surface-catalyzed process rather than a precipitation process, making large-scale
monolayer graphene continuous and uniform [44]. To grow wafer scale uniform mono-
layer graphene, a carbon-containing stock gas, i.e., benzene, ethane or methane is
injected into the high temperature furnace and undergoes a dehydrogenation process
on a catalytic surface such as Cu or Ni. As a result, the carbon atoms rearrange into
a honeycomb lattice [49, 50, 80].
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3.2 Fabrication of graphene field effect transistor
GFET
3.2.1 GFET devices using mechanically exfoliated graphene
After graphene is transferred onto a 300 nm SiO
2
over doped silicon, it is ready to be
fabricated into devices for electrical transport studies. The position of graphene flakes

is determined with respect to pre-defined alignment marks. A single layer of 495 K
molecular weight Polymethyl Methacrylate (PMMA) is spin-coated at 4000 rpm onto
the samples, then baked at 180
o
C for 2 minutes. A subsequent standard electron
beam lithography (EBL, 30 KeV) process locates the graphene samples and defines
thermally evaporated electrodes (Cr/Au = 5/30 nm) on top, followed by a liftoff
process in acetone. Depending on the needs of specific experiments, the contact pads
are designed to either Hall-bar geometry or four-terminal configuration (Fig. 3.4).
Sometimes, a second EBL step is performed to pattern graphene into a specific shape
followed by oxygen plasma etching. The doped silicon is used as the gate electrode
(back gate) and the SiO
2
as the gate dielectric in transport measurements.
Although the back gate provided by heavily doped silicon yields many interesting
transport phenomena [17, 81], it represents only the first step towards more complex
graphene devices. Thus, fabrication of dual gated structures such as lateral graphene
p-n or p-n-p junction devices is sorely needed for further studies [19, 39, 82]. Figure
3.5 shows the ferroelectric top gated device structure using the metal mask approach.
The top dielectric that we are using is ferroelectric copolymer P(VDF-TrFE).
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a
b
Figure 3.5: (a) Schematics of a graphene-ferroelectric p-n-p junctions; (b) Optical
image of a graphene-ferroelectric p-n-p junction device fabricated using metal mask
method. Scale bar is 5 μm.
3.2.2 GFET devices made out of chemical vapor deposition
graphene
Unlike the mechanically exfoliated graphene, the chemical vapor deposition method
makes monolayer graphene much more easily accessible. After CVD graphene growth,

a thin layer of PMMA resist is coated on top of the graphene/copper structure,
after which the copper foil is etched using Ammonium Persulfate (APS). With the
mechanical support from PMMA, the PMMA/graphene hybrid structure can be easily
transferred to any other substrate [50]. After standard EBL process and thermal
evaporation, a second EBL step is required to pattern the etching channel, followed
by oxygen plasma treatment to isolate the electrodes. Taking advantage of the large-
scale nature of CVD graphene, dozens of graphene devices can be fabricated within
a single chip, thus enhancing the device yield, as shown in Fig. 3.6.
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a
b
etching channel
Figure 3.6: (a) Optical image of an array of GFET devices on SiO
2
substrate. Scale
Baris500μm; (b) Hall-bar and four-terminal GFET devices and the patterned
etching channel for device separation. Scale Bar is 10 μm.
3.3 Ferroelectric dielectric preparation and char-
acterization
In this section we present the preparation and characterization of ferroelectric thin
films (ferroelectric organic polymer and inorganic ferroelectrics) used. The ferro-
electric organic polymer needed is a copolymer made from poly(vinylidene fluoride)
(PVDF) and Trifluorethylene (TrFE) (Available from PIEZOTECH). The P(VDF-
TrFE) (72/28) precursor solution is made by dissolving polymers in a solvent of mixed
dimethylformamide and acetone (1:1 by volume) [83].
The preparation of P(VDF-TrFE) solution consists of the following steps:
• Prepare the solvent consisting of a mixture of acetone and DMF with a compo-
sition of 50:50 by volume
• Add P(VDF-TrFE) to the solvent such that the P(VDF-TrFE) to the solvent
has a ratio 10:90 by mass. The specific ratio may be varied for variation in

thickness of P(VDF-TrFE) thin film. In our experiments, we utilized 5:95 ratio
33
70 nm
b
c
a
Topography
Topography
Phase
y
y
180 nm
0.0 nm
β-phase
d
Topography
Phase
100 nm
0.0 nm
0.0 nm
Figure 3.7: (a) Optical image and AFM scanning of spin-coated P(VDF-TrFE) on
graphene flakes. Scale bar is 15 μm. (b), (c) Comparison of P(VDF-TrFE) mor-
phology and phase diagram at short/long annealing time. Scale bars are 400 nm. (d)
Comparison of XRD results of both sufficient and insufficient annealed P(VDF-TrFE)
film.
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(500 nm) and 10:90 ratio (1 μm).
• Completely dissolve the P(VDF-TrFE) solution at 50
o
C for 2 hours.

• Apply P(VDF-TrFE) solution onto the substrate and start the spin-coating
process.
• Dry the spin-coated sample on a hotplate at 100
o
C for 10 mins.
• Further anneal the sample in an oven at 135
o
C for 20 hours. Note that suffi-
cient thermal annealing is critical for the formation of ferroelectric β-phase, as
shown in Fig. 3.7a-c. When the annealing time is insufficient, the formation
of the ferroelectric phase is poor, limiting its ferroelectric performance. After
sufficient annealing, a predominant phase transition from the paraelectric phase
to ferroelectric phase transition occurs, leading to the highly crystalline nature
of P(VDF-TrFE) film (Fig. 3.7d).
Furthermore, the compatibility of P(VDF-TrFE) and ferroelectric inorganic film
PZT with commonly used solvent, i.e., MIBK, IPA and Acetone is tested. The results
show that P(VDF-TrFE) is compatible with MIBK and IPA. However, either e-beam
irradiation or an Acetone rinse will effectively change or remove P(VDF-TrFE) film.
As expected, PZT is compatible with MIBK, IPA, Acetone, and e-beam irradiation.
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3.4 Transport measurements and experimental set-
ups
For transport measurements, we used a quasi-DC (low-frequency AC) measurement
scheme with four-probe configurations in order to exclude contact resistance. The di-
agram for the quasi-DC measurement setup is shown in Fig. 3.8a. A lock-in amplifier
is used to act as a low frequency signal source. The voltage signal generated by the
lock-in amplifier is converted into a current signal determined by V/Rs, given that Rs
 R
device
, which is usually the case in measuring graphene. A Keithley source meter

is used to provide a gate voltage to tune the carrier density of graphene. The typical
values of the resistors used are 10 MΩ and a typical AC frequency used is 13.373 Hz.
The measurement configuration technique for the ferroelectric top gated devices
is illustrated in Fig. 3.8b. The poling of ferroelectric thin film is realized by the
application of a DC voltage to the top contact. In this architecture, graphene serves
as the bottom contact for the polarization of ferroelectric thin film. The resistance
change of graphene as a function of the ferroelectric polarization is recorded by the
lock-in amplifier.
The experimental setup for electronic transport measurements in variable tem-
perature insert is shown in Fig. 3.9. Leads from the GFET device are bonded onto
the chip carrier using a wire bonder. The chip carrier is then inserted to the sample
holder mounted on the VTI probe. The VTI insert is designed such that the sample
can be heated up to 400 K for high vacuum thermal annealing, which is critical to
removing resist residues and water contaminants.
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I
a
Lock-in
Amplifier
Rs
Input A
Rg
Keithley Source
Meter 6430
Computer
Digital
Singal
Input B
b
Figure 3.8: (a) Schematics of a quasi-DC measurement of the electronic properties of

GFET devices. (b) Diagram of a GFeFET device measurement strategies.
37
b
a
Figure 3.9: Variable temperature insert (VTI) electrical transport measurement
setup. (a) Overview of 16T VTI setup; (b) Optical image of the sample holder
in the end of the rotating probe.