CRITICAL DIMENSION AND TEMPERATURE CONTROL IN MULTI ZONE THERMAL PROCESSING 2

i
Acknowledgements
I would like to express my deepest gratitude to my supervisor, Professor Ho Weng
Khuen, for his excellent guidance and consistent support throughout my grad-
uate research at the National University of Singapore. I have indeed benefited
enormously from the insightful advice and instruction that he offered in our dis-
cussions. Without his dedicated help, this thesis would have been impossible. I
would also like to express my appreciation to Professor Ling Keck Voon for his
help rendered to my research in Multiplexed Model Predictive Control.
I would also like to acknowledge the National University of Singapore for the
generous scholarship and research facilities. I am also extremely thankful to my
friends and colleagues: Dr. Fu Jun, Dr. Chen Ming, Dr. Yan Han, Dr. Wang
Yuheng, Dr. Shao Lichun, Mr. Nie Maowen, Mr. Chua Teck Wee, Mr. Ngo Yit
Sung, and many others working in the Advanced Control Technology Laboratory.
I have enjoyed the excellent cooperation during the experiment implementation
and entertaining time spent on the badminton court with them. We have all
contributed to the conducive and congenial working environment.
ii
Finally and most importantly, my heartfelt thanks to my parents and girl-
friend for their love and support. Their love is my impetus to overcome difficulties
faced not only in research but also in my daily life. I would have never reached
so far without their constant encouragement and support.
iii
Contents
Acknowledgements i
Table of Contents iii
Summary vii
List of Tables ix
List of Figures x
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Warpage Effects in Lithography . . . . . . . . . . . . . . . 3
1.1.2 Multiplexed MPC in Lithography . . . . . . . . . . . . . . 4
iv
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 Improvement of CD Uniformity by Real-Time Temperature
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Experimental Evaluation of MMPC Computation Load . . 7
1.2.3 Derivation and Experimental Verification of MMPC ISE
formula for PEB process . . . . . . . . . . . . . . . . . . . 8
1.3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 CD and Real-Time Temperature Control for Warped Wafers 10
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Thermal Modeling of the Baking Process . . . . . . . . . . . . . . 15
2.3 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.3 Real-Time Control . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
v
3 Introduction to Multiplexed MPC and its Computational Load
Evaluation 32
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 An Introduction to Multiplexed MPC . . . . . . . . . . . . . . . . 34
3.3 Multi-Zone Bake Plate Thermal Modeling . . . . . . . . . . . . . 41
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Integral Square Error Performance of Multiplexed MPC 54
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2 ISE Formula for Multiplexed MPC . . . . . . . . . . . . . . . . . 56
4.3 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5 Conclusion 71
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
vi
Bibliography 76
Author’s Publications 87
vii
Summary
This thesis investigates the application of advanced process control for thermal
processing in the lithography step to improve lithography performance as the final
Critical Dimension (CD) uniformity is sensitive to temperature during thermal
processing.
Wafer warpage affects the thermal processing in lithography and can result in
CD nonuniformity. Real-time temperature control is proposed and demonstrated
in the thesis that real-time control of the post-exposure bake temperature to give
a non-uniform temperature distribution across a warped wafer can reduce CD
non-uniformity across the wafer.
Multiplexed Model Predictive Control (MMPC) has recently been proposed
as a strategy to reduce computational complexity. It is experimentally demon-
strated in the thermal processing step that MMPC has computational advantage
over the Standard MPC (SMPC), for large horizon and when constraints are
present. The reduction in computational load can be used gainfully to increase
viii
sampling rate and improve thermal processing performance.
To provide a framework for systematic analysis of the MMPC, a formula
to compute the Integral Square Error (ISE) performance for load disturbance is
derived and validated on a multi-zone semiconductor manufacturing thermal pro-
cess. Experimental results validate the formula and show that shorter sampling
time can result in faster recovery of bake-plate temperature when a cold wafer is

placed on the bake-plate.
ix
List of Tables
2.1 Thermophysical Properties . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Thermal Capacitances and Resistances. . . . . . . . . . . . . . . . 17
2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Maximum Computation Time of MMPC and Standard MPC with
Varying Horizon . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1 Experimental and Theoretical Results for different sampling periods 68
x
List of Figures
2.1 Baking of Flat Wafer 1. Solid-line: center, Dashed-line: edge . . . 13
2.2 Baking of Warped Wafer 4, Solid-line: center, Dashed-line: edge . 14
2.3 The bake-plate used in the experiment. . . . . . . . . . . . . . . . 15
2.4 Baking of Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Critical dimension measurements. Circle: center; Square: edge;
Wafer 1–3: flat wafer with conventional baking; Wafer 4–6: warped
wafer with conventional baking; Wafer 7–9: flat wafer with opti-
mized baking; Wafer 10–12: warped wafer with real-time on-line
adjustment of bake-plate temperature setpoints . . . . . . . . . . 21
2.6 Temperature measurement on a warped wafer with no photoresist
nor pattern. Solid-line: center, Dashed-line: edge . . . . . . . . . 24
2.7 Bake-plate setpoint adjusted to give uniform CD for Flat Wafer 7.
Solid-line: center, Dashed-line: edge . . . . . . . . . . . . . . . . . 26
xi
2.8 Center-zone average air-gap versus bake-plate maximum tempera-
ture drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9 Edge-zone average air-gap versus bake-plate maximum tempera-
ture drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.10 Bake-plate setpoints adjusted in real-time once warpage was de-

tected to give uniform CD for Warped Wafer 10. Solid-line: center,
Dashed-line: edge . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1 Patterns of input moves for Standard MPC (left), and for the Mul-
tiplexed MPC (right). . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Experimental Temperature Responses (Solid) and Temperature
Response of the Model (Dashed) . . . . . . . . . . . . . . . . . . . 44
3.3 Experimental temperature disturbance (’x’) and Step Response of
the Disturbance Transfer Function (Solid) . . . . . . . . . . . . . 46
3.4 Performance and computation time of MMPC and Standard MPC
with N
u
= 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5 Performance and computation time of MMPC and Standard MPC
with N
u
= 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6 Performance and computation time of MMPC and Standard MPC
with N
u
= 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
xii
3.7 Maximum Computation Time in the experiment. . . . . . . . . . 53
4.1 Temperature Responses of MMPC with sampling interval 0.4s (Solid)
and 1.0s (Dashed-dot) superimposed with simulation (Dashed) . . 69
4.2 Comparison of Experimental (’x’) and Theoretical (’o’) ISE . . . . 70
1
Chapter 1
Introduction
1.1 Motivation
Lithography has been one of the fundamental technologies in semiconductor man-

ufacturing. In modern microelectronics manufacturing, lithography alone com-
prises about 30% of the entire chip manufacturing cost [1] and accounts for 40%
to 50% of the total production cycle time [2]. Lithography is also seen as the key
driver in scaling down device size, and historically, advances of lithography have
significantly reduced wafer fabrication cost and improved circuit performance [3].
The Critical Dimension (CD) or the linewidth of the photoresist pattern is
the key output in lithography. The shrinkage of CD has the most impact on
chip speed and performance [1]. For instance, both propagation delay and drain
2
current are proportional to the inverse of the channel length which is determined
by CD. It is assessed that 1nm variation in gate CD results in 1MHz variation in
chip speed [4].
Thermal pro cessing is integrated as part of lithography, including various
baking steps such as the post-apply bake, post-exposure bake and post-develop
bake [5]. Thermal processing has been identified as one major source of CD
variation [6]. The most temp erature sensitive thermal process in lithography is
the post-exposure bake (PEB) process [7]. The PEB step stimulate the chemical
amplification process for most of chemically amplified resists (CARs). For 193nm
CARs, a representative PEB latitude for CD variation is about 7-10nm/
◦
C [8].
Temperature sensitivity of KrF resists is on the order of 2-16nm/
◦
C [9]–[10]. For
commercially available deep ultraviolet (DUV) resists, a representative sensitivity
of 8 nm/
◦
C was reported in [11]–[12]. The resists quoted are used in the DUV
process and the nominal CD is 200 nm.
The high sensitivity of CD variation to temperature implies that CD can be

controlled by the temperature control in thermal processing, especially in PEB.
Zhang et al. [13] showed that the implementation of an advanced thermal pro-
cessing system in PEB could reduce CD variation by 40%. Zhang et al. [14] and
Lee et al. [15] also showed that CD variation could be reduced by adjusting PEB
temperature through a multi-zone bake plate. Specifically, temperature unifor-
mity among the thermal processing system of PEB is critical to CD uniformity
3
enhancement[6, 8, 16, 17, 18, 19].
Thermal processing of semiconductor wafers is commonly performed by plac-
ing the substrate on a heated bake-plate for a given period of time. Currently,
multiple zone bake plate is implemented to obtain fast dynamic temperature re-
sponse, which is beneficial to apply real time process control and maintain tight
tolerances of the temperature [20]. A state-of-the-art 49-zone bake-plate with a
Linear Quadratic Gaussian (LQG) controller has been proposed in [21].
The implementation of advanced process control (APC) has shown perfor-
mance improvement in lithography process [20, 22]. However, as the photolithog-
raphy industry moves to bigger substrate and smaller CD, the stringent require-
ments for lithography thermal processing still persists [23]. Stresses from silicon
wafer processing may cause wafer warpage [24], which will affect the resist pro-
cessing at the various baking steps and eventually affect the CD in lithography.
Another challenge is that a computationally amenable algorithm is required to
apply real-time APC methodology in multi-zone bake plate temperature control
to meet the more and more stringent requirements.
1.1.1 Warpage Effects in Lithography
Warpage is one challenge for PEB processing of wafers [24] [25]. One factor that
contributed to warpage was stress [24]. [26] studied the influences of Warpage on
4
baking temperature, and gave quantitative results as 1
◦
C change for a warpage

level of 50 µm through simulation studies. Such variation will cause substantial
CD nonuniformity.
Since warpage is usually different from wafer-to-wafer, measurement of warpage
is essential for CD nonuniformity compensation. The warpage can be measured
by various methods [27]. The shadow and projection Moire techniques are widely
used warpage measurement methods [28]. Warpage can also be measured through
capacitive probes [29] and through the pneumatic-electromechanical effects [30].
All these methods have the advantage that they can give the precise profile of
the warped wafer. However, one disadvantage is that they are off-line and need
extra processing time to obtain the warpage information. Further, the delay be-
tween the exposure and the PEB steps needs to be reduced due to post-exposure
delay effect of chemically amplified resists [31]. This would eliminate any time
consuming measurement between these two steps. One objective of this thesis
is to adopt an in-situ warpage detection method for proper PEB processing of
warped wafers to obtain CD uniformity.
1.1.2 Multiplexed MPC in Lithography
Model Predictive Control (MPC) has been widely used in industries. It has
advantage in multivariate control systems and can deal with constrains by nature.
Previous study in [32] shows that for a 3 × 3 multivariate system, MPC could
5
performs equally with PI control in error tracking, but outperforms in energy
consumption. However, the on-line computational load required by Standard
MPC can be a limiting factor when MPC is applied to complex systems with fast
dynamics or to embedded applications where computational resources are limited.
In the thermal pro cessing of lithography, to meet the more and more stringent
requirements in temperature control, a state-of-the-art 49 zone bake plate has
been proposed. As the number of bake plate zone is up to 49, computational load
will be a concern in real time control of bake plate using standard MPC.
A variant of Model Predictive Control, called Multiplexed MPC, or MMPC,
has been proposed recently [33] and stability results for MMPC have also been es-

tablished [34]. The motivation for MMPC was to reduce real-time computational
load on multivariable systems. It has been applied on a multi-zone bake-plate and
has been demonstrated experimentally that MMPC has the potential to respond
and recover faster than standard MPC when disturbance takes place [35]. As
the close-loop performance is affected by many factors, for example the sampling
rate, the MMPC design for the thermal process needs to be further investigated.
1.2 Contributions
In this thesis, the application of real time process control of warped wafer and
MMPC control algorithm to meet some stringent requirements in lithography
6
is investigated. This thesis will address three areas: 1) Improvement of CD
uniformity by real-time temperature control for warped wafers during PEB, 2)
Derivation and validation of a formula to compute the Integral Square Error (ISE)
performance of a MMPC controlled thermal system, 3) Experimental evaluation
of MMPC computational load carried out on a multi-zone thermal system.
1.2.1 Improvement of CD Uniformity by Real-Time Tem-
perature Control
A real-time temperature control method will be proposed to improve CD unifor-
mity for warped wafers. It is noted that bake plate temperature will drop to a
maximum value before recovering to the set point. It is also noted that flat wafer
and warped wafer give different maximum temperature drop. Thus wafer warpage
can be detected from the maximum temperature drop. Once the warpage is de-
tected, the bake plate temperature can be adjusted in real-time accordingly to
reduce wafer temperature variations. The wafer-to-wafer CD variation compen-
sation will be demonstrated experimentally.
There are also temperature and CD nonuniformity across the wafer due to
the different air-gap at different location. To realize within-wafer CD uniformity,
a multizone bake plate is used, with the capability to bake different zones to
different temperature independently. When the maximum temperature drops of
7

different bake plate zones are recorded, the warpage can be detected. Bake plate
temperature for different zones can be adjusted independently to compensate for
the wafer temperature and CD variations. The method will be demonstrated
experimentally.
1.2.2 Experimental Evaluation of MMPC Computation
Load
Multiplexed MPC, by distributing the control moves over a complete updating
cycle, reduces computational load otherwise incurred by Standard MPC. We pro-
vide one of the first experimental verification of the computational load reduction
property of Multiplexed MPC. This is especially so when N
u
is large and when
constraints are present.
It is shown that MMPC has computational advantage over the Standard
MPC, for large horizon and when constraints are present. Thus, the MMPC
algorithm can be applied to multi-zone bake-plate system and its property of
reduced online computational time has the potential to make MPC scalable to
more sophisticated (more zones) bake-plate system.
8
1.2.3 Derivation and Experimental Verification of MMPC
ISE formula for PEB process
Temperature non-uniformity will affect critical dimension of the wafer. MMPC
has the comparable response with that of standard MPC when disturbance takes
place. However, it should be noted that there are many factors affecting closed-
loop performance, such as sampling rate, controller tuning, etc.
Therefore, it is worthwhile to develop a formula for computing the Integral-
Square-Error (ISE) of MMPC for PEB process. The formula will be useful in
evaluating the effect of MMPC tuning parameters and its updating patterns,
which will finally affect the CD uniformity.
Multiplexed MPC with different sampling intervals have been demonstrated

experimentally on a multi-zone bake-plate application. Shorter sampling time can
result in faster recovery of bake plate temperature when a cold wafer is placed
on the bake plate. This result is important for the MMPC design. Experimental
results and theoretical results were matched and hence before hardware imple-
mentation, design can be performed with the aid of theory. The ISE formula
enables one to select a suitable sampling interval, or other design choices for the
MMPC, such as MPC control horizon N
u
, MPC controller tuning parameters Q,
R.
9
1.3 Organization
This thesis consists of 5 chapters and is organized as follows. Chapter 2 describes a
real-time temperature control method for warped wafers during PEB to improve
CD uniformity. The implementation will be discussed in detail for a double-
zone bake plate. Chapter 3 presents a revision of the MMPC and exp erimental
evaluation of MMPC computational load carried out on a multi-zone thermal
system. The derivation and Verification of MMPC ISE formula for PEB process
are presented in Chapter 4. Chapter 5 summarizes the research works and gives
recommendations for future works.
10
Chapter 2
CD and Real-Time Temperature
Control for Warped Wafers
This Chapter discusses the experimental results on Critical Dimension (CD) con-
trol via real-time temperature control for warped wafers. As opposed to run-to-
run control where information from the previous wafer or batch is used for control
of the current wafer or batch, the approach here is real-time and make use of cur-
rent information for control of the CD of the current wafer. In this Chapter it
is demonstrated that real-time control of the post-exposure bake temperature to

give nonuniform temperature distribution across the warped wafer can reduce CD
nonuniformity across the wafer.
11
2.1 Introduction
The key output in photolithography is the CD and CD is significantly impacted
by several variables that must also b e monitored to ensure quality [5, 36].
Thermal processing of semiconductor substrate is common and critical in
the photolithography sequence. Temperature uniformity control is an important
issue with stringent specifications and has a significant impact on the CD [37]–[39].
The most temperature sensitive step in the photolithography sequence is the post-
exposure bake step. As the photolithography industry moves to bigger substrate
and smaller CD, the stringent requirements for post-exposure bake processing still
persists [23]. For commercially available deep ultraviolet resist, a representative
post-exposure bake latitude for CD variation is 8 nm/
◦
C [11]–[12]. A number of
recent investigations also showed the importance of proper bake-plate operation
on CD control [19, 39, 40]
Thermal processing of semiconductor wafers is commonly performed by plac-
ing the substrate on a heated bake-plate for a given period of time. The heated
bake-plate is usually held at a constant temperature by a feedback controller that
adjusted the heater power in response to a temperature sensor embedded in the
bake-plate near the surface. The wafers are usually placed on proximity pins of
the order of 100 µm to create an air-gap to minimize contamination.
When a flat wafer at room temperature is placed on the bake-plate, the
12
temperature of the bake-plate drops at first but recovers gradually because of
closed-loop control as shown in Figure 2.1(a). One challenge for thermal process-
ing of wafers in photolithography is the warpage [41]. Figure 2.2(a) shows the
bake-plate temperature when a wafer warped 140µm center-to-edge was placed

on the bake-plate. By comparing Figures 2.1(a) and 2.2(a), it can be seen that
a flat and warped wafer gave rise to different magnitudes of bake-plate temper-
ature drops due to different air-gap sizes and hence different thermal resistances
between the substrates and bake-plate. Figure 2.4 shows a flat and warped wafer
on the bake-plate. Compared with the flat wafer, because the air-gap between
the warped wafer and bake-plate are bigger (smaller), the maximum temperature
drop at the bake-plate are smaller (bigger). Furthermore, we expect the warped
wafer to be heated to a lower (higher) temperature than the flat wafer. Finally,
because of nonuniform processing condition, CD across the warped wafer is not
expected to be uniform.
It was demonstrated in [42]–[43] that the air-gap size can be estimated from
the maximum drop in bake-plate temperature through their inverse relationship.
It was further demonstrated in [43] that using the heat transfer model of the
baking system and the estimated air-gap, we can calculate the bake-plate tem-
perature to give uniform temperatures across the warped wafer. In this chapter we
extend the results by demonstrating that real-time control of the post-exposure
bake temperature to give nonuniform temperature distribution across the warped
13
0 20 40 60 80 100
126
128
130
132
(a)
Bake−plate Temp (Deg C)
0 20 40 60 80 100
0.5
1
1.5
2

2.5
(b)
Control Signal (V)
Time (s)
Figure 2.1: Baking of Flat Wafer 1. Solid-line: center, Dashed-line: edge