Temperature sensing and control in multi zone semiconductor thermal processing

TEMPERATURE SENSING AND CONTROL IN
MULTI-ZONE SEMICONDUCTOR THERMAL PROCESSING





YAN HAN
(B.Eng., SJTU)





A THESIS SUBMITTED
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND
COMPUTER ENGINEERING
NATIONAL UNIVERSITY OF SINGAPORE
2009
i
Acknowledgements
My deepest gratitude is to my advisor, Professor Ho Weng Khuen, for his patience
and support throughout my study and research at the National University of Singa-
pore. I have benefited enormously from the constructive advice and critiques that he
offered over many of our discussions. I must also extend my gratitude to Professor
Ling Keck Voon and Professor Jos´e Romagnoli for the help they rendered to my
research.
I would also like to thank my friends and colleagues: Dr. Hu Ni, Dr. Wu

Xiaodong, Dr. Fu Jun, Dr. Ye Zhen, Dr. Chen Ming, Ms. Wang Yuheng, Mr. Feng
Yong, Mr. Shao Lichun, Ms. Lim Li Hong, Mr. Nie Maowen, Mr. Chua Teck Wee,
Mr. Ngo Yit Sung, Mr Lee See Chek, Ms. Teh Siew Hong, Mr. Lin Feng, Mr. Tan
Kiat An, Mr. Gibson Lee, and many others at the Advanced Control Technology
Laboratory (ACT), the Mechatronics & Automation Laboratory and the Control
& Simulation Laboratory. I have enjoyed entertaining and inspiring conversations
with them and I am thankful for the congenial and conducive working environment
to which we have all contributed.
ii
Finally, my heartfelt thanks to my family for their unfailing support and under-
standing. They give me purpose, without which I would be a lesser person.
iii
Contents
Acknowledgements i
Table of Contents iii
Summary viii
List of Tables xi
List of Figures xiii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 RTD Bias Estimation . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2 Control of the Multi-Zone Bake-Plate . . . . . . . . . . . . . . 6
iv
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.1 RTD Bias Estimation in Multi-Zone Semiconductor Thermal
Processing and Estimator Performance Analysis . . . . . . . . 8
1.2.2 Multiplexed MPC for Multi-Zone Semiconductor Thermal Pro-
cessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 RTD Bias Estimation for Multi-Zone Semiconductor Thermal Pro-

cessing 13
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Bake-Plate Thermal Modeling . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Bias Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Least Squares Estimation . . . . . . . . . . . . . . . . . . . . 21
2.3.2 GT-based Estimation . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 Analysis of Estimator Performance . . . . . . . . . . . . . . . . . . . 25
2.4.1 Influence Function (IF) . . . . . . . . . . . . . . . . . . . . . . 26
2.4.2 IF of LS Estimator . . . . . . . . . . . . . . . . . . . . . . . . 29
v
2.4.3 IF of IQR+LS Estimator . . . . . . . . . . . . . . . . . . . . . 29
2.4.4 IF of GT-based Estimator . . . . . . . . . . . . . . . . . . . . 31
2.4.5 Estimation Variance . . . . . . . . . . . . . . . . . . . . . . . 32
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Appendix 2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Appendix 2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix 2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix 2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3 Simulation and Experimental Results 43
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 A Simulation Example . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.1 Problem Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3 Experimental Verification of Theoretical Results . . . . . . . . . . . . 52
vi
3.3.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.3 Sample Calculation . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Appendix 3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4 Multiplexed MPC for Multi-Zone Semiconductor Thermal Process-
ing 75
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2 Bake-Plate Thermal Modeling . . . . . . . . . . . . . . . . . . . . . . 81
4.3 A Review of Multiplexed MPC and Feedforward Control . . . . . . . 83
4.3.1 Multiplexed MPC . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.2 Feedforward Control . . . . . . . . . . . . . . . . . . . . . . . 84
4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . 85
vii
4.4.2 Parameter Estimation . . . . . . . . . . . . . . . . . . . . . . 85
4.4.3 Experimental Runs . . . . . . . . . . . . . . . . . . . . . . . . 87
4.4.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Appendix 4A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5 Conclusion 97
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Bibliography 102
Author’s Publications 109
viii
Summary
The importance of lithography to semiconductor manufacturing is evident. Lithog-
raphy constitutes about 30% of the cost of manufacturing a chip, and is the key
technological enabler for further down-scaling of device dimensions and upgrading
of chip performance. Thermal processing is an integral part of lithography. In align-
ment with the call for ever smaller critical dimension (CD) and due to the fact that
the final CD is very sensitive to thermal processing temperature, requirement is in-

creasingly stringent on temperature sensing and control in multi-zone semiconductor
thermal processing.
Resistance Temperature Detectors (RTD’s) installed in a multi-zone bake-plate
typically used for semiconductor thermal processing are subject to measurement
bias. Data reconciliation (DR) techniques are extended so that RTD biases can
be estimated online from process data. To handle frequently encountered non-
normality in process data, a generalized T distribution (GT) based bias estimator
is proposed. Equations are derived which relate variance of a bias estimator to
sample size (number of wafers runs per estimation). These equations enable the
ix
computation of the sample size or the number of wafers needed by the bias estimator
to achieve specified variance. With this information, the exact number of wafers
can be used for estimation so that bias can be estimated precisely and eliminated
as soon as possible to avoid wafer wastage. Alternatively, these equations allow the
calculation of the variance of the bias estimator and hence its precision if the number
of wafers used is given.
The theoretical results on estimator analysis are verified experimentally. In
the light of the equations derived, an efficient estimator can be selected. In the
presence of outliers that are close to the good data, the equations show that using
GT, instead of normal distribution, to characterize process data gives rise to a more
efficient estimator than Least Squares (LS) and Interquartile test plus Least Squares
(IQR+LS) and therefore enables earlier remedial actions against RTD bias to save
semiconductor wafers from sensing-related processing defects. In view of the cost of
manufacturing one wafer, a guided choice of an efficient RTD bias estimator and an
appropriate sample size for estimation is economically important.
To fulfil the stringent requirement on temperature control of a multi-zone bake-
plate, Multiplexed Model Predictive Control (MMPC) with feedforward is demon-
strated experimentally on a multi-zone bake-plate application. By distributing the
control moves over one complete update cycle, MMPC can afford to work with higher
sampling rate. It is shown to have the potential to make the bake-plate respond

and recover faster than under conventional MPC when disturbance is induced by
x
placement of a wafer and cannot be sufficiently compensated by feedforward.
The proposed GT-based bias estimator and the MMPC controller can easily
work in the same process to minimize processing defects due to RTD bias, and to
improve spatial temperature uniformity across the bake-plate as well as run-to-run
temperature repeatability.
xi
List of Tables
1.1 CD sensitivities for some commercially available KrF resists. . . . . . 2
3.1 Theoretical and experimental results of 5000 wafer runs divided into
50 per batch and bias estimation was performed batch by batch. . . . 57
3.2 Theoretical and experimental results with randomly selected 25% of
the measurements amplified by 3 times. . . . . . . . . . . . . . . . . 58
3.3 Theoretical and Experimental Results with randomly selected 10% of
the measurements amplified by 10 times. . . . . . . . . . . . . . . . 59
3.4 Theoretical and Experimental Results with randomly selected 25% of
the measurements amplified by 2 times. . . . . . . . . . . . . . . . . 66
3.5 Theoretical and Experimental Results with randomly selected 25% of
the measurements amplified by 6 times. . . . . . . . . . . . . . . . . 67
3.6 Simulation data for the illustrative example in Section 3.2. . . . . . . 71
xii
4.1 Comparison of SMPC’s and MMPC’s measurement and computation
instants. ×
1
denotes solving a 15-variable Quadratic Program (QP).
×
2
denotes solving a 5-variable QP. . . . . . . . . . . . . . . . . . . . 89
xiii

List of Figures
2.1 A schema of an N−zone bake-plate: side view and slant view. The
bake-plate has radially distributed zones. Each zone contains inside
itself an RTD for temperature sensing and an individual resistive
heater for temperature control. . . . . . . . . . . . . . . . . . . . . . 18
2.2 An electric network analog of the bake-plate system. Analogy exists
between voltage and temperature above ambient, current and heater
power, capacitor and thermal capacitance, resistor and thermal resis-
tance, ground and ambient temperature. . . . . . . . . . . . . . . . . 19
2.3 Some special cases of GT. Distributional parameters for these special
cases are: σ =
√
2, p = 2, q → +∞ for normal, σ =
√
2, p = 2, q = 2.4
for t, σ =
√
2, p, q → +∞ for uniform, and σ =
√
2, p = 1, q → +∞
for Laplace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
xiv
3.1 GT distribution versus normal distribution in characterizing a non-
normal distribution. GT’s distributional parameters are σ =
√
2, p =
20, q = 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2 The bake-plate used in the experiment. . . . . . . . . . . . . . . . . . 53
3.3 Raw data from one run (baking process of one wafer). . . . . . . . . . 56
3.4 GT distribution versus normal distribution in characterizing a non-

normal distribution. GT’s distributional parameters are σ = 1.57 ×
10
−2
, p = 2, q = 2.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5 Influence function of various estimators. GT’s distributional param-
eters are σ = 1.57 × 10
−2
, p = 2, q = 2.4. . . . . . . . . . . . . . . . . 69
4.1 Closed-loop temperature responses under MMPC and SMPC when a
flat wafer was placed on the bake-plate. . . . . . . . . . . . . . . . . . 77
4.2 Closed-loop temperature responses under MMPC and SMPC, with
feedforward, when a flat wafer was placed on the bake-plate. . . . . . 78
4.3 Schematics of (a) a flat wafer and (b) a warp ed wafer on the bake-plate. 79
4.4 Patterns of input moves for Standard MPC (left), and for the Multi-
plexed MPC (right). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
xv
4.5 Model verification using step resp onse. From left to right, step input
applied to zone 1, zone 2, and zone 3. . . . . . . . . . . . . . . . . . . 86
4.6 Closed-loop temperature responses under MMPC and SMPC, with
feedforward, in response to a warped wafer. . . . . . . . . . . . . . . 92
4.7 Magnified view of Figure 4.6 from t = 73s to t = 77s. ‘×’s denote
measurement instants for MMPC while ‘◦’s denote measurement in-
stants for SMPC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
1
Chapter 1
Introduction
1.1 Motivation
The importance of lithography in the fabrication of integrated circuits (IC) is two-
fold. First, because of the numerous lithography steps involved in IC manufactur-
ing, lithography accounts for around 30% of the cost of manufacturing a chip [1].

Any drop in the lithographic pro cess throughput amounts to a drop in the overall
throughput for the entire fabrication factory. Second, lithography tends to be the
technical bottleneck for further progress in reducing device size and improving chip
performance, and historically, advances in lithography have framed advances in IC
cost and performance [2].
The Critical Dimension (CD), or the size of the smallest feature printed in resist
2
Table 1.1: CD sensitivities for some commercially available KrF resists.
Resist CD sensitivity (nm/ C)
Apex E 16.0
UVIIHS 7.5
UV6 2.6
TM-461 2.6
DP-024 1.8
ARCH 2 ≈ 0
with adequate control, is the proxy for the accuracy of circuit patterns formed over
the lithography process. The shrinking of CD is the technological driver of Moore’s
Law [1]. As dimensions of a transistor shrink, an increased number of transistors can
be implemented per unit area on a silicon wafer, resulting in cost advantages and
in many cases improved device reliability. For instance, both gate delay and drive
current are proportional to the inverse of the gate length which is determined by
CD. It is shown that 1nm variation in channel CD is tantamount to 1MHz variation
in chip speed [3].
The post-exposure bake (PEB) is a very critical thermal process in lithography
and the CD is typically much more sensitive to this bake than to the softbake [4]. CD
sensitivities to PEB temperature for commercially available KrF resists are shown
in Table 1.1 [5, 6]. While resist suppliers have responded to industrial requests
with resists that can be manipulated to realize smaller CD, there is increasingly de-
3
manding requirement on the accuracy of temperature control in thermal processing,

especially in PEB [7]. It has been shown that the application of an advanced thermal
processing system in PEB could contribute to a reduction in CD variance by 40%
[8]. It has also been shown that proper PEB control leads to improvement in CD
uniformity, which in turn leads to device performance improvement [9]. Specifically,
temperature uniformity across a bake-plate during both transient and steady-state
phases of PEB is critical to enhancing CD uniformity [10, 11, 12, 13, 14, 15].
Currently the most popular PEB method involves the use of a bake-plate [1].
The wafer is brought either into intimate vacuum contact with or close proximity
to a hot, high-mass metal plate. To fulfil the extremely tight CD specifications, the
bake-plate must have excellent across-plate temperature uniformity. To this end, the
bake-plate is typically designed into a multi-zone thermal system. A state-of-the-art
bake-plate with 49 independently controlled heating elements is proposed in [16, 17],
where each zone has an RTD installed within to obtain real-time measurements of
zone temperature.
A typical PEB step begins with a wafer at ambient temperature being trans-
ferred by a mechanical manipulator to the bake-plate held at a setpoint (between
70 C and 150 C and recipe specific). The wafer is removed immediately after being
baked for a pre-specified period of time.
The multi-zone configuration poses a major challenge to temperature sensing.
The fact that readings by RTD’s can be biased is a limiting factor on temperature
4
control accuracy. Bias should be estimated efficiently online to minimize the effect of
inaccurate temperature sensing. Another challenge is posed to control engineering:
a computationally tractable algorithm is required for real-time temp erature control
of a multi-zone bake-plate which is then able to reject in a timely manner the
disturbance caused by the wafer.
1.1.1 RTD Bias Estimation
Thermal processing of semiconductor wafers is common and critical in semiconductor
manufacturing [18, 19, 20]. The most temperature sensitive step in the lithography
sequence is the post-exposure bake step [4, 21]. To obtain temperature uniformity,

a wafer is heated by multiple independently controlled heating elements simultane-
ously. Each zone is equipped with an RTD for temp erature measurement. Heating
in the presence of RTD bias in such temperature sensitive cases inevitably causes
processing defects and reduces wafer yield. To maintain temperature control per-
formance, data reconciliation techniques [22, 23], which seek to find optimal state
estimates from process measurements by maximizing noise likelihood under model
constraint, can be used to perform online RTD calibration by estimating RTD biases
from process data [24].
In process engineering, assumptions commonly made such as normal (Gaussian)
statistics are approximations to reality. The occurrence of outliers, transient data
in steady-state measurements, instrument failure, human error, process nature, etc.
5
can all induce non-normal process data [25]. Indeed, whenever the central limit
theorem is invoked – the central limit theorem being a limit theorem, it can at most
suggest approximate normality for real data. Thermal processes in semiconductor
manufacturing are no exception and if the process being monitored does not vary
normally, conventional data reconciliation techniques, which rest on the normal
distribution assumption, may lead to poor results [18].
According to the central limit theorem, any random distribution can be effec-
tively transformed to the normal distribution by subgrouping and averaging. Studies
have shown that this can be accomplished effectively with subgroups of size as small
as three or four, so long as the primary distribution does not depart too significantly
from normality [26]. There are a number of circumstances that arise in semicon-
ductor manufacturing op erations in which it is inconvenient to generate subgroups
of size greater than one. As a result, it is frequently desirable to have subgroups of
size equal to one and the practice may be problematic where the processes do not
vary normally. Hence it is useful to develop methods for non-normal distribution.
Conventional data reconciliation formulations assume that process data follows
normal (Gaussian) distribution. However, even high-quality process data may not
be normal. The presence of a single huge outlier can spoil the statistical analysis

completely. Hence it is not wise to use the Least Squares (LS) algorithm, the sim-
plest data reconciliation algorithm, without any built-in check [25, 27]. A common
practice to make LS robust is to introduce a preliminary outlier test before applying
6
LS. In the presence of outliers, an outlier test is expected to remove some or all of
them. One of the most popular tests is the interquartile (IQR) test [28].
The generalized T distribution (GT) has previously been employed in econo-
metrics to model random residuals in regression parameter estimation [29]. Being
a distribution superset encompassing normal, uniform, t and Laplace distributions,
GT has the flexibility to characterize economic data with non-normal statistical
properties [30]. It would be a promising distribution model based on which an RTD
bias estimator can be constructed.
1.1.2 Control of the Multi-Zone Bake-Plate
Thermal processing of semiconductor wafers is commonly performed by placement
of the wafer on a heated plate for a pre-specified period of time. The heated plate
is of large thermal mass relative to the wafer and is held at a constant temperature
by a feedback controller that adjusts the resistive heater power in response to mea-
surements of the plate temperature. The plate is designed with multiple radial zone
configurations.
A general requirement for the multi-zone bake-plate is the ability to reject the
load disturbance induced by placement of a cold wafer on the plate. Initially the
plate temperature drops and then recovers because of closed-loop control. In man-
ufacturing, wafers are processed in quick succession, one after another. Sluggish
7
response will adversely affect, for example, the repeatability of the manufacturing
process if the recovery time of the plate temperature is longer than the baking time
of the wafer and the next wafer comes before the plate temperature fully recovers.
When this happens, there is not only wafer-to-wafer non-repeatability in tempera-
ture processing trajectory, but also plate-to-plate non-repeatability as the feedback
controller generally does not respond the same. If the processing temperature is

not critical, then this type of response is acceptable. However, with processes such
as PEB for chemically amplified photoresist processing, temperature control is very
critical [31, 32].
If a wafer is perfectly flat and the time at which the wafer arrives is known in
advance, a standard feedforward controller can be designed to eliminate the tem-
perature disturbance. In practice, however, wafer conditions differ. For example, a
wafer can warp up to 100µm [33]. In this case, feedforward control will not be able
to eliminate the temperature disturbance completely and feedback control will still
be necessary.
Work on bake-plate temperature control can be found in [34, 35, 36]. In [35],
PI was used as the feedback controller, while the more sophisticated MPC and
LQG controllers were used in [34] and [36] respectively. MPC operates by solving
a constrained optimization problem online, in real-time, in order to decide how to
update the control inputs (manipulated variables) at the next update instant. This
results in demanding online computational load and can be a limiting factor when
8
MPC is applied to complex systems with many inputs or implemented on embedded
systems where computational resources are limited.
In a recent work, a variant of MPC called Multiplexed MPC, or MMPC was
proposed and stability results for MMPC were also established [37, 38]. MMPC
distributes the update of control inputs over one complete cycle to the effect that
optimization is with respect to only one control input at a time. The motivation
for MMPC is to reduce real-time computational load when MPC is implemented on
a multivariable system. In multi-zone semiconductor thermal processing, MMPC
has the potential to bring about better temperature control performance, than con-
ventional MPC, by affording faster sampling with its much reduced computational
load.
1.2 Contributions
1.2.1 RTD Bias Estimation in Multi-Zone Semiconductor
Thermal Processing and Estimator Performance Anal-

ysis
As has been discussed in Section 1.1.1, an array of RTD’s are installed in the multi-
zone bake-plate for semiconductor thermal processing. GT-based data reconciliation
9
for the state vector has been examined in a simulation study [25] and we extend the
technique to RTD bias estimation.
We derive equations relating variance of the bias estimator to sample size (num-
ber of wafers runs per estimation). These equations enable us to compute the sample
size or the number of wafers needed by the bias estimator to achieve specified vari-
ance. With this information, the precise number of wafers can be used and wastage
can be prevented. Alternatively, these equations allow us to calculate the variance
of the bias estimator and hence its precision if the number of wafers used is given.
Such information can be used to select appropriate bias estimators depending on
applications.
We examine specifically the performance of the simple least squares (LS), in-
terquartile range test plus least squares (IQR+LS) and the generalized T distribution
(GT) based bias estimator for the difficult problem where measurement outliers are
close to good data such that they cannot be separated easily. The theory is verified
experimentally on a multi-zone bake-plate for semiconductor thermal processing.
In the light of the equations derived, an efficient estimator can be selected. In
the presence of outliers that are close to the good data, the equations show that
using GT, instead of normal distribution, to characterize process data gives rise to a
more efficient estimator than the LS and the IQR+LS and therefore enables earlier
remedial actions against RTD bias to save semiconductor wafers from sensing-related
processing defects.