tài liệu lập trình PLC S7 300
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S7-300 Instruction List
CPU 312 IFM, 314 IFM,
313, 314, 315, 315-2 DP, 316-2 DP,
318-2
6ES7 398-8AA03-8BN0
Edition 1
Contents
Contents
Contents
Address Identifiers and Parameter Ranges . . . . . . . . .
2
Abbreviations and Mnemonics . . . . . . . . . . . . . . . . . . .
12
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Examples of Addressing . . . . . . . . . . . . . . . . . . . . . . . .
16
Execution Times with Indirect Addressing . . . . . . . . .
20
List of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . .
Bit Logic Instructions with Parenthetical
Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORing of AND Operations . . . . . . . . . . . . . . . . . . .
Logic Instructions with Timers and Counters . . . . .
Word Logic Instructions with the Contents of
Accumulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
Evaluating Conditions Using AND, OR and
EXCLUSIVE OR . . . . . . . . . . . . . . . . . . . . . . . .
Edge-Triggered Instructions . . . . . . . . . . . . . . . . . .
Setting/Resetting Bit Addresses . . . . . . . . . . . . . . . .
Instructions Directly Affecting the RLO . . . . . . . . .
Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . .
Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Instructions for Timers and Counters . . . . . . .
Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . .
Load and Transfer Instructions for Address
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load and Transfer Instructions for the Status Word
Load Instructions for DB Number and DB Length .
Integer Math (16 Bits) . . . . . . . . . . . . . . . . . . . . . . .
Integer Math (32 Bits) . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Math (32 Bits) . . . . . . . . . . . . . . . . .
Square Root and Square Instructions (32 Bits) . . . .
Logarithmic Function (32 Bits) . . . . . . . . . . . . . . . .
Trigonometrical Functions (32 Bits) . . . . . . . . . . . .
Adding Constants . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Using Address Registers . . . . . . . . . . . . . . .
28
28
0
36
38
40
44
46
60
64
70
72
76
78
88
90
Comparison Instructions with Integers (16 Bits) . . .
Comparison Instructions with Integers (32 Bits) . . .
Comparison Instructions with Real Numbers
(32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator Transfer Instructions, Incrementing
and Decrementing . . . . . . . . . . . . . . . . . . . . . . . .
Program Display and Null Operation Instructions . .
Data Type Conversion Instructions . . . . . . . . . . . . .
Forming the Ones and Twos Complements . . . . . . .
Block Call Instructions . . . . . . . . . . . . . . . . . . . . . .
Block End Instructions . . . . . . . . . . . . . . . . . . . . . . .
Exchanging Shared Data Block and Instance Data
Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instructions for the Master Control Relay (MCR) . .
122
124
Alphabetical Index of Instructions . . . . . . . . . . . . . . . .
162
126
128
132
134
136
138
142
144
148
150
152
160
Convention:
In the following, the CPU 312 IFM is called CPU 312*.
In the following, the CPU 314 IFM is called CPU 314*.
In the following, the CPU 315-2 DP is called CPU 315-2.
In the following, the CPU 316-2 DP is called CPU 316-2.
98
102
104
106
108
110
112
114
116
118
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Addresses Identifiers and Parameter Ranges
Addresses Identifiers and Parameter Ranges
Address Identifiers and Parameter
Ranges
Addr.
ID
Q
QB
Q
QW
Q
QD
Q
Parameter Ranges
312*
313
314
314*
315/315–2/
316–2
318-2
Description
D
i ti
0.0 to 2047.71 Output bit (in PIQ)
0.0 to 31.7
0.0 to 127.7
0.0 to 123.7
0.0 to 127.7
124.7 to
127.7
–
124.0 to
127.7
–
–
... integrated outputs
0 to 31
0 to 127
0 to 123
0 to 127
0 to 20471
Output byte (in PIQ)
124 to 127
–
124 to 127
–
–
... integrated outputs
20461
Output word in (PIQ)
... integrated outputs
0 to 30
0 to 126
0 to 122
0 to 126
0 to
124 to 126
–
124 to 126
–
–
0 to 28
0 to 124
0 to 120
0 to 124
0 to 20441
124
–
124
–
–
... integrated outputs
Output double word (in PIQ)
B
–
–
–
Byte with general registerindirect addressing
W
–
–
–
Word with general registerindirect addressing
D
–
–
–
Double word with general
register-indirect addressing
0.0 to 8191.7
0.0 to 8191.7
0.0 to
65533.7
Data bit in data block
DBX
DB
1 to 63
1 to 127
1 to 127
0 to 2047
Data block
DBB
0 to 6143
0 to 8191
0 to 8191
0 to 65533
Data byte in DB
DBW
0 to 6142
0 to 8190
0 to 8190
0 to 65532
Data word in DB
DBD
0 to 6140
0 to 8188
0 to 8188
0 to 65530
Data double word in DB
1
2
PIQ is preset to 256 byte
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Addresses Identifiers and Parameter Ranges
Addr.
ID
Parameter Ranges
312*
DIX
DI
Addresses Identifiers and Parameter Ranges
313
314
314*
0.0 to 8191.7
Description
315/315-2/
316-2
318-2
0.0 to
8191.7
0.0 to
65533.7
Data bit in instance DB
1 to 63
1 to 127
1 to 127
1 to 2047
Instance data block
DIB
0 to 6143
0 to 8191
0 to 8191
0 to 65533
Data byte in instance DB
DIW
0 to 6142
0 to 8190
0 to 8190
0 to 65532
Data word in instance DB
DID
0 to 6140
0 to 8188
0 to 8188
0 to 65530
Data double word in instance DB
I
0.0 to 31.7
0.0 to 127.7
0.0 to 123.7
0.0 to 127.7
0.0 to
2047.7 1
124.0 to
127.7
–
124.0 to
127.7
–
–
... integrated inputs
0 to 31
0 to 127
0 to 123
0 to 127
0 to 2047 1
Input byte (in PII)
124 to 127
–
124 to 127
–
–
... integrated inputs
0 to 30
0 to 127
0 to 122
0 to 126
0 to 2046 1
Input word (in PII)
124 to 126
–
124 to 126
–
–
... integrated inputs
0 to 28
0 to 124
0 to 120
0 to 124
0 to 2044 1
124
–
124
–
–
0.0 to 255.7
0.0 to 255.7
0.0 to
8191.7 2
LB
0 to 255
0 to 255
0 to 8191 2
Local data byte
LW
0 to 254
0 to 254
0 to 8190 2
Local data word
LD
0 to 252
0 to 252
0 to 8188 2
Local data double word
IB
IW
ID
L
1
2
4
Input bit (in PII)
Input double word (in PII)
... integrated inputs
Local data bit
PII is preset to 256 byte
Local data area is preset to 4096 byte
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Addresses Identifiers and Parameter Ranges
Addr.
ID
M
Addresses Identifiers and Parameter Ranges
Parameter Ranges
312*
313
314
314*
315/315-2/
316-2
318-2
Description
0.0 to 127.7
0.0 to 255.7
0.0 to 255.7
0.0 to
1023.0
MB
0 to 127
0 to 255
0 to 255
0 to 1023
Bit memory byte
MW
0 to 126
0 to 254
0 to 254
0 to 1022
Bit memory word
MD
0 to 124
0 to 252
0 to 252
0 to 1020
Bit memory double word
6
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Bit memory bit
7
Addresses Identifiers and Parameter Ranges
Addresses Identifiers and Parameter Ranges
Parameter Ranges
Addr. ID
PQB
Q
318–2
313
314
314*
315
315-2/
316–2
0 to 31
0 to 31
0 to 767
0 to 751
0 to 767
0 to 1023
0 to 8191
Peripheral
p
output
p byte
y
(direct I/O access)
0 to 766
0 to 750
0 to 766
0 to 1022
0 to 8190
Peripheral output
word (direct I/O access)
0 to 764
0 to 748
0 to 764
0 to 1020
0 to 8188
Peripheral output
double word (direct
I/O access)
0 to 767
0 to 751
0 to 767
0 to 1023
0 to 8191
Peripheral
p
input
p byte
y
(direct I/O access)
0 to 766
0 to 750
0 to 766
0 to 1022
0 to 8190
Peripheral
p
input
p word
(direct I/O access)
0 to 764
0 to 748
0 to 764
0 to 1020
0 to 8188
Peripheral input
double word
(direct I/O access)
0 to 127
0 to 511
Timer
0 to 63
0 to 511
Counter
124
PQW
PQD
PIB
256 to 383
256 to 383
0 to 30
0 to 30
256 to 382
256 to 382
0 to 28
0 to 28
256 to 380
256 to 380
0 to 31
0 to 31
124 to 125
PIW
256 to 383
256 to 383
0 to 30
0 to 30
124
PID
Description
312*
256 to 382
256 to 382
0 to 28
0 to 28
256 to 380
256 to 380
T
0 to 63
Z
0 to 31
0 to 127
0 to 35
0 to 63
Parameter
–
–
Instruction addressed
via parameter
B#16#
W#16#
DW#16#
–
–
Byte
Word
Double word
hexadecimal
8
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Addresses Identifiers and Parameter Ranges
Addr.
ID
Addresses Identifiers and Parameter Ranges
Parameter Ranges
312*
313
314
314*
315/315–2,
316
318-2
Description
D#
–
–
IEC data constant
L#
–
–
32-bit integer constant
P#
–
–
Pointer constant
S5T#
–
–
S5 time constant (16 bits) 1
2
Time constant (16/32 bits)
T#
2
–
TOD#
–
–
IEC time constant
C#
–
–
Counter constant (BCD–codiert)
2#
–
–
Binary constant
B
(b1,b2)
B
(b1,b2,
b3,b4)
–
–
Constant, 2 or 4 Byte
1
2
10
for loading of S5 timers
T#1D_5H_3M_1S_2MS
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Abbreviations and Mnemonics
Abbreviations and Mnemonics
Abbreviations and Mnemonics
The following abbreviations and mnemonics are used in the
Instruction List:
Abbreviations
Description
Example
Abbreviations
Description
Example
k8
8-bit constant
32
f
Timer–/Zähler–Nr.
5
k16
16-bit constant
62 531
g
Operandenbereich
k32
32-bit constant
127 624
IB, QB, PIB, MB, LB,
DBB, DIB
i8
8-bit integer
–155
h
Operandenbereich
IW, QW, PIW, MW, LW,
DBW, DIW
i16
16-bit integer
+6523
i
Operandenbereich
i32
32-bit integer
–2 222 222
ID, QD, PID, MD, LD,
DBD, DID
m
P#x.y (pointer)
P#240.3
r
Baustein–Nr.
10
n
Binary constant
1001 1100
p
Hexadecimal constant
EA12
q
Real number (32-bit
floating-point number)
12.34567E+5
LABEL
Symbolic jump address
(max. 4 characters)
DEST
a
Byteadresse
2
b
Bitadresse
x.1
c
Operandenbereich
I, Q, M, L, DBX, DIX
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Registers
Registers
Registers
S Area-internal address
ACCU1 and ACCU2 (32 Bits)
The accumulators are registers for processing bytes, words or
double words. The operands are loaded into the accumulators,
where they are logically gated. The result of the logic operation
(RLO) is in ACCU1.
00000000 00000bbb bbbbbbbb bbbbbxxx
S Area-crossing address
10000yyy 00000bbb bbbbbbbb bbbbbxxx
Legend:
CPU 318–2: also ACCU3 and ACCU4.
Accumulator designations:
b Byte address
x Bit number
y Area identifier
(see section “Examples of Addressing”)
Bits
ACCU
ACCUx (x = 1 to 4)
Bits 0 to 31
ACCUx-L
Bits 0 to 15
ACCUx-H
Bits 16 to 31
ACCUx-LL
Bits 0 to 7
ACCUx-LH
Bits 8 to 15
ACCUx-HL
Bits 16 to 23
ACCUx-HH
Bits 24 to 31
Status Word (16 Bits)
The status word bits are evaluated or set by the instructions.
The status word is 16 bits long.
Bit
Assignment
0
FC
1
RLO
Result of (previous) logic operation
2
STA
Status *
3
OR
Or *
Address Registers AR1 and AR2 (32 Bits)
4
OS
Stored overflow
The address registers contain the area-internal or area-crossing addresses for instructions using indirect addressing. The address registers are 32 bits long.
5
OV
Overflow
6
CC 0
Condition code
7
CC 1
Condition code
8
BR
9 ... 15
Unassigned
The area-internal and/or area-crossing addresses have the following
syntax:
Description
First check bit *
Binary result
–
* Bit cannot be evaluated in the user program with the L STW
instruction since it is not updated at program runtime.
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Examples of Addressing
Examples of Addressing
Examples of Addressing
Addressing Examples
Description
Direct Addressing
Addressing Examples
Description
Direct Addressing
L +27
Load 16-bit integer constant
“27” into ACCU1
A I 0.0
ANDing of input bit 0.0
L L#–1
Load 32-bit integer constant
“–1” into ACCU1
L IB 1
Load input byte 1 into ACCU1
L IW 0
Load input word 0 into
ACCU1
L 2#1010101010101010
Load binary constant into
ACCU1
L ID 0
Load input double word 0 into
ACCU1
L DW#16#A0F0_BCFD
Load hexadecimal constant into
ACCU1
Indirect Addressing of Timers/Counters
L ’END’
Load ASCII character into
ACCU1
SP T [LW 8]
Start timer; the timer number is
in local word 8
L T#500 ms
Load time value into ACCU1
CU C [LW 10]
Start counter; the counter number is in local data word 10
L C#100
Load count value into ACCU1
L B#(100,12)
Load 2-byte constant
L B#(100,12,50,8)
Load 4-byte constant
L P#10.0
Load area-internal pointer into
ACCU1
L P#E20.6
Load area-crossing pointer into
ACCU1
L –2.5
Load real number into ACCU1
L D#1995–01–20
Load date
L TOD#13:20:33.125
Load time of day
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S7-300 Instruction List
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Area-Internal Memory-Indirect Addressing
A I [LD 12]
Example: L P#22.2
T LD 12
A I [LD 12]
AND operation: The address of
the input is in local data double
word 12 as pointer
A I [DBD 1]
AND operation: The address of
the input is in data double
word 1 of the DB as pointer
A Q [DID 12]
AND operation: The address of
the output is in data double
word 12 of the instance DB as
pointer
A Q [MD 12]
AND operation: The address of
the output is in memory marker
double word 12 of the instance
DB as pointer
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Examples of Addressing
Examples of Addressing
Addressing Examples
Description
Addressing Examples
Area-Internal Register-Indirect Addressing
Addressing Via Parameters
A I [AR1,P#12.2]
A Parameter
AND operation: The address of
the input is calculated from the
“pointer value in AR1+
P#12.2”
Description
Addressing via parameters
Area-Crossing Register-Indirect Addressing
Examples of how to calculate the pointer
For area-crossing register-indirect addressing, bits 24 to 26 of the
address must also contain an area identifier. The address is in the
address register.
S Example for sum of bit addresses x7:
Area
identifier
P
I
Q
M
DB
DI
L
VL
Coding
(binary)
1000 0000
1000 0001
1000 0010
1000 0011
1000 0100
1000 0101
1000 0110
1000 0111
Area
hex.
80
81
82
83
84
85
86
87
Result:
I/O area
Input area
Output area
Bit memory area
Data area
Instance data area
Local data area
Predecessor local data
(access to local data of
invoking block see
page 15)
L B [AR1,P#8.0]
Load byte into ACCU1: The
address is calculated from the
“pointer value in AR1+ P#8.0”
A [AR1,P#32.3]
AND operation: The address of
the operand is calculated from
the “pointer value in AR1+
P#32.3”
18
LAR1 P#8.2
A I [AR1,P#10.2]
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Input 18.4 is addressed (by adding the byte and bit
addresses)
S Example for sum of bit addressesu7:
L MD 0
Random pointer, e.g. P#10.5
LAR1
A I [AR1,P#10.7]
Result:
Input 21.4 is addressed (by adding the byte and bit
addresses with carry)
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Execution Times with Indirect Addressing
Execution Times with Indirect Addressing
Execution Times with Indirect
Addressing
You must calculate the execution times when using indirect addressing. This chapter shows you how.
Two-Part Statement
A statement with indirectly addressed instructions consists of two
parts:
The execution time for loading the address of the instruction from
the various areas is shown in the following table. You will also find
this table on the fold-out part of the cover.
You do not have to change the page when calculating the execution
time.
Execution Time in ms
Address is in ...
312*/
313
314/
314*
315/315-2/
316-2
318–2
Bit memory area M
Word
Double word
1.7
3.5
0.7
2.3
0.8
2.1
0.2
0.3
Data block DB/DX
Word
Double word
5.2
6.7
2.8
3.9
3.0
4.1
0.2
0.3
Local data area L
Word
Double word
2.0
3.7
0.8
2.6
0.9
2.2
0.2
0.3
AR1/AR2 (area-internal)
3.0
1.9
1.7
0.0
AR1/AR2 (area-crossing)
4.9
3.9
3.2
0 .0
Parameter (word) ... for:
Timers
Counters
Block calls
4.0
2.5
2.1
0.2
Parameter (double word)
... for
Bits, bytes,
words and
double words
7.3
5.3
4.3
0.3
Part 1: Load the address of the instruction
Part 2: Execute the instruction
In other words, you must calculate the execution time of a statement with indirectly addressed instructions from these two parts.
Calculating the Execution Time
The total execution time is calculated as follows:
Time required for loading the address
+ execution time of the instruction
= Total execution time of the instruction
The execution times listed in the chapter entitled “List of Instructions” apply to the execution times of the second part of an instruction, i.e. for the actual execution of an instruction.
You must then add the time required for loading the address of the
instruction to this execution time (see Table on following page).
The pages that follow contain examples for calculating the instruction run time for the various indirectly addressed instructions.
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Execution Times with Indirect Addressing
Execution Times with Indirect Addressing
Examples of Calculations (for the CPU 314)
You will find a few examples here for calculating the execution
times for the various methods of indirect addressing. Execution
times are calculated for the CPU 314.
Step 2:
AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled
“List of Instructions”)
Typical Execution Time in ms
Direct Addressing
Calculating the Execution Times for Area-Internal
Memory-Indirect Addressing
0.2
:
Example:
A I [DBD 12]
Step 1:
Load the contents of DBD 12 (time required is listed
in the table on page 21)
Address is in ...
Execution Time in ms
Bit memory area M
Word
Double word
0.7
2.3
Data block DB/DI
Word
Double word
2.8
3.9
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Indirect Addressing
Time for
AI
2.0+
:
Total execution time:
3.9 ms
+
2.0 ms
=
5.9 ms
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Execution Times with Indirect Addressing
Execution Times with Indirect Addressing
Calculating the Execution Time for Area-Internal
Register-Indirect Addressing
Calculating the Execution Time for Area-Crossing
Memory-Indirect Addressing
Example:
A I [AR1, P#34.3]
Example:
A [AR1, P#23.1] ... with I 1.0 in AR1
Step 1:
Load the contents of AR1, and increment it by the
offset 34.3 (the time required is listed in the table on
page 21)
Step 1:
Load the contents of AR1, and increment them by
the offset 23.1 (the time required is in the table on
page 21)
Address is in ...
Execution Time in ms
Address is in ...
Execution Time in ms
:
:
:
:
AR1/AR2 (area-internal)
1.9
:
Step 2:
AR1/AR2 (area-crossing)
:
AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled
“List of Instructions”)
:
Step 2:
0.2
:
Typical Execution Time in ms
Indirect Addressing
Direct Addressing
2.0+
0.2
:
:
Time for
AI
Indirect Addressing
Time for
AI
2.0+
:
Total execution time:
3.9 ms
+
2.0 ms
=
5.9 ms
Total execution time:
1.9 ms
+
2.0 ms
=
3.9 ms
24
:
AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled
“List of Instructions”)
Typical Execution Time in ms
Direct Addressing
3.9
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
25
Execution times with Indirect Addressing
Execution times with Indirect Addressing
Execution Time for Addressing Via Parameters
Example:
A Parameter ... with I 0.5 in the block parameter list
Step 1:
Load input I 0.5 addressed via the parameter (the
time required is in the table on page 21).
Address is in ...
Execution Time in ms
:
:
:
:
Parameter (double word)
Step 2:
5.3
AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled
“List of Instructions”)
Typical Execution Time in ms
Direct Addressing
0.2
:
Indirect Addressing
Time for
AI
2.0+
:
Total execution time:
5.3 ms
+
2.0 ms
=
7.3 ms
26
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
27
List of Instructions
List of Instructions
List of Instructions
page 16), you must add the time required for loading the address of
the particular instruction to the execution times listed (see page 21).
This chapter contains the complete list of S7-300 instructions. The
descriptions have been kept as concise as possible. You will find a
detailed functional description in the various STEP 7 reference
manuals.
Please note that, in the case of indirect addressing (examples see
InIn
struction
Bit Logic Instructions
Examining the signal state of the addressed instruction and gating
the result with the RLO according to the appropriate logic function.
Typical Execution Time in ms
Length
g
Address
Identifier
A
I/Q
M
L
DBX
DIX
a.b
a.b
a.b
a.b
a.b
c[AR1,m]
c[AR2,m]
[AR1,m]
[AR2,m]
Parameter
Status word for:
in
Description
AND
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
Register–ind., area–internal (AR1)
Register–ind., area–internal (AR2)
Area-crossing via (AR1)
Area-crossing via (AR2)
Via parameter
315
315-2 318-2
316-2
312*
313
314
314*
1 2/2
1 2/2
2
2
2
0.7
1.5
2.2
5.2
5.2
0.2
0.6
0.8
2.7
2.7
0.3
0.6
0.9
2.8
2.8
2
2
2
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
312*
313
314
314*
315
315-2
316-2
318-2
0.1+
0.1+
0.1+
0.1+
0.1+
2.5+
2.7+
3.0+
4.2+
4.2+
2.0+
2.2+
2.2+
2.8+
2.8+
1.6+
1.7+
1.8+
2.5+
2.5+
0.1+
0.1+
0.1+
0.1+
0.1+
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
Yes
–
Yes
Yes
Instruction affects:
–
–
–
–
–
Yes
Yes
Yes
1
1
2
28
A
Indirect Addressing 1
Direct Addressing
Words
Plus time required for loading the address of the instruction
(see page 21)
With direct instruction addressing
Adress area 0 to 127
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
29
List of Instructions
InIn
struction
List of Instructions
Typical Execution Time in ms
Length
Address
Identifier
AN
I/Q
M
L
DBX
DIX
a.b
a.b
a.b
a.b
a.b
c[AR1,m]
c[AR2,m]
[AR1,m]
[AR2,m]
Parameter
Status word for:
Description
in
AND NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
1 2/2
1 2/2
2
2
2
Register–ind., area–internal (AR1)
Register–ind., area–internal (AR2)
Area-crossing via (AR1)
Area-crossing via (AR2)
Via parameter
0.4
0.7
0.9
3.6
312*
313
314
314*
315
315-2
316-2
318-2
312*
313
314
314*
315
315-2
316-2
318-2
1.4
1.9
2.5
5.5
5.5
0.5
0.7
0.9
3.0
3.0
0.5
0.8
1.0
3.1
3.1
0.1
0.1
0.1
0.1
0.1
2.9+
3.1+
3.4+
4.6+
4.6+
2.2+
2.4+
2.4+
2.9+
2.9+
1.9+
2.1+
2.2+
2.8+
2.8+
0.1+
0.1+
0.1+
0.1+
0.1+
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
Yes
–
Yes
Yes
Instruction affects:
–
–
–
–
–
Yes
Yes
Yes
1
1
2
30
AN
2
2
2
2
2
Indirect Addressing 1
Direct Addressing
Words
Plus time required for loading the address of the instruction
(see page 21)
With direct instruction addressing
Adress area 0 to 127
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
31
List of Instructions
InIn
struction
List of Instructions
Typical Execution Time in ms
Length
Address
Identifier
O
I/Q
M
L
DBX
DIX
a.b
a.b
a.b
a.b
a.b
Description
in
OR
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
c[AR1,m]
c[AR2,m]
[AR1,m]
[AR2,m]
Parameter
Register–ind., area–internal (AR1)
Register–ind., area–internal (AR2)
Area-crossing via (AR1)
Area-crossing via (AR2)
Via parameter
I/Q
M
L
DBX
DIX
OR NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
ON
a.b
a.b
a.b
a.b
a.b
c[AR1,m]
c[AR2,m]
[AR1,m]
[AR2,m]
Parameter
Status word for:
Register–ind., area–internal (AR1)
Register–ind., area–internal (AR2)
Area-crossing via (AR1)
Area-crossing via (AR2)
Via parameter
312*
313
314
314*
315
315-2
316-2
318-2
312*
313
314
314*
315
315-2
316-2
318-2
1 2/2
1 2/2
2
2
2
0.7
1.5
2.2
5.2
5.2
0.2
0.6
0.8
2.7
2.7
0.3
0.7
0.9
2.9
2.9
0.1
0.1
0.1
0.1
0.1
2.5+
2.7+
3.0+
4.2+
4.2+
2.0+
2.2+
2.2+
2.8+
2.8+
1.6+
1.7+
1.8+
2.5+
2.5+
0.1+
0.1+
0.1+
0.1+
0.1+
2
2
2
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
13/2
12/2
2
2
2
1.4
1.9
2.5
5.5
5.5
0.5
0.7
0.9
3.0
3.0
0.5
0.8
1.0
3.1
3.1
0.1
0.1
0.1
0.1
0.1
2.9+
3.1+
3.4+
4.6+
4.6+
2.2+
2.4+
2.4+
2.9+
2.9+
1.6+
2.0+
2.2+
2.8+
2.8+
0.1+
0.1+
0.1+
0.1+
0.1+
2
2
2
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
–
–
Yes
Yes
Instruction affects:
–
–
–
–
–
0
Yes
Yes
1
1
2
32
O, ON
Indirect Addressing 1
Direct Addressing
Words
Plus time required for loading the address of the instruction
(see page 21)
With direct instruction addressing
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
33
List of Instructions
InIn
struction
List of Instructions
Typical Execution Time in ms
Length
Address
Identifier
X
Description
in
Indirect Addressing 1
Direct Addressing
Words
312*
313
314
314*
315
315-2
316-2
318-2
312*
313
314
314*
315
315-2
316-2
318-2
EXCLUSIVE OR
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
2
2
2
2
2
0.7
1.5
2.2
5.2
5.2
0.2
0.6
0.8
2.8
2.8
0.3
0.7
0.9
2.9
2.9
0.1
0.1
0.1
0.1
0.1
2.5+
2.7+
3.0+
4.2+
4.2+
1.9+
2.1+
2.1+
2.6+
2.6+
1.6+
1.7+
1.9+
2.5+
2.5+
0.1+
0.1+
0.1+
0.1+
0.1+
c[AR1,m]
c[AR2,m]
[AR1,m]
[AR2,m]
Parameter
Register–ind., area–internal (AR1)
Register–ind., area–internal (AR2)
Area-crossing via (AR1)
Area-crossing via (AR2)
Via parameter
2
2
2
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
I/Q
M
L
DBX
DIX
EXCLUSIVE OR NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
2
2
2
2
2
1.4
1.9
2.5
5.5
5.5
0.5
0.7
0.9
3.0
3.0
0.5
0.8
1.0
3.1
3.1
0.1
0.1
0.1
0.1
0.1
2.9+
3.1+
3.4+
4.6+
4.6+
2.2+
2.4+
2.4+
2.9+
2.9+
1.9+
2.0+
2.2+
2.8+
2.8+
0.1+
0.1+
0.1+
0.1+
0.1+
Register–ind., area–internal (AR1)
Register–ind., area–internal (AR2)
Area-crossing via (AR1)
Area-crossing via (AR2)
Via parameter
2
2
2
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
I/Q
M
L
DBX
DIX
a.b
a.b
a.b
a.b
a.b
XN
a.b
a.b
a.b
a.b
a.b
c[AR1,m]
c[AR2,m]
[AR1,m]
[AR2,m]
Parameter
Status word for:
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
–
–
Yes
Yes
Instruction affects:
–
–
–
–
–
0
Yes
Yes
1
1
34
X, XN
Plus time required for loading the address of the instruction
(see page 21)
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
35
List of Instructions
List of Instructions
Bit Logic Instructions with Parenthetical
Expressions
Saving the BR, RLO and OR bits and a function identifier
(A, AN, ...) to the nesting stack. Seven nesting levels are possible
per block.
Instruction
Address
Identifier
Length
in
Words
Description
Typical Execution Time in ms
312*/313
314/314*
315/315-2
316-2
318-2
A(
AND left parenthesis
1
2.9
1.7
1.7
0.1
AN(
AND NOT left parenthesis
1
2.9
1.7
1.7
0.1
O(
OR left parenthesis
1
2.9
1.4
1.7
0.1
ON(
OR NOT left parenthesis
1
2.9
1.4
1.7
0.1
X(
EXCLUSIVE OR
left parenthesis
1
2.9
1.4
1.7
0.1
XN(
EXCLUSIVE OR NOT
left parenthesis
1
2.9
1.4
1.7
0.1
Status word for:
A(, AN(, O(, ON(, X(,
XN(
Instruction depends on:
Instruction affects:
)
Status word for:
36
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Yes
–
–
–
–
Yes
–
Yes
Yes
–
–
–
–
–
0
1
–
0
Right parenthesis, popping an
entry off the nesting stack, gating the RLO with the current
RLO in the processor
)
Instruction depends on:
Instruction affects:
BR
1
3.3
1.7
1.9
0.1
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
–
–
–
–
–
–
–
Yes
–
Yes
–
–
–
–
Yes
1
Yes
1
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
37
List of Instructions
List of Instructions
ORing of AND Operations
The ORing of AND operations is implemented according to the
rule: AND before OR.
Instruction
Address
Identifier
O
Status word for:
Length
in
Words
Description
ORing of AND operations
according to the rule:
AND before OR
312*/313
314/314*
315/315-2/
316-2
318-2
1.4
0.3
0.5
0.1
1
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
Yes
–
Yes
Yes
Instruction affects:
–
–
–
–
–
Yes
1
–
Yes
38
O
Typical Execution Time in ms
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
39
List of Instructions
List of Instructions
Logic Instructions with Timers and
Counters
Examining the signal state of the addressed timer/counter and
gating the result with the RLO according to the appropriate
logic function.
In
Instruction
Typical Execution Time in ms
Length
Address
Identifier
in
Words
Description
A
AND
Timer
Counter
T
C
Timer para. Timer/counter
Counter p. (addressed via parameter)
Status word for:
312*
313
314
314*
315
315-2
316-2
318-2
312*
313
314
314*
315
315-2
316-2
318-2
1 2/2
1 2/2
2.4
1.7
0.8
0.6
0.9
0.6
0.1
0.1
3.3+
3.0+
2.2+
1.9+
2.1+
1.8+
0.1+
0.1+
2
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
Yes
–
Yes
Yes
Instruction affects:
–
–
–
–
–
Yes
Yes
Yes
1
13/2
1 2/2
3.0
2.4
1.0
0.8
1.1
0.9
0.1
0.1
3.7+
3.3+
2.4+
2.2+
2.3+
2.1+
0.1+
0.1+
2
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
Yes
–
Yes
Yes
Instruction affects:
–
–
–
–
–
Yes
Yes
Yes
1
AN
T
C
A
Indirect Addressing 1
Direct Addressing
AND NOT
Timer
Counter
Timer para. Timer/counter
Counter p. (addressed via parameter)
Status word for:
1
2
40
AN
Plus time required for loading the address of the instruction
(see page 21)
With direct instruction addressing
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
41
List of Instructions
Instruction
O
List of Instructions
Address
Identifier
Typical Execution Time in ms
Length
g
i
in
Words
Description
Indirect Addressing 1
Direct Addressing
312*/
313
314/
314*
315
315-2
316-2
318-2
312*/
313
314/
314*
315
315-2
316-2
318-2
1 2/2
13/2
2.4
1.7
0.8
0.6
0.9
0.6
0.1
0.1
3.3+
3.0+
2.2+
1.9+
2.1+
1.8+
0.1+
0.1+
2
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
14/2
15/2
3.0
2.4
1.0
0.8
1.1
0.9
0.1
0.1
3.7+
3.3+
2.4+
2.2+
2.3+
2.1+
0.1+
0.1+
T
C
OR timer
OR counter
Timerpara.
Counter p.
OR timer/counter
(addressed via parameter)
T
C
OR NOT timer
OR NOT counter
Timerpara.
Counter p.
OR NOT timer/counter
(addressed via parameter)
2
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
T
C
EXCLUSIVE OR timer
EXCLUSIVE OR counter
2
2
2.4
1.7
0.8
0.6
0.9
0.6
0.1
0.1
3.3+
3.0+
2.2+
1.9+
2.1+
1.8+
0.1+
0.1+
Timerpara.
Counter p.
EXCLUSIVE OR timer/counter
(addressed via parameter)
2
2
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
T
C
EXCLUSIVE OR NOT timer
EXCLUSIVE OR NOT counter
2
2
3.0
2.4
1.0
1.0
1.1
0.9
0.1
0.1
3.7+
3.3+
2.4+
1.2+
2.3+
2.1+
0.1+
0.1+
Timerpara.
Counter p.
EXCLUSIVE OR NOT
timer/counter (addressed via
parameter)
2
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
–
–
Yes
Yes
Instruction affects:
–
–
–
–
–
0
Yes
Yes
1
ON
X
XN
Status word for:
1
2
42
O, ON, X, XN
Plus time required for loading the address of the instruction
(see page 21)
With direct instruction addressing
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
43
List of Instructions
List of Instructions
Word Logic Instructions with the
Contents of Accumulator 1
Gating the contents of ACCU1 and/or ACCU1-L with a word or
double word according to the appropriate function. The word or
Instruction
Address
Identifier
AW
AW
k16
OW
OW
k16
XOW
XOW
k16
AD
AD
k32
OD
OD
k32
XOD
XOD
k32
Status word for:
double word is either a constant in the instruction or in ACCU2.
The result is in ACCU1 and/or ACCU1-L.
Length
in
Words
Description
Typical Execution Time in ms
312*/313
314/314*
315/315-2/
316-2
318-2
AND ACCU2-L
1
1.7
0.5
0.6
0.1
AND 16-bit constant
2
2.3
0.7
0.9
0.1
OR ACCU2-L
1
1.7
0.5
0.6
0.1
OR 16-bit constant
2
2.3
0.7
0.9
0.1
EXCLUSIVE OR ACCU2-L
1
1.7
0.5
0.6
0.1
EXCLUSIVE OR 16-bit
constant
2
2.3
0.7
0.9
0.1
AND ACCU2
1
3.4
1.9
2.0
0.1
AND 32-bit constant
3
4.1
2.1
2.3
0.15
OR ACCU2
1
3.4
1.9
2.0
0.1
OR 32-bit constant
3
4.1
2.1
2.3
0.15
EXCLUSIVE OR ACCU2
1
3.4
1.9
2.0
0.1
EXCLUSIVE OR 32-bit
constant
3
4.1
2.1
2.3
0.15
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Instruction depends on:
–
–
–
–
–
–
–
–
–
Instruction affects:
–
Yes
0
0
–
–
–
–
–
44
AW, OW, XOW, AD,
OD, XOD
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
45
List of Instructions
List of Instructions
Evaluating Conditions Using AND, OR
and EXCLUSIVE OR
Examining the specified conditions for their signal status, and gating the result with the RLO according to the appropriate function.
Instruction
Address
Identifier
A
Typical Execution Time in ms
312*/313
314/314*
315/315-2/
316-2
318-2
AND
Result=0
(CC 1=0) and (CC 0=0)
1
1.5
0.5
0.6
0.1
>0
Result>0
(CC 1=1) and (CC 0=0)
1
2.3
0.7
0.9
0.1
<0
Result<0
(CC 1=0) and (CC 0=1)
1
2.3
0.7
0.9
0.1
<>0
Result00
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
1
1.5
0.5
0.6
0.1
<=0
Result<=0
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
1
1.5
0.5
0.6
0.1
>=0
Result>=0
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
1
1.5
0.5
0.6
0.1
==0
Status word for:
A
Instruction depends on:
Instruction affects:
46
Length
in
Words
Description
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
FC
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
–
–
–
–
–
Yes
Yes
Yes
1
S7-300 Instruction List
EWA 4NEB 710 6087-02
S7-300 Instruction List
EWA 4NEB 710 6087-02
47
