Homework 2 arbiter and test bench verilog

VLSI DESIGN AUTOMATION
Homework #2, 2-1

Test bench for Arbiter

Student: Bui Huu Nguyen
ID number: 2016310539
Submission Date: 2016/10/06
Update Date: 2016/10/12


Arbiter
ENB

ENB

ENB

ENB

BUS
[7:0]

CPU
ENB

ENB

ENB

ENB

Grant-8bits [7:0]

Arbiter

Request-8bits
Priority-24bits
RoundORpriority-1bit
Reset-1bit
Clock

Figure 1: Diagram input and output of Arbiter
Arbiter Operates:
- Arbiter is a device used in a multi-master bus system to decide which bus master
will be allowed to control the bus for each bus cycle.
- The input of arbiter inclusion: request (8bits), priority (24bits), roundORpriority
(1bit), reset (1bit), clock.
- The output of arbiter inclusion: bits of grant (8bits)


A. Write test bench
1. Selection bit roundORpriority equal 0 that has round mode.
0-1-2-3-4-5-6-7

Figure 2: Round mode
a) Single request
- Value of input “request” will be changed one bit flowing table.
00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

b) Multi request
- Value of input “request” will be changed as flowing table
11000000

11100000

00001111

11110000

11100111

2. Selection bit roundORpriority equal 1 that has priority mode.
c) Multi request with different priority
- Set input “priority” to a specific value:
Request: 7-6-5-4-3-2-1-0
Order:

5-6-7-0-1-2-3-4

 Priority: 24’b101-110-111-000-001-010-011-100
- Value of input “request” will be changed as flowing table
11100000

01110000

d) Multi request with random priority
- priority = $random();

01111000

$ramdom()


e) Multi request with random request and priority
- request = $random(); priority = $random();
Code Abiter test bench
`timescale 1ns / 100 ps
module arbiter_tb();
//integer i,j,k,p,q,r,s,t,u,v ; //index for "for" loops
//----------------------------------------------------------------// parameters
//----------------------------------------------------------------parameter NUMUNITS = 8;
parameter ADDRESSWIDTH = 3; //number of bits needed to address NUMUNITS
//----------------------------------------------------------------// input and output declarations
//----------------------------------------------------------------reg clock;
reg reset;
reg roundORpriority;

reg [NUMUNITS-1 : 0] request;
reg [ADDRESSWIDTH*NUMUNITS-1 : 0] priority;
wire [NUMUNITS-1 : 0] grant;
//arbiter x(clock, reset, roundORpriority, request, priority,grant);
initial begin
reset = 0;
clock = 0;


request = 8'b0;
roundORpriority = 1'b0; // round mode
priority = 24'h000000;
#10 reset = 1;
//roundORpriority = 2'b00;
//single request
request = 8'b00000001;
#10
request = 8'b00000010;
#10
request = 8'b00000100;
#10
request = 8'b00001000;
#10
request = 8'b00010000;
#10
request = 8'b00100000;
#10
request = 8'b01000000;
#10
request = 8'b10000000;

//multi request
#10
request = 8'b11000000;


#10
request = 8'b11100000;
#10
request = 8'b00001111;
#10
request = 8'b11110000;
#10
request = 8'b11100111;
//Priority mode
roundORpriority = 1'b1; // priority mode
priority = 24'b101110111000001010011100; // 7-6-5-4-3-2-1-0 request, 5-6-7-0-12-3-4 priority
#10
request = 8'b11100000;
#10
request = 8'b01110000;
#10
request = 8'b01111000;
#10
request = $random(); // random request
// random priority
#10
priority = $random();
#10
request = 8'b11100000;

#10
request = 8'b01110000;
#10
request = 8'b01111000;
// random priority and random request
#10
priority = $random();
#10
request = $random();
end
always #5 clock = ! clock;
arbiter
u0(.clock
(clock),.reset
(reset),.roundORpriority
(1'b0),.request(request),.priority (priority),.grant (grant));
endmodule
B. Simulation result
1. RoundORpriority = 0, round mode.
a) Single request


-request: 00000001->grant:00000001
b. Multi request

-request: 10000000  grant: 10000000 (7)
-request: 11000000  grant: 01000000 (6)
-request: 11100000  grant: 10000000 (7)
-request: 00001111  grant: 00000001 (1)

2. RoundORpriority = 0, priority mode

0-1-2-3-4-5-6-7


-request: 11100000  grant: 10000000
-request: 01110000  grant: 00010000
-request: 01111000  grant: 00010000
-request: 00100100  grant: 00000100 (random request)
3. Multi request with random priority

-priority: 24’h895e81 = 24’b100-010-010-101-111-010-000-001
-Order:

4-2-2-5-7-2-0-1

-request:

7-6-5-4-3-2-1-0


-request: 11100000  grant: 0100000
-request: 01110000  grant: 0100000
-request: 01111000  grant: 0010000
4. Multi request with random request and priority
-priority: 24’h84d609 = 24’b100-001-001-101-011-000-001-001
-Order:

4-1-1-5-3-0-1-1

-request:

7-6-5-4-3-2-1-0

-request: 01100011  grant: 0100000 or 00000001 or 00000010 or 00100000 or
01000000

Homework 2-1
1. Seeded random function with range definition.
request = $random(seed)%(32'b1<<8);
priority = $random(seed)%(32'b1<<24);
2. Check output of ‘grant’ output is ‘xxx’


task check_func;
input [NUMUNITS-1:0] request;
reg [NUMUNITS-1:0] expected_grant;
integer j,k,m, min, index1;
integer index[7:0];
reg [ADDRESSWIDTH-1:0] prio[7:0];
reg [ADDRESSWIDTH-1:0] tmp_prio;
begin
#1;
k=0;
for(j=NUMUNITS-1; j>=0; j=j-1) begin
if (old_request[j]) begin
for(m=0;mtmp_prio[m]=old_priority[j*ADDRESSWIDTH + m];
prio[k] = tmp_prio;
index[k] = j;

k=k+1;
end
end
min =NUMUNITS-1;
for(j=0; j// $display("request=%8b, index=%0d, priority=%0d", old_request, index[j],
prio[j]);
if(min >= prio[j]) begin
min = prio[j];
index1=index[j];
end
end
// $display("request=%8b, index_max=%0d", old_request, index1);
expected_grant=old_request==0 ? 8'h00 : 8'h01 << index1;
if(grant==expected_grant)
$display("-----@%4d Request = %8b, Real_Grant = %8b, Expected_Grant = %8b =>
CORRECTLY", $time, old_request,
grant, expected_grant);
else


$display("-----@%4d Request = %8b, Real_Grant = %8b, Expected_Grant = %8b =>
INCORRECTLY", $time, old_request,
grant, expected_grant);
old_request = request;
old_priority = priority;
end
endtask
///Update code Arbiter 10/12/2016
`timescale 1ns / 100 ps

module arbiter_tb();
//integer i,j,k,p,q,r,s,t,u,v ; //index for "for" loops
integer seed;
//----------------------------------------------------------------// parameters
//----------------------------------------------------------------parameter NUMUNITS = 8;
parameter ADDRESSWIDTH = 3; //number of bits needed to address NUMUNITS
//----------------------------------------------------------------// input and output declarations
//----------------------------------------------------------------reg clock;
reg reset;
reg roundORpriority;
reg [NUMUNITS-1 : 0] request;
reg [ADDRESSWIDTH*NUMUNITS-1 : 0] priority;
wire [NUMUNITS-1 : 0] grant;
reg [NUMUNITS-1 : 0] old_request;
reg [ADDRESSWIDTH*NUMUNITS-1 : 0] old_priority;
//arbiter x(clock, reset, roundORpriority, request, priority,grant);
initial begin
reset = 0;
clock = 0;
request = 8'b0;
roundORpriority = 1'b0; // round mode


priority = 24'h000000;
#6 reset = 1;
//roundORpriority = 1'b0;
//single request
request = 8'b00000001;
check_func(request);
#10

request = 8'b00000010;
check_func(request);
#10
request = 8'b00000100;
check_func(request);
#10
request = 8'b00001000;
check_func(request);
#10
request = 8'b00010000;
check_func(request);
#10
request = 8'b00100000;
check_func(request);
#10
request = 8'b01000000;
check_func(request);
#10
request = 8'b10000000;
check_func(request);
//multi request
#10
request = 8'b11000000;
check_func(request);
#10
request = 8'b11100000;
check_func(request);
#10

request = 8'b00001111;
check_func(request);
#10
request = 8'b11110000;
check_func(request);
#10
request = 8'b11100111;
check_func(request);
//Priority mode
roundORpriority = 1'b1; // priority mode
priority = 24'b101110111000001010011100; // 7-6-5-4-3-2-1-0 request, 5-6-7-0-12-3-4 priority
#10
request = 8'b11100000;
check_func(request);
#10
request = 8'b01110000;
check_func(request);
#10
request = 8'b01111000;
check_func(request);
#10
request = $random(seed)%(32'b1<<8); // random request
check_func(request);
// random priority
#10
priority = $random(seed)%(32'b1<<24);
check_func(priority);
#10
request = 8'b11100000;
check_func(request);

#10
request = 8'b01110000;
check_func(request);
#10


request = 8'b01111000;
check_func(request);
// random priority and random request
#10
priority = $random(seed)%(32'b1<<24);
$display("@%4d----------PRIORITY %24b ---------", $time, priority);
check_func(request);
#10
request = $random(seed)%(32'b1<<8);
check_func(request);
end
always #5 clock = ! clock;
//--check function
task check_func;
input [NUMUNITS-1:0] request;
reg [NUMUNITS-1:0] expected_grant;
integer j,k,m, min, index1;
integer index[7:0];
reg [ADDRESSWIDTH-1:0] prio[7:0];
reg [ADDRESSWIDTH-1:0] tmp_prio;
begin
#1;
k=0;
for(j=NUMUNITS-1; j>=0; j=j-1) begin

if (old_request[j]) begin
for(m=0;mtmp_prio[m]=old_priority[j*ADDRESSWIDTH + m];
prio[k] = tmp_prio;
index[k] = j;
k=k+1;
end
end
min =NUMUNITS-1;
for(j=0; j

// $display("request=%8b, index=%0d, priority=%0d", old_request, index[j],
prio[j]);
if(min >= prio[j]) begin
min = prio[j];
index1=index[j];
end
end
// $display("request=%8b, index_max=%0d", old_request, index1);
expected_grant=old_request==0 ? 8'h00 : 8'h01 << index1;
if(grant==expected_grant)
$display("-----@%4d Request = %8b, Real_Grant = %8b, Expected_Grant = %8b =>
CORRECTLY", $time, old_request,
grant, expected_grant);
else
$display("-----@%4d Request = %8b, Real_Grant = %8b, Expected_Grant = %8b =>
INCORRECTLY", $time, old_request,
grant, expected_grant);
old_request = request;

old_priority = priority;
end
endtask
arbiter
u0(.clock
(clock),.reset
(reset),.roundORpriority
(1'b0),.request(request),.priority (priority),.grant (grant));
endmodule
Results:


3. Review “DUT” why ‘grant’ output is ‘xxx’ when the ‘rst’ is less than first up of
clock. Change “DUT” as asysnc, rst, and simulation.
Answer:
Because reset is active at ‘0’ level, if rising of reset happens after 1st positive edge
clock then system is reset, some internal signals (grantD, scan, next, nextNext)
would be zero, not unknown.


If reset is set to ‘1’ level before rising edge of 1st clock, at 1st positive edge of clock,
reset is in-active, so system is still not reset, some internal signals (grantD, scan,
next, nextNext) is unknown value, therefore, the output grant also is unknown until
reset is active again

Change synchronous reset to asynchronous reset and run simulation. In file
arbiter.v, we modify reg_code become:

And we obtain result: