The architecture of computer hardware and systems software an information technology approach ch07

CHAPTER 7:
The CPU and Memory
The Architecture of Computer Hardware
and Systems Software:
An Information Technology Approach
3rd Edition, Irv Englander
John Wiley and Sons 2003


CPU: 3 Major Components
 ALU (arithmetic logic unit)
 Performs calculations and comparisons (data changed)

 CU (control unit): performs fetch/execute cycle
 Functions:




Moves data to and from CPU registers and other hardware
components (no change in data)
Accesses program instructions and issues commands to the
ALU

 Subparts:




Memory management unit: supervises fetching instructions and
data

I/O Interface: sometimes combined with memory management
unit as Bust Interface Unit

 Registers
 Example: Program counter (PC) or instruction pointer
determines next instruction for execution
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Memory

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System Block Diagram

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Memory

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The Little Man Computer

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Memory

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Concept of Registers
 Small, permanent storage locations within the

CPU used for a particular purpose
 Manipulated directly by the Control Unit
 Wired for specific function
 Size in bits or bytes (not MB like memory)
 Can hold data, an address or an instruction
 How many registers does the LMC have?

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Memory

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Registers
 Use of Registers
 Scratchpad for currently executing program


Holds data needed quickly or frequently

 Stores information about status of CPU and currently
executing program



Address of next program instruction
Signals from external devices

 General Purpose Registers






User-visible registers
Hold intermediate results or data values, e.g., loop counters
Equivalent to LMC’s calculator
Typically several dozen in current CPUs

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Special-Purpose Registers
 Program Count Register (PC)
 Also called instruction pointer

 Instruction Register (IR)
 Stores instruction fetched from memory

 Memory Address Register (MAR)
 Memory Data Register (MDR)
 Status Registers
 Status of CPU and currently executing program
 Flags (one bit Boolean variable) to track condition
like arithmetic carry and overflow, power failure,
internal computer error
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Memory

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Register Operations
 Stores values from other locations (registers and
memory)
 Addition and subtraction
 Shift or rotate data
 Test contents for conditions such as zero or positive

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Operation of Memory
 Each memory location has a unique address
 Address from an instruction is copied to the
MAR which finds the location in memory
 CPU determines if it is a store or retrieval
 Transfer takes place between the MDR and
memory
 MDR is a two way register

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Memory

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Relationship between MAR,
MDR and Memory
Addres
s

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Memory

Data

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MAR-MDR Example

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Memory

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Visual Analogy of Memory

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Memory

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Individual Memory Cell

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Memory

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Memory Capacity
 Determined by two factors
1. Number of bits in the MAR



LMC = 100 (00 to 99)
2K where K = width of the register in bits

2. Size of the address portion of the instruction




4 bits allows 16 locations
8 bits allows 256 locations
32 bits allows 4,294,967,296 or 4 GB

 Important for performance
 Insufficient memory can cause a processor to

work at 50% below performance
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RAM: Random Access Memory
 DRAM (Dynamic RAM)
 Most common, cheap
 Volatile: must be refreshed (recharged with power)
1000’s of times each second

 SRAM (static RAM)
 Faster than DRAM and more expensive than
DRAM
 Volatile
 Frequently small amount used in cache memory
for high-speed access used
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ROM - Read Only Memory
 Non-volatile memory to hold software that is
not expected to change over the life of the
system
 Magnetic core memory

 EEPROM
 Electrically Erasable Programmable ROM
 Slower and less flexible than Flash ROM

 Flash ROM
 Faster than disks but more expensive
 Uses



BIOS: initial boot instructions and diagnostics
Digital cameras

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Fetch-Execute Cycle
 Two-cycle process because both instructions and
data are in memory
 Fetch
 Decode or find instruction, load from memory into
register and signal ALU
 Execute
 Performs operation that instruction requires
 Move/transform data

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Memory

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LMC vs. CPU
Fetch and Execute Cycle

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Memory

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Load Fetch/Execute Cycle
1. PC -> MAR

Transfer the address from the
PC to the MAR

2. MDR -> IR

Transfer the instruction to the
IR

3. IR(address) -> MAR

Address portion of the
instruction loaded in MAR

4. MDR -> A

Actual data copied into the
accumulator

5. PC + 1 -> PC

Program Counter incremented

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Store Fetch/Execute Cycle
1. PC -> MAR

Transfer the address from the
PC to the MAR

2. MDR -> IR

Transfer the instruction to the
IR

3. IR(address) -> MAR

Address portion of the
instruction loaded in MAR

4. A -> MDR*

Accumulator copies data into
MDR

5. PC + 1 -> PC

Program Counter incremented

*Notice how Step #4 differs for LOAD and STORE

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ADD Fetch/Execute Cycle
1. PC -> MAR

Transfer the address from the
PC to the MAR

2. MDR -> IR

Transfer the instruction to the
IR

3. IR(address) -> MAR

Address portion of the
instruction loaded in MAR

4. A + MDR -> A

Contents of MDR added to
contents of accumulator

5. PC + 1 -> PC

Program Counter incremented

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LMC Fetch/Execute
SUBTRACT

IN

OUT

HALT

PC  MAR

PC  MAR

PC  MAR

PC  MAR

MDR  IR

MDR  IR

MDR  IR

MDR  IR

IR[addr]  MAR

IOR  A

A  IOR

A – MDR  A

PC + 1  PC

PC + 1  PC

PC + 1  PC
BRANCH

BRANCH on Condition

PC  MAR

PC  MAR

MDR  IR

MDR  IR

IR[addr]  PC

If condition false: PC + 1  PC
If condition true: IR[addr]  PC

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Bus
 The physical connection that makes it possible
to transfer data from one location in the
computer system to another
 Group of electrical conductors for carrying
signals from one location to another
 Line: each conductor in the bus

 4 kinds of signals
1. Data (alphanumeric, numerical, instructions)

2. Addresses
3. Control signals
4. Power (sometimes)
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Bus
 Connect CPU and Memory
 I/O peripherals: on same bus as
CPU/memory or separate bus
 Physical packaging commonly called
backplane
 Also called system bus or external bus
 Example of broadcast bus
 Part of printed circuit board called motherboard
that holds CPU and related components
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Bus Characteristics
 Protocol
 Documented agreement for communication
 Specification that spells out the meaning of each
line and each signal on each line

 Throughput, i.e., data transfer rate in bits per second
 Data width in bits carried simultaneously

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