The architecture of computer hardware and systems software an information technology approach ch08

Chapter 8
CPU and Memory:
Design, Implementation, and Enhancement

The Architecture of Computer
Hardware and Systems Software:
An Information Technology Approach
3rd Edition, Irv Englander
John Wiley and Sons 
2003


CPU Architecture Overview
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CISC – Complex Instruction Set Computer
RISC – Reduced Instruction Set Computer
CISC vs. RISC Comparisons
VLIW – Very Long Instruction Word
EPIC – Explicitly Parallel Instruction
Computer

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CISC Architecture
 Examples
 Intel x86, IBM Z-Series Mainframes, older
CPU architectures

 Characteristics
 Few general purpose registers
 Many addressing modes
 Large number of specialized, complex
instructions
 Instructions are of varying sizes
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Limitations of CISC Architecture
 Complex instructions are infrequently
used by programmers and compilers
 Memory references, loads and stores,
are slow and account for a significant
fraction of all instructions
 Procedure and function calls are a
major bottleneck
 Passing arguments
 Storing and retrieving values in registers
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RISC Features
 Examples
 Power PC, Sun Sparc, Motorola 68000

 Limited and simple instruction set
 Fixed length, fixed format instruction words
 Enable pipelining, parallel fetches and executions

 Limited addressing modes
 Reduce complicated hardware

 Register-oriented instruction set
 Reduce memory accesses

 Large bank of registers
 Reduce memory accesses
 Efficient procedure calls

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CISC vs. RISC Processing

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Circular Register Buffer

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Circular Register Buffer
- After Procedure Call

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CISC vs. RISC Performance
Comparison
 RISC  Simpler instructions
 more instructions
 more memory accesses
 RISC  more bus traffic and
increased cache memory misses
 More registers would improve CISC
performance but no space available for them
 Modern CISC and RISC architectures are
becoming similar
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VLIW Architecture
 Transmeta Crusoe CPU
 128-bit instruction bundle = molecule
 4 32-bit atoms (atom = instruction)
 Parallel processing of 4 instructions

 64 general purpose registers
 Code morphing layer
 Translates instructions written for other CPUs into
molecules
 Instructions are not written directly for the Crusoe
CPU
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EPIC Architecture
 Intel Itanium CPU
 128-bit instruction bundle
 3 41-bit instructions
 5 bits to identify type of instructions in bundle

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128 64-bit general purpose registers
128 82-bit floating point registers
Intel X86 instruction set included
Programmers and compilers follow guidelines
to ensure parallel execution of instructions

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Paging
 Managed by the operating system
 Built into the hardware
 Independent of application

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Logical vs. Physical Addresses
 Logical addresses are relative locations
of data, instructions and branch target
and are separate from physical
addresses
 Logical addresses mapped to physical
addresses
 Physical addresses do not need to be
consecutive

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Logical vs. Physical Address

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Page Address Layout

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Page Translation Process

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Memory Enhancements
 Memory is slow compared to CPU processing
speeds!
 2Ghz CPU = 1 cycle in ½ of a billionth of a second

 70ns DRAM = 1 access in 70 millionth of a second

 Methods to improvement memory accesses
 Wide Path Memory Access
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Retrieve multiple bytes instead of 1 byte at a time

 Memory Interleaving
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Partition memory into subsections, each with its own
address register and data register

 Cache Memory
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Memory Interleaving

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Why Cache?
 Even the fastest hard disk has an
access time of about 10 milliseconds

 2Ghz CPU waiting 10 milliseconds
wastes 20 million clock cycles!

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Cache Memory
 Blocks: 8 or 16 bytes
 Tags: location in main memory
 Cache controller
 hardware that checks tags

 Cache Line
 Unit of transfer between storage and cache memory

 Hit Ratio: ratio of hits out of total requests
 Synchronizing cache and memory
 Write through
 Write back
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Step-by-Step Use of Cache

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Step-by-Step Use of Cache

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Performance Advantages
 Hit ratios of 90% common
 50%+ improved execution speed
 Locality of reference is why caching works
 Most memory references confined to small region of
memory at any given time
 Well-written program in small loop, procedure or
function
 Data likely in array
 Variables stored together
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Two-level Caches
 Why do the sizes of the caches have to be
different?

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Cache vs. Virtual Memory
 Cache speeds up memory access
 Virtual memory increases amount of
perceived storage
 independence from the configuration and
capacity of the memory system
 low cost per bit

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