ĐIỆN tử VIỄN THÔNG 08 signal datatypes v9 khotailieu

Signals and Data Types


Objectives
After completing this module, you will be able to:
•

Declare ports and signals by using appropriate data types

•

List possible values for each data type

•

Declare scalar and composite data types (array and record)

•

Declare one-dimensional and two-dimensional arrays

•

Declare and use VHDL subtypes

Signals and Data Types - 8 - 2

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Outline

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•
•
•
•

Signals and Data Types - 8 - 3

Overview
Scalar Types
Composite Types
2-D Arrays
Summary

© 2007 Xilinx, Inc. All Rights Reserved


Data Types
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The wide range of available data types provides flexibility in hardware modeling and builtin error checking to ensure signal compatibility in large, complex models
–

•

Data types are very important in VHDL
–
–

•

Type checking rules must be obeyed in behavioral and gate-level models

A given data type allows only values within its range to be applied
Each object (signal, variable, constant, or port) must have its type defined
when declared

VHDL is a strongly typed language
–

Connected signals must be of the same type

Signals and Data Types - 8 - 4

© 2007 Xilinx, Inc. All Rights Reserved


Signals and Ports
•

Data type and width must match on signal and port assignments
entity REG_4 is
port ( D_IN1
CNTRL
CLK, RST
Q
end entity REG_4;
signal
signal
signal

signal

: in std_logic_vector (3 downto 0);
: in std_logic_vector (1 downto 0);
: in std_logic;
: out std_logic_vector (3 downto 0));

A : integer ;
B : bit ;
C : integer ;
D : std_logic ;

Signals and Data Types - 8 - 5

A <= C;
A <= C + 1;
A <= B;
D <= C;
B <= D;
Q <= CNTRL;

© 2007 Xilinx, Inc. All Rights Reserved

GOOD
GOOD
ERROR
ERROR
ERROR
ERROR

VHDL Type Categories
•

Four categories of data types in VHDL
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Scalar
•

–

Composite
•

–

Group objects, similar or different types

Access
•

–

Single-value object, defined indexes, ordered

Defines pointers to objects
–
Covered in the Advanced VHDL course

File
•

Sequence of objects of a given type
–
Covered in the Advanced VHDL course

Signals and Data Types - 8 - 6

© 2007 Xilinx, Inc. All Rights Reserved


Outline
•
•
•
•
•

Signals and Data Types - 8 - 7

Overview
Scalar Types
Composite Types
2-D Arrays
Summary

© 2007 Xilinx, Inc. All Rights Reserved

Scalar Data Types
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Scalar data types are single values. In VHDL, this class includes
–
–
–
–
–
–
–
–

bit
boolean
std_logic and std_ulogic
integer
real
character
Physical concepts and amounts
Enumerated types for immediate recognition

Signals and Data Types - 8 - 8

© 2007 Xilinx, Inc. All Rights Reserved


bit and boolean
•

Concise for modeling hardware, but it does not model high-impedance, unknown, or don’t
care, for example

type bit is (‘0’, ‘1’) ;

•

Useful for modeling at a more abstract level

architecture BEHAVE of MUX is
signal A,B,SEL, Z : bit ;
begin
if SEL = ‘1’ then
Z <= A ;
else
Z <= B ;
end if . . .

type boolean is (false, true) ;
Signals and Data Types - 8 - 9

© 2007 Xilinx, Inc. All Rights Reserved

if Sel =‘1’,

if F >= G..

both yield boolean result

std_logic and std_ulogic
•

std_logic was developed from the Multi-Value Logic (MVL) system and provides for more
detailed hardware modeling than bit
–

–

Supports different signal strengths, don't-care conditions, and 3-state
drivers
Defined in package std_logic_1164

type std_ulogic is (

Signals and Data Types - 8 - 10

‘U’, -- Uninitialized
‘X’, -- Forcing Unknown
‘0’, -- Forcing Zero
‘1’, -- Forcing One
‘Z’, -- High Impedance
‘W’, -- Weak Unknown
‘L’, -- Weak Zero
‘H’, -- Weak One
‘ - ’ -- Don’t Care
);
© 2007 Xilinx, Inc. All Rights Reserved

Recall: type bit is

limited to (‘0’, ‘1’)


std_logic versus std_ulogic
•

Both contain the same set of possible values
–
–

The difference is in implementation
The u in ulogic means unresolved

•

If you want to drive two or more signals to a common output of type std_logic, some form
of a resolution function must be used

•

std_ulogic offers no such capability, but it does provide a built-in means of error checking
for inadvertent wire-oring

signal A,B,C,RES_OUT : std_logic ;
signal OUT_1 : std_ulogic ;

A
B
C
Signals and Data Types - 8 - 11

OUT_1 <= A ;
OUT_1 <= B ;
A
OUT_1 <= C ;

ER
RO
R

OUT_1

© 2007 Xilinx, Inc. All Rights Reserved

B
C

GO
OD

RES_OUT <= A;
RES_OUT <= B;
RES_OUT <= C;

RES_OUT


Signal Resolution
•

A given output may not have multiple wire-or drivers
–

To model a 3-state output, use a conditional signal assignment and data
type std_logic
signal A,B,C, RES_OUT : std_logic ;

RES_OUT <= A when EN0 = ‘1’ else ‘Z’ ;
RES_OUT <= B when EN1 = ‘1’ else ‘Z’ ;
RES_OUT <= C when EN2 = ‘1’ else ‘Z’ ;

EN0

A
EN1

B
EN2

C
Signals and Data Types - 8 - 12

© 2007 Xilinx, Inc. All Rights Reserved

GO
OD

RES_OUT

integer and real
•

Allows for flexible, intuitive quantities and values
–

Specifying the range of any integer is essential; otherwise, the default is a
minimum 32-bit implementation

type integer is range . . .
•

signal A : integer range 0 to 7;
signal B : integer range 15 downto 0 ;

Allows you to use floating point values
–
–

Declare reals with the intended range of real values
Real values are not synthesizable

type real is range . . .

Signals and Data Types - 8 - 13

type CAPACITY is range -25.0 to 25.0 ;
signal SIG_1 : CAPACITY := 3.0 ;

© 2007 Xilinx, Inc. All Rights Reserved

Character
•

Updated in VHDL-93 to include all items in the ISO eight-bit set
–
–

Typically, characters are used to create strings
The exact nature of strings is discussed later in this module

type character is ( nul, sol, stx, etx, eot, enq, ack, bel,
...
‘@’, ‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’, ‘G’,
.. . );

constant MY_CHAR: character := ‘Q’ ;
Signals and Data Types - 8 - 14

© 2007 Xilinx, Inc. All Rights Reserved


Physical
•

Physical types are used to quantify real-world physical concepts and amounts, such as
mass, length, time

•

A physical type must be defined in terms of its primary unit
–

Any secondary units must be multiples of the primary

type time is range 1 to 1000000
units
time is the only pre-defined physical
fs;
type in VHDL. It can be used to
ps = 1000 fs;
model cell delays and other timens = 1000 ps;
based parameters.
us = 1000 ns;
ms = 1000 us;
constant TPD : time := 3ns ;
...
...
end units ;
Z <= A after TPD ;
Signals and Data Types - 8 - 15

© 2007 Xilinx, Inc. All Rights Reserved


Enumerated
•

Offers the most flexibility in abstract hardware modeling

–

–

User-defined enumerated types use values that are immediately
recognizable and intuitively relevant to the operation of the model
Makes code more readable when describing state machines and complex
systems

type MY_STATE is ( RST, LOAD, FETCH, STOR, SHIFT ) ;

...
signal STATE, NEXT_STATE : MY_STATE ;
...
case (STATE) is
when LOAD => . . .
if COND_A and COND_B then
NEXT_STATE <= FETCH ;
else NEXT_STATE <= STOR ;
Signals and Data Types - 8 - 16

© 2007 Xilinx, Inc. All Rights Reserved


Outline
•
•
•
•
•

Signals and Data Types - 8 - 17

Overview
Scalar Types
Composite Types
2-D Arrays
Summary

© 2007 Xilinx, Inc. All Rights Reserved


Composite Data Types
•

Composite data types are groups of elements in the form of an array or record
–

•

bit_vector, std_logic_vector, and string are all pre-defined composite types

signal A_WORD : std_logic_vector (3 downto 0) := “0011” ;
This creates four elements of type bit grouped together in an array
–

–

There is no pre-defined LSB or MSB interpretation; therefore, this value is
not automatically read by the compiler as 3

Note the use of double quotes (“0011”) for any bit_vector, std_logic_vector,
or string object and the use of single quotes (‘1’) for bit, std_logic, and
character

Signals and Data Types - 8 - 18

© 2007 Xilinx, Inc. All Rights Reserved


Arrays
•

Arrays are groups of elements, all of the same type
type WORD is array (3 downto 0) of std_logic ;
signal B_BUS : WORD ;
What are the
possible
values for
each element
of the array
in each case?

3

B_BUS

2

1

index position

0

signal B_BUS : DATA ;
type DATA is array (3 downto 0) of integer range 0 to 9 ;
Signals and Data Types - 8 - 19

© 2007 Xilinx, Inc. All Rights Reserved


Array Assignments
•

When assigning one array to another

1. The arrays must be the same type
2. The arrays must be the same length
3. The assignment is positional, from left to right

–
–
–

signal BUS_A, BUS_B: std_logic_vector (3 downto 0) ;
signal BUS_C : std_logic_vector (0 to 3) ;
BUS_C <= BUS_A ;
3
2
1

0

BUS_B <= BUS_A ;
3
2
1
0

3

2

1

BUS_A

BUS_A

BUS_B

BUS_C
0

0

1

2

Inadvertent index swap?

Signals and Data Types - 8 - 20

© 2007 Xilinx, Inc. All Rights Reserved

3


Array Assignment Notation
•

To simplify array assignments—and enhance readability—you can designate a
hexadecimal or octal base
–

Underscores can also be used to further enhance readability
signal DATA_WORD : std_logic_vector (11 downto 0) ;

DATA_WORD <= X“A6F”;
DATA_WORD <= “101001101111” ;
DATA_WORD <= O“5157”;
DATA_WORD <= B“1010_0110_1111” ;
Signals and Data Types - 8 - 21

© 2007 Xilinx, Inc. All Rights Reserved


Records
type OPCODE is record
PARITY : bit;
ADDRESS : std_logic_vector ( 0 to 3 );

DATA_BYTE : std_logic_vector ( 7 downto 0 );
NUM_VALUE : integer range 0 to 6;
STOP_BITS : bit_vector (1 downto 0);
end record ;
...
signal TX_PACKET, RX_PACKET : OPCODE;

A record is a group of
elements that may be of
different types.

...
PARITY

ADDRESS

DATA_BYTE

TX _ PAC K ET
Signals and Data Types - 8 - 22

© 2007 Xilinx, Inc. All Rights Reserved

NUM_VALUE STOP_BITS


Strings
--declared within the package or architecture
constant WARNING1: string ( 1 to 27 ) := “Unexpected Outputs Detected” ;
constant WARNING2: string ( 1 to 31 ) := “ System Unstable, Aborting Now ” ;

constant WARNING3: string ( 1 to 21 ) := “ Entering FSM State2 ” ;

process ( A_SIG, B_SIG, C_SIG )
begin
if (A_SIG and B_SIG ) /= ‘1’ then
report WARNING1;
elsif ( A_SIG and C_SIG ) = ‘1’ then
report WARNING2 & “ Problem Mod2“;
end if ;
process ( A_SIG , B_SIG )
end process ;
begin

process ( A_SIG , B_SIG, C_SIG )
begin
if (A_SIG and B_SIG ) /= ‘1’ then
report “ Unexpected Outputs…” ;
elsif ( A_SIG and C_SIG ) = ‘1’ then
report “ I need a vacation “;
end if ;
end process ;

assert ( A_SIG and B_SIG ) /= ‘1’ then
report WARNING1
severity note ;
end process ;

Signals and Data Types - 8 - 23

© 2007 Xilinx, Inc. All Rights Reserved

A string is a userdefined array of
data type character


Array Aggregates
•

Aggregates are a convenient means for grouping both scalar and composite data types
for assignment
signal H_BYTE, L_BYTE: std_logic_vector ( 0 to 7);
signal Q_OUT : std_logic_vector (31 downto 0);
signal A, B, C, D : std_logic;
signal WORD : std_logic_vector (3 downto 0);

(A,B,C,D) <= WORD; Only scalar data variables are allowed on the left-side aggregates
WORD <= ( 2 => ‘1’, 3 => D, others => ‘0’ ) ;
Q_OUT <= ( others => ‘0’ ) ;
WORD <= ( A, B, C, D ) ;
H_BYTE <= ( 7|6|0|1 => ‘1’, 2 to 5 => ‘0’ ) ;
The total number of elements on both sides of any assignment must match;
“others” can be used as a default assignment, regardless of the array size
Signals and Data Types - 8 - 24

© 2007 Xilinx, Inc. All Rights Reserved


Record Aggregates
•

Aggregates are a convenient means for grouping both scalar and composite data types
for assignment
type D_WORD is record
UPPER : std_logic_vector (7 downto 0 ) ;
LOWER : std_logic_vector (7 downto 0 ) ;
end record ;
signal DATA_WORD : D_WORD ;
signal H_BYTE, L_BYTE: std_logic_vector (7 downto 0);
signal TX_PACKET, RX_PACKET : OPCODE; --defined earlier
DATA_WORD <= ( H_BYTE, L_BYTE) ;

Only records can accept aggregate of arrays

TX_PACKET <= ( ‘1’,”0011”,”11101010”,5,”10” ) ;
DATA_WORD <= ( LOWER => L_BYTE, UPPER=> H_BYTE) ;
TX_PACKET. ADDRESS <= ( “0011” ) ;
TX_PACKET. ADDRESS(2) <= ‘0’ ;
DATA_WORD <= ( LOWER | UPPER=> H_BYTE);
DATA_WORD <= ( others => H_BYTE);
Signals and Data Types - 8 - 25

© 2007 Xilinx, Inc. All Rights Reserved