ĐIỆN tử VIỄN THÔNG 12b lab4 counter v9 khotailieu

n­Bit Binary Counter and RTL 
Verification Lab

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-2


n-Bit Binary Counter and RTL Verification Lab
Introduction
In this lab, you will write a complete RTL description for the entity MY_CNTR by using generics
to specify the bit width. This is an n-bit binary, up/down loadable counter, with active low
asynchronous reset. You will then build a VHDL testbench to verify the functionality of the RTL
code as well as the hardware it models.

Objectives
After completing this lab, you will be able to:
 Create, simulate, and verify RTL code for an n-bit binary counter
 Use the language templates in the ISE™ software
 Use VHDL generics

Procedure
Examine the circuit below (Figure 12b-1). In this lab, you will write a complete RTL description
for the entity MY_CNTR by using generics to specify the bit width. The circuit is an n-bit binary,
up/down loadable counter, with active low asynchronous reset.

D_IN

Q_OUT
MY_CNTR

CE
LOAD
UpDn
CLK
RST
Figure 12b-1. Schematic for a Generic (n-bit) Wide Binary Counter
NOTE: Toolwire is the default platform for running labs. Use R:\ for all directory references.

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-3


This lab comprises two primary steps: You will declare a generic, using it to create an n-bit binary
counter and create a testbench to verify the design.
For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the procedure.
Below these general instructions, you will find accompanying step-by-step directions and
illustrated figures that provide more detail for performing the procedure. If you feel confident
about completing a procedure, you can skip the step-by-step directions and move on to the next
general instruction.
Note: When using Toolwire to perform this lab, all software programs, files and projects will be

located on the R:\ drive instead of C:\.
Note: If you are unable to complete the lab at this time, you can download the lab files for this
module from the Xilinx FTP site at
/>
Creating n-Bit Counter with Generics

Step 1

For each procedure within a primary step, there are general instructions (indicated by
the
symbol). These general instructions only provide a broad outline for
performing the procedure. Below these general instructions, you will find
accompanying step-by-step directions and illustrated figures that provide more detail
for performing the procedure. If you feel confident about completing a procedure,
you can skip the step-by-step directions and move on to the next general instruction.
General Flow for this Lab:
Step 1:
Creating an
n-Bit Counter
with Generics

Step 2:
Creating a
Testbench
and Verifying
Functionality

Open the existing My_Class_Labs project within the ISE™ software, located in
the R:\training\vhdl\labs directory.
 Select Start  Programs  Xilinx ISE 9.1i  Project Navigator to launch the Project

Navigator
By default, the ISE software should start with the last open project as the current project.
 If not, select File  Open Project  My_Class_Labs

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-4


!
!

Important: Unless otherwise noted, you must label your project and HDL source files as
instructed, or simulation may not work properly in the Toolwire environment.
 Select Project  New Source
 In the New Source dialog box, select VHDL Module and enter MY_CNTR in the File name
field
 Click Next to open the table-based entity wizard
 Use this table to enter the port data for the intended module. Refer to the counter schematic in
Figure 12b-1
Note that you cannot enter the generic at this point.
 When you are finished, click Next and click Finish
The tool automatically creates the entity declaration based on the data entered in the table.
Note: After you exit the wizard, all subsequent edits are made in the HDL editor itself,
including changes to items that were originally specified in the wizard.
Again, you cannot specify the generic by using the wizard. You will simply specify the

generic within the HDL text editor.
Also, in this particular model, you will need to reference the subprograms that allow
arithmetic operations on arrays in VHDL. The wizard in the ISE™ software includes some of
these packages by default, and they are declared at the top of the file.
 Add the IEEE.numeric_std.all package to the file, as shown below:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
These are so-called arithmetic packages and they are fully explained later in this course.
The text editor opens and the file shows the entity declaration. This data is based on what was
entered in the wizard. The label is MY_CNTR with the ports as specified.

Specify the generics.
 Declare a VHDL generic to specify the port width for the input and output data bus. Specify
the generic as an integer with a default value of 8
 Label the generic as you wish
For examples on using generics, refer to the “Language Concepts” module or the quick
reference card located near the front of this workbook.

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-5


After finishing the entity, complete the architecture shell. Recall that this is a

dependent (secondary) design unit to the entity.
To write the functional code for the binary counter, you will use a combination of
nested if/else statements that accurately describe the counter operation.
In doing so, you must determine the priority of the if/else statements, which
directly infer logic and functional priority. For example, what is the priority of the
control inputs, LOAD, RST, CE, and UPDN? Again, the nesting of if/else
statements directly controls signal precedence.
!
!

You can find an example of a similar binary counter in the language templates of the ISE™
software. Click either the Light Bulb button in the toolbar or select Edit  Language
Templates. You can copy and paste the HDL source code examples directly into the HDL
editor.
 Using the generic, declare an 8-bit wide signal within the architecture with the name COUNT
This signal will be updated and assigned within the clocked process.
 Outside the process, assign the value of the internal signal COUNT to the module’s output
port Q_OUT; that is, Q_OUT <= COUNT;
 Use the following assignment to signal COUNT under the reset condition
COUNT <= (others => ‘0’ ) ;
This allows you to initialize the signal without regard to its actual size. This is an important
measure of flexibility because you are using generics and could conceivably change the port
width.
After this is done, your source code for the counter should be complete.

Perform a syntax check.
 In the Sources for window, select MY_CNTR.vhd. In the Processes window, expand
Synthesize and double-click Check Syntax
 Double-click View RTL Schematic to verify that the synthesis compiler interprets your code
as a binary up/down counter

 Correct any errors. Ask for help from the instructor if needed

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-6


Creating a Testbench and Verifying Functionality

Step 2

General Flow for this Lab:
Step 1:
Creating an
n-Bit Counter
with Generics

Step 2:
Creating a
Testbench
and Verifying
Functionality

Build a testbench to verify the functionality of the counter and the accuracy of the
RTL source code.
 Select Project  New Source

 In the New Source dialog box, select VHDL Test Bench and enter MY_CNTR_TB in the File
name field
 Click Next
 When prompted to select the module for which the testbench is to be associated, select
MY_CNTR
As in the “VHDL Simulation and RTL Verification” lab, the testbench wizard creates the
structural portion of the top-level testbench. You can concentrate on creating the input
stimulus.
!
!

The testbench wizard does not maintain the generic in the component declaration, but
rather uses the assigned value, which is okay in this example because you do not plan to
actually change its value. However, if that were your objective, you would need to modify
this code to restate the generic or manually copy and paste the original source code to
maintain it.

Create the input stimulus. If you have problems creating the specified input
stimulus, ask for assistance from the instructor.
 Set the clock signal to toggle at a rate of 100 MHz
 Assert the reset signal at time 15 ns, hold for 25 ns, and then de-assert
 Set the CE signal initially to high and make it low at time 300 ns for 100 ns
 Set the LOAD signal initially to low and toggle it high at time 500 ns for one full clock cycle
 Set the UPDN signal initially to high and then low at time 750 ns
 Set the D_IN signal value to X”0F”, or 00001111

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com

1-877-XLX-CLAS

12b-7


Perform a syntax check and simulate by using the ISE Simulator.
 In the Sources for window, select MY_CNTR_TB.vhd and in the Processes window, doubleclick Check Syntax
 Correct any errors before proceeding. Ask for help from the instructor if needed
 In the Processes window, double-click Simulate Behavioral Model

Conclusion
In this exercise, you created a fully functional binary counter that can be dynamically scaled to
any length. The use of generics is an important tool for module reuse and source-code readability.
You also observed that the ISE™ software environment contains HDL source code templates that
you can use as a quick reference or starting point for user-specific code.
Finally, you created a testbench with stimulus designed to verify key aspects of the counter’s
operation.

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-8


A

Answers

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity MY_CNTR is
generic ( CNT_WIDTH : integer := 8);
port
( D_IN : in std_logic_vector (CNT_WIDTH -1 downto 0);
CLK, RST, UpDn, LOAD, CE : in std_logic;
Q_OUT: out std_logic_vector (CNT_WIDTH -1 downto 0)
end MY_CNTR;

);

architecture RTL of MY_CNTR is
signal COUNT :std_logic_vector (CNT_WIDTH -1 downto 0);
begin
process ( CLK, RST )
begin
if RST='1' then
COUNT <= ( others => ‘0’ ) ;
elsif rising_edge (CLK) then
if CE='1' then
if LOAD='1' then
COUNT <= D_IN;
else
if UpDn='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;

end if;
end if;
end if;
end if;
end process;
Q_OUT <= COUNT;
end RTL;

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-9


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity MY_CNTR_TB is
end MY_CNTR_TB;
architecture TEST of MY_CNTR_TB is
signal CLK_SIG:
std_logic := '1';
signal RST_SIG:
std_logic := '1';
signal UpDn_SIG:
std_logic := '1';

signal CE_SIG:
std_logic := '1';
signal LOAD_SIG:
std_logic := '0';
signal D_IN_SIG:
std_logic_vector ( 7 downto 0) := X"0F";
signal Q_OUT_SIG:
std_logic_vector ( 7 downto 0);
COMPONENT my_cntr
PORT(
d_in : IN std_logic_vector(7 downto 0);
clk : IN std_logic ;
rst : IN std_logic ;
updn : IN std_logic;
load : IN std_logic;
ce : IN std_logic;
q_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
UUT: my_cnt8 PORT MAP(
d_in => D_IN_SIG,
clk => CLK_SIG,
rst => RST_SIG,
updn => UpDn_SIG,
load => LOAD_SIG,
ce => CE_SIG,
q_out => Q_OUT_SIG
);
CLK_SIG <= not CLK_SIG after 5 ns;

CE <= ‘1’, ‘0’ after 300 ns, ‘1’ after 400 ns;
RST_SIG <= '0' after 15 ns, '1' after 40 ns;
UpDn_SIG <= '0' after 750 ns;
LOAD_SIG <= '1' after 500 ns, '0' after 510 ns;
end TEST;

n-Bit Binary Counter and
RTL Verification Lab

www.xilinx.com
1-877-XLX-CLAS

12b-10