kiến trúc máy tính phạm minh cường chương ter4 part2 the processorsinhvienzone com
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Computer Architecture
Chapter 4: The Processor Part 2
Dr. Phạm Quốc Cường
Adapted from Computer Organization the Hardware/Software Interface – 5th
Computer Engineering – CSE – HCMUT
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1
Single-cycle Datapath
Chapter 4 — The Processor — 2
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(Multi-cycle) Pipelined Datapath
• Up to five instruction will be in execution in
one clock cycle
• Separate the datapath into five pieces:
– IF: Instruction fetch
– ID: Instruction decode and register file read
– EX: Execution and address calculation
– MEM: Data memory access
– WB: Write back
3
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Five Stage Datapath
4
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Instructions Execution
5
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Pipeline registers
• Need registers between stages
– To hold information produced in previous cycle
Chapter 4 — The Processor — 6
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Pipeline Operation
• Cycle-by-cycle flow of instructions through the
pipelined datapath
– “Single-clock-cycle” pipeline diagram
• Shows pipeline usage in a single cycle
• Highlight resources used
– c.f. “multi-clock-cycle” diagram
• Graph of operation over time
• We’ll look at “single-clock-cycle” diagrams for
load & store
Chapter 4 — The Processor — 7
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IF for Load, Store, …
Chapter 4 — The Processor — 8
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ID for Load, Store, …
Chapter 4 — The Processor — 9
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EX for Load
Chapter 4 — The Processor — 10
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MEM for Load
Chapter 4 — The Processor — 11
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WB for Load
Wrong
register
number
Chapter 4 — The Processor — 12
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Corrected Datapath for Load
Chapter 4 — The Processor — 13
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EX for Store
Chapter 4 — The Processor — 14
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MEM for Store
Chapter 4 — The Processor — 15
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WB for Store
Chapter 4 — The Processor — 16
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Multi-Cycle Pipeline Diagram
• Form showing resource usage
Chapter 4 — The Processor — 17
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Multi-Cycle Pipeline Diagram
• Traditional form
Chapter 4 — The Processor — 18
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Single-Cycle Pipeline Diagram
• State of pipeline in a given cycle
Chapter 4 — The Processor — 19
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Pipelined Control (Simplified)
Chapter 4 — The Processor — 20
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Pipelined Control
• Control signals derived from instruction
– As in single-cycle implementation
Chapter 4 — The Processor — 21
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Pipelined Control
Chapter 4 — The Processor — 22
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Data Hazards in ALU Instructions
• Consider this sequence:
sub
and
or
add
sw
$2, $1,$3
$12,$2,$5
$13,$6,$2
$14,$2,$2
$15,100($2)
• We can resolve hazards with forwarding
– How do we detect when to forward?
Chapter 4 — The Processor — 23
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Dependencies & Forwarding
Chapter 4 — The Processor — 24
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Detecting the Need to Forward
• Pass register numbers along pipeline
– e.g., ID/EX.RegisterRs = register number for Rs sitting in
ID/EX pipeline register
• ALU operand register numbers in EX stage are given
by
– ID/EX.RegisterRs, ID/EX.RegisterRt
• Data hazards when
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Chapter 4 — The Processor — 25
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Fwd from
EX/MEM
pipeline reg
Fwd from
MEM/WB
pipeline reg
