Lecture Operating systems: A concept-based approach (2/e): Chapter 2 - Dhananjay M. Dhamdhere
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Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 1
Copyright © 2008
Overview of operating systems
•
A modern OS contains a very large number of features
– Many of these features were first introduced in different classes
of operating systems, namely
* Batch Processing operating systems
* Multiprogramming operating systems
* Time sharing operating systems
* Real time operating systems
* Distributed operating systems
– These features are used in a modern OS as well
* We study these features in the context of the relevant OS
* Study their influence on system performance and user service
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 2
Copyright © 2008
Recap from Chapter 1
•
The fundamental goals of an operating system
– Obtain
* High system performance
* Good user service
within a computing environment
– A computing environment consists of a computer system, its
interfaces with other systems, and user computations
* Measures of system performance and user service depend on the
computing environment
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 3
Copyright © 2008
Recap from Chapter 1
•
Fundamental tasks of an OS
– Management of Programs
* Organize their execution by sharing the CPU
* Ensure good user service
– Management of Resources
* Fast allocation and de-allocation without constraining user programs
* Efficient use of resources
– Security and Protection
* Ensure absence of interference with programs and resources by
entities within and outside the OS
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 4
Copyright © 2008
Introduction
In this chapter, we shall first study:
• Fundamentals of OS operation
– Features of a computer that are important for an OS
– How the OS controls execution of programs
– How a program interacts with an OS
•
Efficiency, system performance and user convenience
– Measures of system performance
– User service as a measure of user convenience
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 5
Copyright © 2008
OS and the Computer System
•
In this module, we study
– Fundamental features of computer systems that are important to
an OS
* Memory hierarchy
* Interrupt structure
* I/O organization
– How an OS uses these features to control operation of an OS
– Fundamentals of how a program interacts with an OS
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 6
Copyright © 2008
Memory utilization during operation of an OS
• The kernel is the core of the OS; it is memory resident at all times
• Nonkernel programs are loaded in the transient area when needed
• Rest of the memory is shared between user programs
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 7
Copyright © 2008
Model of a computer system
• The CPU and the I/O subsystem have independent paths to memory
• The memory management unit plays a part in implementing virtual memory
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 8
Copyright © 2008
The program status word (PSW)
•
The CPU contains two kinds of registers
– User accessible registers
* Used for arithmetic or logical operations, addressing, indexing, etc.
These are called general purpose registers, or simply, CPU
registers
– Control registers
* Condition code register (also called the flags register), program
counter, etc.
* Their contents govern operation of the CPU
•
Control registers are collectively called the program
status word (PSW)
– Individual control registers are considered as fields of the PSW
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 9
Copyright © 2008
Fields of the Program Status Word (PSW)
• The ‘privileged mode’ field indicates whether the CPU is in the privileged
mode, which is used by the OS, or user mode
* Some instructions can be executed only when CPU is in the privileged mode
• Condition code and Program counter registers were mentioned before
• Other registers are discussed later
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 10
Copyright © 2008
Privileged mode of CPU
•
The CPU can operate in two modes. The privileged
mode (P) field of PSW controls the CPU mode
– Privileged mode (`P’ field contains 1)
* Certain sensitive instructions can be executed only when the CPU is
in this mode
For example, initiation of an I/O operation, setting protection
information for a program
These instructions are called privileged instructions
– User mode
* Privileged instructions cannot be executed when the CPU is in this
mode
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 11
Copyright © 2008
State of the CPU
•
The state of the CPU consists of
– The PSW and contents of the general purpose registers of the
CPU
– It indicates
* What the CPU is engaged in doing at any moment
* What the CPU can do, in terms of privileges to perform certain
operations
– The OS keeps track of the state of the CPU to know what the
program currently executing on the CPU is doing
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 12
Copyright © 2008
State of the CPU
(a) An assembly language program
(b) CPU state of the program after executing the COMPARE instruction
– 0 in the P field indicates that the CPU is in the user mode
– 150 in the PC field indicates that the CPU is about to execute the
instruction with address 150
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 13
Copyright © 2008
Memory hierarchy
•
The memory hierarchy is a cost-effective method of
obtaining a large and fast memory
– It is an arrangement of several memories with different access
speeds and sizes
* The CPU accesses only the fastest memory; i.e., the cache
* If a required byte is not present in the memory being accessed, it is
loaded there from a slower memory
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 14
Copyright © 2008
Memory hierarchy
• Cache memory is the fastest and disk the slowest in the hierarchy
• The CPU accesses only the cache memory
• If required data or instruction is not present in the cache, it is loaded there
from memory (if not present in memory, it is first loaded from disk)
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 15
Copyright © 2008
Memory hierarchy
•
Cache memory
– Organization
* A cache block or cache line is loaded from memory when some
byte in it is referenced
* A ‘write-through’ arrangement is typically used to update memory
– The cache hit ratio (h) indicates what percentage of accessed
bytes were already present in cache
* The cache hit ratio has high values because of
Temporal locality
Spatial locality
* Effective memory access time =
h x access time of cache memory +
(1 – h) x (time to load a cache block + access time of cache memory)
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 16
Copyright © 2008
Memory hierarchy
•
Main memory
– Memory protection prevents access to memory by an
unauthorized program
* Memory bound registers indicate bounds of the memory allocated to
a program (see next slide)
•
Virtual memory
– The part of memory hierarchy consisting of the main memory
and a disk is called virtual memory
* A program and its data are stored on the disk
* Required portions of the program and its data are loaded in memory
when accessed
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 17
Copyright © 2008
Memory protection using bound registers
• The lower bound register (LBR) and upper bound register (UBR) contain
addresses of first and last bytes allocated to the program
• LBR, UBR are stored in the memory prot info (MPI) field of the PSW
• The CPU raises an interrupt if an address is outside the LBR–UBR range
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 18
Copyright © 2008
Input / Output organization
•
An I/O operation slows down a program’s execution due
to mismatch of CPU and I/O speeds
– Involvement of the CPU in I/O operations should be the
minimum possible
* CPU should be free to execute instructions while I/O operations are
in progress
– Different I/O modes
* Programmed I/O
* Interrupt I/O
* Direct memory access (DMA)
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 19
Copyright © 2008
Input / Output modes
•
Details of the Input/output modes
– Programmed I/O
* Data transfer between memory and an I/O device takes place
through the CPU
CPU cannot perform any other operation until I/O completes
– Interrupt I/O
* An I/O instruction starts an I/O operation and frees the CPU to
execute other instructions
An interrupt is raised every time a unit of data is to be
transferred between memory and the I/O device
An interrupt processing program in the kernel actually transfers
the data
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 20
Copyright © 2008
Input / Output modes
•
Details of the Input/output modes (contd)
– Direct memory access (DMA)
* An I/O instruction indicates the operation to be performed and the
number of bytes of data to be transferred. Its execution starts the
I/O operation
Data transfer is coordinated by the DMA controller; it does not
involve the CPU
When the I/O operation completes, the DMA controller raises
an I/O interrupt to indicate its completion (interrupts are
discussed later)
CPU is free to execute other instructions while an I/O operation
is in progress
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 21
Copyright © 2008
Interrupts
•
An interrupt signals the occurrence of an event to the
CPU
– An event is a situation that requires OS intervention
– At an interrupt, the interrupt action in the hardware diverts the
CPU to execution of an interrupt processing routine (IPR)
* The IPR is a routine in the OS kernel
* It handles the situation that caused the interrupt
* After the IPR, kernel switches the CPU to execution of a user
program
– Different classes of interrupts convey occurrences of different
kinds of events
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 22
Copyright © 2008
Classes of interrupts
•
Three important classes of interrupts are
– Program interrupt
* Caused by conditions within the CPU during execution of an
instruction; e.g.,
Occurrence of an arithmetic overflow, addressing exception, or
memory protection exception
Execution of the software interrupt instruction
– I/O interrupt
* Indicates completion of an I/O operation
– Timer interrupt
* Indicates that a specified time interval has elapsed
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 23
Copyright © 2008
The interrupt action
1. The interrupt code is formed depending on the cause of the interrupt;
it is stored in the interrupt code (IC) field of the PSW
2. The PSW is saved in a memory location (or in the stack)
3. Contents of an appropriate interrupt vector are loaded in the PSW;
new contents of the PSW now control CPU operation
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 24
Copyright © 2008
Steps in interrupt action
•
The interrupt action consists of three steps
1. Set interrupt code in the PSW
*
The code describes the situation that caused the interrupt
*
It is stored in the interrupt code field of the PSW
1. Save the PSW
*
PSW is saved in a memory location
*
Interrupt code gets saved as a part of the PSW
1. Load interrupt vector
*
Interrupt vector of the occurred interrupt is chosen
It contains address of the interrupt processing routine (IPR)
*
It is loaded in the PSW
Control is transferred to the IPR
Chapter 2: Overview of
Operating Systems
Dhamdhere: Operating Systems—
A ConceptBased Approach , 2 ed
Slide No: 25
Copyright © 2008
