CPU- Synthesis Description

CHAPTER
1
Basic Concepts
This chapter answers the question, “What are abstract data
types?” The idea of using well-designed abstract data types
(ADTs) to simplify the development life cycle and to create
reusable code is well established. This chapter covers the ba-
sics of designing and implementing ADTs in an object-ori-
ented programming language. As a foundation to exploring
data abstraction, we will take a look inside Java and ex-
plore some of the internal workings of the Java runtime sys-
tem. Java reference objects will be explained. The passing
of reference and value types as arguments and how each
type of argument passing is used in the Java programming
language will be discussed. Near the end of this chapter, ex-
ercises are provided to stimulate understanding in the use
of reference objects.
1
CHAPTER
13
13
CPU: Synthesis
Description
In this chapter, we further refine the CPU description and
examine the RTL (Register Transfer Level) description of
the CPU. The CPU is described by a number of lower-level
components that are instantiated to form the CPU design.
At the top of the CPU design is an architecture that
instantiates all of the lower-level components to form
the CPU. The CPU block diagram is shown in Figure 13-1.
Chapter Thirteen

304
Reg0
Reg1
Reg2
Reg3
•
•
Reg7
Regsel
ProgCnt
AddrReg
Addr(15:0)
Data(15:0)
ALU
Control
Ready
R/W
VMA
Shifter
Shiftsel
Alusel
OutReg
Progsel
Addrsel
Outsel
OpReg
OpRegsel
InstrReg
Instrsel
Clock

Reset
Comp
Compsel
CompoutCompout
Figure 13-1
CPU Block Diagram.
Following is an implementation of this block diagram, shown by file
cpu.vhd
:
library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity cpu is
port(clock, reset, ready : in std_logic;
port(addr : out bit16;
port(rw, vma : out std_logic;
port(data : inout bit16);
end cpu;
architecture rtl of cpu is
component regarray
port( data : in bit16;
port( sel : in t_reg;
port( en : in std_logic;
port( clk : in std_logic;
port( q : out bit16);
end component;
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CPU: Synthesis Description
component reg
port( a : in bit16;

port( clk : in std_logic;
port( q : out bit16);
end component;
component trireg
port( a : in bit16;
port( en : in std_logic;
port( clk : in std_logic;
port( q : out bit16);
end component;
component control
port( clock : in std_logic;
port( reset : in std_logic;
port( instrReg : in bit16;
port( compout : in std_logic;
port( ready : in std_logic;
port( progCntrWr : out std_logic;
port( progCntrRd : out std_logic;
port( addrRegWr : out std_logic;
port( outRegWr : out std_logic;
port( outRegRd : out std_logic;
port( shiftSel : out t_shift;
port( aluSel : out t_alu;
port( compSel : out t_comp;
port( opRegRd : out std_logic;
port( opRegWr : out std_logic;
port( instrWr : out std_logic;
port( regSel : out t_reg;
port( regRd : out std_logic;
port( regWr : out std_logic;
port( rw : out std_logic;

port( vma : out std_logic
port( );
end component;
component alu
port( a, b : in bit16;
port( sel : in t_alu;
port( c : out bit16);
end component;
component shift
port ( a : in bit16;
port( sel : in t_shift;
port( y : out bit16);
end component;
component comp
port( a, b : in bit16;
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306
port( sel : in t_comp;
port( compout : out std_logic);
end component;
signal opdata, aluout, shiftout, instrregOut : bit16;
signal regsel : t_reg;
signal regRd, regWr, opregRd, opregWr, outregRd, outregWr,
signal addrregWr, instrregWr, progcntrRd, progcntrWr,
signal compout : std_logic;
signal alusel : t_alu;
signal shiftsel : t_shift;
signal compsel : t_comp;
begin
ra1 : regarray port map(data, regsel, regRd, regWr, data);

opreg: trireg port map (data, opregRd, opregWr, opdata);
alu1: alu port map (data, opdata, alusel, aluout);
shift1: shift port map (aluout, shiftsel, shiftout);
outreg: trireg port map (shiftout, outregRd, outregWr,
data);
addrreg: reg port map (data, addrregWr, addr);
progcntr: trireg port map (data, progcntrRd, progcntrWr,
data);
comp1: comp port map (opdata, data, compsel, compout);
instr1: reg port map (data, instrregWr, instrregOut);
con1: control port map (clock, reset, instrregOut, com
pout, ready, progcntrWr, progcntrRd, addrregWr, out
regWr, outregRd, shiftsel, alusel, compsel, opre
gRd, opregWr, instrregWr, regsel, regRd, regWr, rw,
vma);
end rtl;
Architecture
rtl
of entity
cpu
is a structural implementation of the
block diagram. Architecture
rtl
contains the component declarations of all
of the components used to build the design, the signals used to connect the
components, and the component instantiations to create the functionality.
After the component and signal declarations are the component instan-
tiation statements that instance the components and connect the appro-
priate signals. In the next few sections, each of the VHDL component
descriptions is described in more detail.

ALU
The first entity described is the ALU. This entity performs a number of
arithmetic or logical operations on one or more input busses. A symbol for
the ALU is shown in Figure 13-2.
307
CPU: Synthesis Description
c
sel
ab
ALU
Figure 13-2
ALU Interface.
Inputs
a
and
b
are the two input busses upon which the ALU operations
are performed. Output bus
c
returns the result of the ALU operation. Input
sel
determines which operation is performed as specified by Figure 13-3.
As we can see, the ALU can perform a number of arithmetic operations,
such as add and subtract, and some logical operations, such as AND, OR,
and XOR. Following is a VHDL description of the ALU entity:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_lib.all;
entity alu is

port( a, b : in bit16;
port( sel : in t_alu;
port( c : out bit16);
end alu;
architecture rtl of alu is
begin
aluproc: process(a, b, sel)
begin
case sel is
when alupass =>
c <= a after 1 ns;
when andOp =>
c <= a and b after 1 ns;
when orOp =>
c <= a or b after 1 ns;
when xorOp =>
c <= a xor b after 1 ns;
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308
Sel Input Operation
0000 C = A
0001 C = A AND B
0010 C = A OR B
0011 C = NOT A
0100 C = A XOR B
0101 C = A + B
0110 C = A – B
0111 C = A + 1
1000 C = A –1
1001 C = 0

Figure 13-3
ALU Function Table.
when notOp =>
c <= not a after 1 ns;
when plus =>
c <= a + b after 1 ns;
when alusub =>
c <= a - b after 1 ns;
when inc =>
c <= a + “0000000000000001” after 1 ns;
when dec =>
c <= a - “0000000000000001” after 1 ns;
when zero =>
c <= “0000000000000000” after 1 ns;
when others =>
c <= “0000000000000000” after 1 ns;
end case;
end process;
end rtl;
The architecture uses a large
case
statement on input
sel
to determine
which of the arithmetic or logical operations to perform. The possible
values of signal
sel
are determined by type
t_alu
described in package

cpu_lib
in file
cpulib.vhd
. After the new value for output
c
is calculated,
all of the resulting values are assigned with a 1-nanosecond time delay
to eliminate delta delay problems during RTL simulation.
309
CPU: Synthesis Description
Comp
The next component described is the comparator entity
comp
. This entity
compares two values and returns either a
‘1’
or
‘0’
depending on the
type of comparison requested and the values being compared. A symbol
showing the ports of the comparator is shown in Figure 13-4.
The comparison type is determined by the value on input port
sel
.For
instance, to compare if inputs
a
and
b
are equal, apply the value
eq

to port
sel
. If ports
a
and
b
have the same value, port
compout
returns
‘1’
. If the
values are not equal,
‘0’
is returned. The types of comparisons allowed are
described by type
t_comp
in package
cpu_lib
in file
cpulib.vhd
described
earlier. The full table of comparison types and values is shown in Figure 13-5.
All operations work on two input values and return a single bit result.
This bit is used to control the flow of operation within the processor while
executing instructions. Following is a VHDL description of the
comp
entity:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

compout
sel
ab
Comp
Figure 13-4
Comp Interface.
Sel input value Comparison
EQ Compout = 1 when a equals b
NEQ Compout = 1 when a is not equal to b
GT Compout = 1 when a is greater than b
GTE Compout = 1 when a is greater than or equal to b
LT Compout = 1 when a is less than b
LTE Compout = 1 when a is less than or equal to b
Figure 13-5
Comp Operation
Table.
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310
use work.cpu_lib.all;
entity comp is
port( a, b : in bit16;
sel : in t_comp;
compout : out std_logic);
end comp;
architecture rtl of comp is
begin
compproc: process(a, b, sel)
begin
case sel is
when eq =>

if a = b then
compout <= ‘1’ after 1 ns;
else
compout <= ‘0’ after 1 ns;
end if;
when neq =>
if a /= b then
compout <= ‘1’ after 1 ns;
else
compout <= ‘0’ after 1 ns;
end if;
when gt =>
if a > b then
compout <= ‘1’ after 1 ns;
else
compout <= ‘0’ after 1 ns;
end if;
when gte =>
if a >= b then
compout <= ‘1’ after 1 ns;
else
compout <= ‘0’ after 1 ns;
end if;
when lt =>
if a < b then
compout <= ‘1’ after 1 ns;
else
compout <= ‘0’ after 1 ns;
end if;
when lte =>

if a <= b then
compout <= ‘1’ after 1 ns;
else
compout <= ‘0’ after 1 ns;
end if;
end case;
end process;
end rtl;
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CPU: Synthesis Description
The comparator consists of a large
case
statement where each branch
of the
case
statement contains an
IF
. If the condition tested is true, a
‘1’
value is assigned; otherwise, a
‘0’
is assigned. Again, each assignment
occurs after 1 nanosecond to remove delta delay problems.
Control
The
control
entity provides the necessary signal interactions to make the
data flow properly through the CPU and perform the expected functions.
Architecture
rtl

contains a state machine that causes all appropriate signal
values to update based on the current state and input signals and produce
a next state for the state machine. A symbol for the control block is shown
in Figure 13-6.
The control symbol has only a few inputs, but a lot of outputs. The
control block provides all of the control signals to regulate data traffic for
the CPU. Following is the VHDL description for the CPU:
library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity control is
port( clock : in std_logic;
port( reset : in std_logic;
port( instrReg : in bit16;
port( compout : in std_logic;
port( ready : in std_logic;
port( progCntrWr : out std_logic;
port( progCntrRd : out std_logic;
port( addrRegWr : out std_logic;
port( addrRegRd : out std_logic;
port( outRegWr : out std_logic;
port( outRegRd : out std_logic;
port( shiftSel : out t_shift;
port( aluSel : out t_alu;
port( compSel : out t_comp;
port( opRegRd : out std_logic;
port( opRegWr : out std_logic;
port( instrWr : out std_logic;
port( regSel : out t_reg;
port( regRd : out std_logic;

port( regWr : out std_logic;
port( rw : out std_logic;
port( vma : out std_logic
port);
end control;
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312
Reset
ProgCntrWr
ProgCntrRd
AddrRegWr
AddrRegRd
OutRegWr
OutRegRd
ShiftSel
AluSel
CompSel
OpRegRd
OpRegWr
InstrWr
RegSel
RegRd
RegWr
Rw
Vma
Clock
InstrReg
Compout
Ready
Control

Figure 13-6
Control Symbol.
architecture rtl of control is
signal current_state, next_state : state;
begin
nxtstateproc: process( current_state, instrReg, compout,
nxtstateproc: process( ready)
begin
progCntrWr <= ‘0’;
progCntrRd <= ‘0’;
addrRegWr <= ‘0’;
outRegWr <= ‘0’;
outRegRd <= ‘0’;
shiftSel <= shftpass;
aluSel <= alupass;
compSel <= eq;
opRegRd <= ‘0’;
opRegWr <= ‘0’;
instrWr <= ‘0’;
regSel <= “000”;
regRd <= ‘0’;
regWr <= ‘0’;
rw <= ‘0’;