VHDL Reference Tables

Appendix B
VHDL Reference Tables
This appendix focuses on tables of information that are useful when writ-
ing VHDL descriptions. Most of the information in the tables is available
in the text of the book, however, these tables consolidate the information
into one area for easy reference.
Table B-1 lists all of the different kinds of statements alphabetically
and includes an example usage.
Table B-1
Statement or Clause Example(s)
Access Type TYPE access_type IS ACCESS type_to_be_accessed;
Aggregate record_type := (first, second, third);
Alias ALIAS opcode : BIT_VECTOR (0 TO 3) IS
INSTRUCTION(10 TO 13);
Architecture ARCHITECTURE architecture_name OF entity
name IS
--
declare some signals here
BEGIN
--
put some concurrent statements here
END architecture_name;
Array Type TYPE array_type IS ARRAY (0 TO 7) OF BIT;
Assert ASSERT x > 10 REPORT “x is too small”
SEVERITY ERROR;
Attribute Declaration ATTRIBUTE attribute_name : attribute_type;
Attribute Specification ATTRIBUTE attribute_name OF
entity_name : entity_class IS value;
Block Statement block_name : BLOCK
--
declare some stuff here

BEGIN
--
put some concurrent statements here
END BLOCK block_name;
Case Statement CASE some_expression IS
WHEN some_value =>
--
do_some_stuff
WHEN some_other_value =>
--
do_some_other_stuff
WHEN OTHERS =>
--
do_some_default_stuff
END CASE;
Appendix B: VHDL Reference Tables
436
Table B-1
Continued.
Statement or Clause Example(s)
Component Declaration COMPONENT component_name
PORT (port1_name : port1_type;
port2_name : port2_type;
port3_name : port3_type);
END COMPONENT;
Component Instantiation instance_name : component_name PORT MAP
(first_port, second_port, third_port);
instance_name : component_name PORT MAP
(formal1 => actual1, formal2 => actual2);
Conditional Signal Assignment target <= first_value WHEN (x = y) ELSE

second_value WHEN a >= b ELSE
third_value;
Configuration Declaration CONFIGURATION configuration_name OF
entity_name IS
FOR architecture_name
FOR instance_name : entity_name USE
ENTITY
library_name.entity_name
(architecture_name);
END FOR;
FOR instance_name : entity_name USE
CONFIGURATION
library_name.configuration_name;
END FOR;
END FOR;
END configuration_name;
Constant Declaration CONSTANT constant_name : constant_type :=
value;
Entity Declaration ENTITY entity_name IS
PORT (port1 : port1_type;
port2 : port2_type);
END entity_name;
Exit Statement EXIT;
EXIT WHEN a <= b;
EXIT loop_label WHEN x = z;
File Type Declaration TYPE file_type_name IS FILE OF data_type;
File Object Declaration FILE file_object_name : file_type_name IS IN
“/absolute/path/name”;
For Loop FOR loop_variable IN start TO end LOOP
--

do_some_stuff
END LOOP;
437
Appendix B: VHDL Reference Tables
Table B-1
Statement or Clause Example(s)
Function Declaration FUNCTION function_name (parameter1 :
parameter1_type;
parameter2 :
parameter2_type)
RETURN return_type;
Function Body FUNCTION function_name (parameter1 :
parameter1_type;
parameter2 :
parameter2_type)
RETURN return_type IS
BEGIN
--
do some stuff
END function_name;
Generate Statement generate_label : FOR gen_var IN start TO end
GENERATE label : component_name PORT
MAP (.........);
END GENERATE;
Generic Declaration GENERIC (generic1_name : generic1_type;
generic2_name : generic2_type);
Generic Map GENERIC MAP (generic1_name => value1,
value2);
Guarded Signal Assignment g1 : BLOCK (clk = ‘1’ AND clk’EVENT)
BEGIN

q <= GUARDED d AFTER 5 NS;
END BLOCK;
IF Statement IF x <= y THEN
--
some statements
END IF;
IF z > w THEN
--
some statements
ELSIF q < r THEN
--
some more statements
END IF;
IF a = b THEN
--
some statements
ELSIF c = d THEN
--
some more statements
ELSE
--
even more statements
END IF;
Incomplete Type TYPE type_name;
Appendix B: VHDL Reference Tables
438
Table B-1
Continued.
Statement or Clause Example(s)
Library Declaration LIBRARY library_name;

Loop Statement FOR loop_variable IN start TO end LOOP
--
do lots of stuff
END LOOP;
WHILE x < y LOOP
--
modify x and y and do other stuff
END LOOP;
Next Statement IF i < 0 THEN
NEXT;
END IF;
Others Clause WHEN OTHERS =>
--
do some stuff
Package Declaration PACKAGE package_name IS
--
declare some stuff
END PACKAGE;
Package Body PACKAGE BODY package_name IS
--
put subprogram bodies here
END package_name;
Physical Type TYPE physical_type_name IS RANGE start TO end
UNITS
unit1 ;
unit2 = 10 unit1;
unit3 = 10 unit2;
END UNITS;
Port Clause PORT ( port1_name : port1_type; port2_name :
port2_type);

Port Map Clause PORT MAP (port1_name => signal1, signal2);
Procedure Declaration PROCEDURE procedure_name (parm1 : in
parm1_type; parm2 : out
parm2_type; parm3 :
inout parm3_type);
Procedure Body PROCEDURE procedure_name (parm1 : in
parm1_type; parm2 : out
parm1_type; parm3 :
inout parm3_type) IS
BEGIN
--
do some stuff
END procedure_name;
439
Appendix B: VHDL Reference Tables
Table B-1
Statement or Clause Example(s)
Process Statement PROCESS (signal1, signal2, signal3)
--
declare some stuff
BEGIN
--
do some stuff
END PROCESS;
Record Type TYPE record_type IS
RECORD
field1 : field1_type;
field2 : field2_type;
END RECORD;
Report Clause ASSERT x = 10 REPORT “some string”;

Return Statement RETURN;
RETURN (x + 10);
Selected Signal Assignment WITH z SELECT
x <= 1 AFTER 5 NS WHEN 0,
2 AFTER 5 NS WHEN 1,
3 AFTER 5 NS WHEN OTHERS;
Severity Clause ASSERT x > 5 REPORT “some string” SEVERITY
ERROR;
Signal Assignment a <= b AFTER 20 NS;
Signal Declaration SIGNAL x : xtype;
Subtype Declaration SUBTYPE bit8 IS INTEGER RANGE 0 TO 255;
Transport Signal Assignment x <= TRANSPORT y AFTER 50 NS;
Type Declaration TYPE color is (red, yellow, blue, green, orange);
TYPE small_int is 0 to 65535;
Use Clause USE WORK.my_package.all;
Variable Declaration VARIABLE variable_name : variable_type;Wait
Statement WAIT ON a, b, c;
WAIT UNTIL clock’EVENT AND clock = ‘1’;
WAIT FOR 100 NS;
WAIT ON a, b UNTIL b > 10 FOR 50 NS;
While Loop WHILE x > 15 LOOP
--
do some stuff
END LOOP;
Table B-2 lists all of the predefined attributes that retrieve infor-
mation about VHDL type data. The descriptions are necessarily terse
to fit into the table cells; see Chapter 6, “Predefined Attributes” for
more detailed information.