Nghiên cứu và xây dựng cấu trúc systolic có độ phức tạp thấp của bộ lọc tự thích nghi

DAI HOC QUOC GIA HA N Q I

NGHIEN ClTU VA XAY D I T N G
CAU TRUC SYSTOLIC
CO DO PHLTC T A P T H A P

CUA BO LOC Tir THICH NGHI

Mas6: QC.07.02
Chii nhiem de tai: Tran Quang Vinh

DAI HOC QUOC GIA HA Npl_
TRUNG TAM T H O N G n M H U ^ ^ ^

000600000^^

HA NOI


MUC LUC
Noidunj;

Trang

Bang giai ihich cae ehCr \ iet tat

^

Danh saeh can bg iham gia de tai

4

Tom tat cac ket qua chinh ciia dc tai

5

Main results of project

7

Bao cao tong kct
2.1. Muc lieu \'a ngi dung nghien ciai

8

2.2. Dal van de

8

2.3. Cac mach Ige so

9

2.4. Bg Ige FIR

9

2.5. Bg Igc thieh nghi

II

2.6. Kien true Systolic eho bg Ige

13

2.7. VLSI. ASIC, FPGA va VHDL

18

2.8. Ngon ngu 'VHDL

22

2.9. Thue nghicm: ihiel ke. mo phong va thuc hien cac bg Ige FIR

24

\'a bg Igc ihich nghi eo eau true Systolic trcn FPGA
3.

Ket luan

38

4

Tai lieu tham khao

40

5.

Phicu dang ky ket qua nghien cuu KHCN

42

6.

CAC TAI LIEU LILN QUAN

44


Bang giai thich cac elm* viet tat

Bang 1: Giai thieh cae chCr viet tat
IC

Integrated Circuit

SSI

SmalLSeale Integration

MSI

Medium-Scale Integration

LSI

Large-Scale Integration

VLSI

Very-Large-Seale Integration

ASIC

Application Specific IC

PLD

Programmable Logic Device

FPGA

Field-Programmable Gate Array

LTI system

Linear Time - Invariant system

FIR filter

Finite Impulse Resonse filler

IIR filler

Infinite Impulse Response filler

DF-FIR

Direct Form Finite Impulse Resonse filler

TF-FIR

Transposed Form Finite Impulse Resonse filler

LMS

Least Mean Square algorithm

DLMS

Delyed LMS algorithm

VHDL

Very high speed integrated eircuit Hardware Description Language

ECG

Eleelroeardiograph

SNR

Ratio of Signal to noise


Danh sach can bo tham giai thuc hien de tai
Bang 2: Danh sach can bg, egng lac vicn, hgc vien eao hge va sinh vien tham gia

thue hien dc tai
ST ^

Ho va Ten

Co* quan

Hoc ham hoc \'\
PGS. TS

Dai hge Cong nghe

2 " " Nguyen Kiem Hung

ThS

Nghien eu'u sinh

3

ThS

Conci tv Aetive-Semi

Cu nhan

Dai hge Cong nghe

1

Iran Quang Vinh
Nguyen Manh Phuong

0

~"'4~ ~ Nguyen Anh Cuang

^

5

Mai Nggc I lung

Cu nhan

Dai hge Cong nghe

^'

Ngu)en Nggc Mai

Cu nhan

Dai hge Cong nghe


1.
Tom tat cac ket qua nghien cuu
chinh cua de tai
1.1. Ten de tai

Nghien cuu va xay dung eau true Systolic eo do phue lap ihap ciia
bg Ige lu thieh nghi.
Ma so: QC.07.02

1.2.

ChutridStai
Ten : PGS.TS. Tran Quang Vmli
Co quan : Truang Dai hge Cong nghe, Dai hge Quoe gia Ma ngi.
Dja chi : 144 Xuan Thuy, Can giay, Fla ngi.
Dienthoai : 04-3-7549572

1.3. Nhung ket qua ehinh
1.3.1. Ket qua ve khoa hoc:
• Da thiel ke thue hien duge eac bg Ige dien lu so thieh nghi hien dai ung dung
eong nghe Systolic thap ehieu (duang ong ID) trcn chip vi dien lu c6 do tieh
hgp Ion la FPGA cua hang Xilinx. Tuo"ng img voi do la cae mo-dun phan mem
du'gc phal trien tren ngon ngu dac la phan eung VFIDL su dung eho cae img
dung nghien cuu va giang day ve mot ITnli vue moi a Viet nam la thiel ke maeh
tieh hgp ca rat Ion VLSI eho xu ly tin hieu so. Cac ket qua nay da duge the hien
Irong 02 bao cao khoa hge sinh vien (01 duge giai nhal


dp truang) \'a c6 01 bao cao da gui den Hoi nghi qu6e le Cong nghe Thong tin
va Truycn lhe')ng ATCIO.
1.3.2. Ket qua phiic vu thuc tc
U'ng dung eho giang day ly thuyct va thue hanh eac mon hge "Fhiet ke so ',
•^Thiel k6 maeh ASIC va VLSI". "Cc^u true may vi tinh \ a ky thuat ghep noi",
va "Xu li tin hieu so" lai truang DHCN. DHQG MN. Cae mon hgc nay, voi cae
ung dung duge cap nhat lu da tai. eo th^ ap dung eho eac phep do lucmg tnet

nhicu tai cae he thong xu ly tin hieu. dieu khicn so hoae he thong vien thong.
1.3.3. Ket qua dao lao
So sinh vien lam Khoa luan lot nghiep lien quan den de tai: 03.
So sinh vien nghien cuu khoa hge lien quan den de tai: 03.
So hgc vien sau dai hoc lien quan den de tai: 02.
1 3 4 Ket qua naiij^ eao ticm luc khoa hoc
(.'6 duge nigl bg phan mem voi cae mo-dun dung eho vice xay dung eac bg Ige
thieh nghi I'lR c6 so bac Ige tin y Iren ca so ket hgp Kit phal trien Vertex-II
PRO cua Xilinx voi eac ngon ngu dae la phan cung VHDL va goi phan mem
MATLA!^.
1.3.5. Tinh hinh sii dung kinh phi
Da su dung hcl kinh phi duge cap eiia dc tai.
'

Muc
chi
119

Ngi dung chi

(ngan dong)
Chi nghiep \'u ehu) en mon:
- Xay dung de cuo'ng chi liet, ihu thap \'a
\ iet lai lieu long quan.
- Mua ihiet hi vat tu tieu hao

14

So lien
13.200

2.000
3.000

- Mua sach. djeh tai heu ehuycn mon

2.000

- In an
- Chi khac eho nghiep vu chuyen mon:

1.000
5.200

Chi phi thue muon chu\cn mon:
Tong egng

14.800
28.000

Ghi ehu


MAIN RESULTS OF THE PROJECT
1.

Title:

Study on Systolic architectures with low complexity for adaptive filters

Code:

QC.07.02

2.

Co-ordinator:

Assoc/Prof Dr. Tran Quang Vinh

3.

Main results
a) Scientific Signification:
o

Setup models of advanced adaptive digital fillers which are applied by the
Pipelied Systolic technology on VLSI microelectronic chips as the FieldProgrammable Gale Array FPGA one of Xilinx Corp.

o

There is 01 scientific report sending to the International Conference.

o

There is 02 the student's scientific reports which were awared.

o

Developed Software Modules are used for the realistic applications and
the new training fields of VLSI integrated Circuits Design in Vietnam in

present time..

b) Servini^:
The researching results of project can be used as docmenlalions for
teaching

not only on theory but also on praeties in some subjects like

''Computer structure & interfacing technique", "ASIC & VLSI design''
and "Digital Signal Processing" .
c) Training:
o

Number of undergraduate theses related project:

o

Number of graduate students: 02

o

Number of Student's Scientific Research: 03.

03

In brief:
'iliere is a software packet with some modules which are used for building the
normal FIR fillers, Pipelined Systolic FIR filters and the Adaptive digital filters with
high orders. The received results are basing on the combination of using the Vertex-II
PRO Xilinx kit and developing software modules with the hardware description

language like VHDL and software packet MATLAB.


2.
9

r

Bao cao tong Icet
2.1. Muc tieu va noi dung nghien eiiu
Muc lieu ehinh cua dc tai nay la nghien cuu thiel ke. mo phong va ihive hien mot
s6 bg Igc tin hieu so nhu bg Igc FIR va bg Ige thieh nghi tren mot chip FPGA. Tren eo
sa do cAu true Syslolie eo do phue lap thap duge phal trien tren eac bg Ige nay nham
tang hieu sual (cu ihe la tan so lay mfiu tin hieu cue dai) cua bg Ige.
Ngi dung nghien cuu eua de lai duge lien hanh tren 2 nhiem vu chinh sau.
Nhiem \ u ihu nhat la nghien euu long quan cae \an de ly lhu\et \ e eac bg Ige so,
bg Igc FIR. ho Ige thieh nghi, eau true S>slolie thap chieu va eae \i maeh tieh hgp ea
kVn VLSI la chip FPGA se duge sir dung de phal trien eae bg Igc nay.
Nhiem \u ihu hai la thiel ke. mo phong va thuc hien cac bg Igc FIR va bg Igc
ihieh nghi diing loi l-'IR ccS he so hien doi dLvgc tren mgl kit phal trien FPGA. Cae bg
Igc na\' cung dvxgc nghien cuu phal trien \ai eau true S\slolie bae thap de ehung minh
hieu qua tang toe do xu ly cua ehung. Ngon ngu dae la phan eung VHDL duge su
dung kcl hgp \ ai phan mem Mallab

2.2. Dat van (le :
Loe tin iiieu so duge su dung irong rat nhieu ITnh vue, lu xu ly tin hieu am ihanh
hinh anh den xu ly eac tin hieu dae bict irong eac llnh \ u c sonar, radar hay tin hieu y
sinh. Cac bg Igc so flR duge su dung nhieu do tinh dcm gian va on dinh. Phan mem
Ihicl ke cac ho Ige so kieu nay hien cung da \a dang duge nhung vao eae chip VLSI
hicn dai iilnr I I'Ci.A ciio phep c6 duge nhung chip ehu\en dung xu ly tin hieu so hieu

qua ironi; cac linh \ irc ke tren. Llien dai nhal trong cae ung dung na\' hien nay la eae
ho Inc iliich Hidii- Lac bg Igc na\ thu'cruL; su duuLZ loi la eae bg Ige FIR eo he so hien


d6i thieh nghi. Co nhieu giai thuat thuc hien de tim vector he so bien doi toi uu nay
voi do chinh xac va hoi tu thieh hgp. Trong so do, giai thuat binh phuong trung binh
toi thieu LMS duge su dung pho bien do tinh dan gian va hieu qua ciia no.
Trong kha nhieu ung dung, dac biet eho eae ung dung thai gian thue, can cae he
thong CO chat lugng dam bao nhung lai phai c6 mot toe do lay mau (dong nghia voi
toe do xu ly) nhanh, voi bae bg Ige ion. Do vay, mot so phuong phap xir ly phue tap
hon nhu Systolic du'ong ong DLMS da va dang duge nghien euu ap dung. Thuc chat
day la cac phuong phap xu ly duang ong hay xu" ly song song.

2.3, Cae maeh loe so
Giong nhu cae mach Igc tuang tu (analog filter), mgch Igc so (digital filler) Ihire
hien chue nang ehgn Igc tin hieu thco dai tan so. Cae bg Ige so dang duge nghien cuu
phal trien nhanh chong ihay the eho eae maeh Ige luong lu eo dien su dung cac linh
kien RLC va eae bg khueeh dai thuat loan. Cac bg Ige so duge su dung rgng rai trong
nhieu ung dung khac nhau eua xu ly tin hieu so. bao gom xu ly lieng noi. truyen du
lieu, xu ly anh va video, sonar, radar, xu ly dia ehan va tham do dau mo, dien dan
dung.
Cae maeh Ige so bat bien thai gian luycn linh L'LI (linear lime - invariant) duge
su dung thuang xuyen nhal do viee phan tieh, thiel ke va van hanh do'n gian. Mgl bg
Ige L l l lu'o"ng lae voi tin hieu vao qua mot xu li ggi la nhan chap (convolution)
y = h * X . Trong do x la vee-la eae mau tin hieu vao, v la vee-la eae mau tin hieu ra
va // la vee-to dap ung xung eua bg Ige.
Theo dang eua dap ung xung /?, cac bg Igc so LTI noi ehung duge phan Ihanh eae
hg Igc CO dc'ip ung xung huu hgn FIR (finite impulse response) va hg Igc c6 dap ung
xung vo hgn IIR (ininite impulse response). Nhu ten ggi eua no, bg Igc FIR ehua mgl
so hu'u ban eae gia tri mau tin hieu, lam giam long chap 6" tren thanh mgl long hCru ban

eho mot mau tin hieu ra. Trong khi do, bg Igc IIR iai doi hoi mot long v6 ban duge
thue hien.
Thict ke bg Igc so da duge ehu trgng trong nhieu nam qua. Van de quan Irgng
trong thiel ke bg Ige ehinh la lim kiem duge mot dap ung tan so I-I{co) xap xi lot nhat
voi dap ung bien do va pha nhu mong muon.

2.4. BoIocFIR


Do uu diSm 6n dinh nen bg Igc FIR thuong duge chgn lam loi de xay dung cac
c^u true Igc quan lam. Chuoi mau du lieu ra cua mgl bg Ige FIR eo do dai L (hay hgc
Igc L-1) nhan duge tu mgl chuoi mau 16i vao x{n) la mgl long chap hCm ban sau:
(1
Trong do- /?„ ^ 0 tai /?,_, ^ 0 la /. he s6 eua bg Ige. Chung cung phu hgp voi dap
un\i, xung cua bg Igc FIR. Voi cae he L'fl, thuan lien ban neu bieu dien trong mien z:
Y{z)=n{z)X{z)

(2)

Trone do //(/,) la ham tru\en cua bg Igc duge dinh nghTa trong mien - nhu sau:

(3)

//(r) = X/'. --'
k-

(1

So do khoi cua mol bo loe 1-IR bac L-1 nhu I linh I sau:

x{n)

•- z

/'.)

-L-2 - K S )

h2

S

(y-

ãâ

i\.

(^

y(n)

llinh L So tlo khoi Ciiii true ciia ho loc FIR hac /,-!

So do na\' la lap hgp cac bg Ire tin hieu (/." ). bg nhan \'a bg egng. NhCrng loan
hang luon ihuirng irirc trong moi bg nhan la cae he so cua bg Ige h^. De linh duge eac
gia lri_v(/0 tir cac mau loi \'ao x{n} ihi cac mau Ian Urgt phai qua eac bg Ire, bg nhan va
bg egng. WVi bg Igc I'lR eo do dai la /. ihi phai sau L phep nhan va L ~ 1 phep egng ihi
niai tinh du'oc mot gia iri eua loi ra.
Nlur \ a \ . bg Igc FIR c6 cfiu true nhu tren eo nhuge diem la kha nang dap ung

cham. cac mau loi ra khong dvxge lien luc ma sau mgl khoang thai gian tinh loan xon"
cac piicp ntian \a phep egng moi duge xual ra.
i^o loc MR nlnr trcn L:OI la Ao loc TIR iruc iicj? (dirreel FIR filler). Mot bien iht^
kliac L'oi la IOL' I-IR ehiivcn vi (U-ansposcd MR Jlller) du'oe de xual iheo so- d6 Hinh 2
\oi cac \ uioni: ,sau: Irao doi i:iua cac dau \ ao \a ra. daii huang IUOIILI cha\- tin hieu.


Thuong bg loc FIR chuyen vi hay duge dung trong Idii thiel ke eae bg Igc can eo
thong lugng cao (high thi'oughput) vi trong khi do khong can them mot thanh ghi dieh
eho x(n) va ciing khong can phai them mot tang duong ong eho nlianh long eua eac
tieh ma van dat duge toe do cao [1]. Trong nhung bg Ige nhu vay thi viee ap dung kien
true duong ong voi cac bg chol, thanh ghi dieh la can thiel de khac phue nhuge diem
cua bg Igc FIR true tiep. Viee nghien cuu tang toe eac bg egng va bg nhan bang cac ky
thuat duong ong hay xu ly song song eung rat quan trgng.
x(n)

^(X)

/7,2 ^ ( X )

"1 - ^

h2

ho - K x )

Hinh 2. Bo loc FIR bac L-I voi can true chuyen vj.

2.5. Bo loc thich nghi
• Bg loc thich nghi: Cae bg Ige LTI duge thiet ke eho nhung ung dung trong do

eae he so Ige ''toi uu" khong doi theo thai gian. Tuy nliien eo nhung truang hgp nhu
xu ly lieng noi, xu ly eac thong tin trong radar, sonar hoae xu ly eae tin hieu y sinh,
v.v...can CO eae bg Ige eo he so Ige "toi uu" eo the dieu ehinh duge theo thai gian liiy
thuge su bien doi eua tin hieu vao. Neu eae tham so tin hieu vao thay doi eham so vai
tan so lay mau tin hieu thi la eo the linh duge eae he so Ige tot ban va eo the dieu chinh
duge mot bg Igc thieh hgp ban. Bg Ige kieu nhu vay ggi la bg Igc thich nghi (adaptive
filter) [8].
1 il{n)

-v(//)
Input signal
(lefercnce)

/
Bo loc FIR
CO he s6 /?K
bien 66\

Desired 5igiial

.K.)

/
Giai thuat thich nghi

output ~
signal

^

error
signal

ein)=(lin) --y (")

Hinh 3. Bo loc so thich nghi dung loi FIR.

Do CO tinh on dinh nen bg ige FIR (chi eo eae diem khong) thuang hay dirge su
dung lam bg Ige thich nghi hon bg Igc IIR (eo ea eac dit§m kliong va diem cue). Sa dd

11


khoi mot bg Igc thich nghi dung mach Igc FIR eo he so bien doi duge bieu dien nlur
hinh 3.
Cac thong so cua bg Ige nay nhu sau:
-

.v(n) la mau tin hieu vao thu n. Thuang duge ggi la "input hay reference

-

signal".
y(n) la mau tin hieu ra sau bg Igc. Thuang duge ggi la "output signal".

-

d{n) la mau tin hieu la long eua tin hieu saeh can phal hien va can nhieu.
fhu'ang duge ggi la ""desired signal"'.
e(n) - d{n) - v(n) la mau tin hieu sai lech, fhuang duge ggi la "error signal".

Muc dieh cua he thong la phai dieu chinh eac he so bg Ige FIR sao eho lu tin hieu
vao x{n) CO duge tin hieu ra v(/;) nhu the nao do dc eong suat eua tin hieu sai leeh e{n)
^ d{n) ~ y{n) dat circ lieu.
(iiai ihual thong dung nhal de dieu chmh thieh nghi eae he so Igc la "binh phuong
trung binh eiic lieu LNLS (Leasl Mean Square) se duge su dimg trong thue nghiem.
• Dieu ehi/ih cue he sf) Icjc qua danh gia toi uu Wiener [2]
Lho bg Igc FIR \ai cac he so eo the dieu chinh du'ge !h(k). 0 < k < L-1}. Cigi
!\{n)| la chuoi eac mau tin hieu \ ao bg loc. Tin hieu ra cua bg loc \\{n)] bang:
y(n)-^ Y^l}[k)x{n-k),

\ai n - 0. 1

M

(4)

; -(I

Gia thiel eo chuoi mong muon \d{ii)] eo the so sanh duge vai loi ra bg Ige FIR.
Khi do CO the tao nen mot chuoi sai lech \e{n)\ nhu sau: e[n)^d[n)~

y{n)

(5)

Cac he so bg Igc se duge ehgn \ oi dieu kien long cae sai lech binh phuong L la
ciiv lieu |3]. Nhir\ay c6:

/-Z'-(") = I d(u)-Y^h[k)x(n-k)

(6)

-

(7)

\^d--{}})-2Y^li{k)rjk)-^Y.Y.^^^^'^^^^^'»\..ik-l)

I lOMiz do:
\'\\.[k)\ la chuoi Urong quan chco j^iua chum ra \d{n)\ \ a e h u o i \ a o
I lA ) - ^ d[}])x[)} k I.

\o\ 0 •__ A- £: A ^ I

\\{n)'
(H)


(rxx(^) la chuoi tu tuang quan cua {x{n)}:
M

r^^(k)^Y.^{n)x{n

+ k),

vai

Q

(9)

/i=0

Tong E nay la ham bac hai cua cae he so Ige FIR se cue lieu khi dao ham rieng
phan theo eac he so Igc duge dat bang kliong:
^^^^ =0
dh{in)

voi

0
(10)

/.-I

va do do:

^ h(k)r^^ (k - m) - /;,, (m)

vai

0
(II)

k=0

Day la he phuong trinh luycn linh tim cac he so Ige toi uu.

Co the viet cac chuoi tren dual dang vee to trong do:
Td,^ = E{d(n) x(n)} la ma Iran tuang quan cheo va R^^ = E{( x(n) x (n) )} la ma tran
tu tuang quan c6 {L x L) phan tu.
Khi do (10) CO the viet ggn lai thanh phuong trinh danh gia toi uu Wiener:
//opi-^,,"'/'u,

(12)

Dieu can thiel de eo the giai duge he phuong trinh tren la R^^^' phai ton lai. Dieu
nay eo duge khi R^^-^ khae khong. Co the chi ra rang neu tin hieu la ehuan dung thi ma
Iran 7^^^"' ton tai. C-6-the clit ra rang neu tin hieu la chuan dung thi ma Iran 7?^:^" ton tai.
Phuong trinh bieu dien sai leeh danh gia loi uu Ira thanh:
Eopi ^ H{t/(/7)-/;^optA'(^0}'
= E{d{n)f

- 2 //^ptr^x + //^,,n R^^ /'opi

^ '•dd(O) -//^,p, /\K

(13)

vai /"dd(0) ^ o d la phuong sai eua d.

2.6. Kien true Systolic eho cac bo loe
2.6.1. Cau true Systohc Array
Hien nay eo nhieu ung dung, dae biet la eac ung dung thai gian thuc, doi hoi phai
CO toe do xu ly du nhanh. De giai quyet van de nay, mot so ky thuat nham nang eao loc
do xu ly du lieu da duge nghien euu phat trien, va ky thuat systolic array la mgl trong
so do.
Systolic Array la su slip xep cc'ic hg xu ly thanh can (rue mang, vc) du lieu dime

truyen dong thai giuxi nhung mang Idn can nhau. Thong ihimng, nhung du lieu khac
nhau thi chuyen dong theo cac hux'xng khc'ic nhau. Tai moi budc, moi ho xu ly nhan du

13


lieu lu m6t hay nhik bo xu ly km can. xu ly ehung vc) a buac tiC'p theo, du lieu dau ra
duge chuyen sang bg xu ly khac.
H.T.Kung va Charles Leiserson k\n ddu lien xual ban lai lieu viet ve syslolie
array \ao nam 1978, dong thai dai ten e^u true nay nhu vay can cu vao boat dong cua
no tuang lu nhu nhip lam thu eua tim va eae dong maeh (rhythmical systolic of the
heart and arteries) trong he tuan hoan. a do mau duge bo'm ve phia truae tu dong mach
nay loi dong mach tiep theo ben canh [3]. Cdu true Systohc Array thich hgp eho
nhung ung dung su dung cac he th6ng VLSI nhu FPGA. Mgl ky thuat thong dung
trong cAu ink Syslolie la xu li dimvg dug, trong do vice linh loan duge ehia ihanh cae
eong doan nho lion, cac eong doan nay c6 the duge chi dinh lai mgl chuoi cae phan tu
xu li d5ng ihoi khac nhau theo each nao do nham dat duge toe do eao. Duang ong
trong tinh huong nay giong nhu' nigl day truyen lap rap 6 to hien ctai, trong do nhiem
\ u Ifip rap duge phan thanh mgl tap cac eong doan lap rap nho ma moi eong doan do
duge thue hien dong ihoi bai eac eong nhan 6 cac tram khae nhau tren da>' chuyen.
Duong ong lu> c6 lam eho he thong mat mgl thai gian Ire, nhung mgl khi no da duge
lam da\ thi moi 6 to se duge xuat ra chi trong it phut. Vai ni6 hinh nay thi ro rang
khonu the dc tat ca cac c6nCo ihe coi Systolic Array la mot dang eau true xu ly duang ong hoae song song
dac biet chua eac dan vi xu ly dfr lieu ggi tat la PL (processing element). Cae khoi xu
ly na\' duge sap xep thanh mgl mang (aiay). PI', tuang tu nhu CPU nhung no khong
nhal thiel phai co bg dem chuong trinh. fung PL nhu la mgl trigger truyen thong bai
su luan ehu>en du lieu tu PL na\' den cae PL Ian can. Thong thuang, nhung du lieu
khae nhau ihi se luan chuyen theo cae huong khae nhau. Cae PE eo kha nang luu Irir
\a xu ly du lieu doc lap vai nhau. Cac bg xu ly nay eo the eo mot vai ihanh ghi va

khoi tinh so hgc-logic ALU. Moi PE sau khi xu ly du lieu xong se ehia se du lieu eho
cac PL Ian can, Hinh 4 duai da\' mo la kien true systolic array mgl chieu va nhieu
ehieu \ eVi dir lieu chuyen dong theo mot hudng hay nhit!u hu-ong.

Hata
aata

/^ Host N
Vx _Processor
j ^y

L-^l PE [-•I PE |-^| PE

[-K|

result,.
PE

- •

PF

results

Minh -1. Luon" i\{\ lieu t r o u " eau true s\stoIic a r r a y .


Hinh 5 mo ta kien true systolic array hai chieu, du lieu chuyen dong hai huang
theo chieu cua mui ten qua cac PE. Du lieu ra cung theo hai hu'ong.
Cau true systolic array c6 nhijng dac diem:

- Day la cau true xu ly song song.
- Rat nhieu bg xu ly du lieu duge ket noi vai nhau.
- Khong giong nhu nhieu dang xu ly song song, eau true systolic array khong bj
giam toe do khi eo su chuyen tiep.
- Cac nhan xu ly (cells) hay bg xu ly (processor) PE linh loan xu ly dij" lieu, luu
tru du lieu mot each doc lap vai nliau. Moi bg XLY ly eo the eo mgl vai thanh ghi
va khoi ALU. Moi bg xu ly ehia se thong tin eho eac khoi xu ly Ian can sau khi
xu ly thong tin nhan duge
Luong du' lieu vao

I

•nj

lieu

>

-•

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1

PE

PE

PE

1
PE

"

PE

T

T

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-•

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-•

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Y

i

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''

-•

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> ^ H ^ .b
D6UC

jong

% ^•^^

1

eu Tc

t

>'

'

1

i

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1
^

Lu6ng dO' lieu ra

Hinh 5. Cau true systolic array hai ehieu.

2.6.2. Cau true Systohc duong ong va song song
Thue hien eau tri'ie Systolic Array duang ong la viee ehen eae bg ch6t \ao duong
du lieu, dieu do eho phep lam giam do dai duang dae trung (critical path), dan loi tang
duge toe do xung nhip dong ho va nhu vay, tuc la tang duge loc do I^y mau tin hieu.
Keo theo do eiang giam duge eong suat tieu tan trong mach. Voi eau true song song, do
dung song song eae cau true phan eung nen tuy khong giam duxyng dac trung. khong eo
bg chol nhu'ng \'an tang duge loc do lay mau.


Xct viee thue hien chuoi du' lieu yinD) = Yj^i{k)x{nD-kD)

eua mot bg Ige FIR

k=0

nhu hinh 6 va gia su moi phep egng va phep nhan duge thue hien trong klioang thai
gian tuang ung i^ va 1^ . Moi phan tu xir ly PE nam trong duang eham eham. Mot bg
Ire duge them vao goe tren ben phai hinh va mot bg egng vai 0 duge them vao goc
duai ben trai hinh chi nham cai ihien tinh can doi eua sa do. Co 2 ban che eua so do
nay. Thu nhal la c6 hai loai phan tu khac biet: mgl loai truyen tin hieu vao eua no tai
phan lu ben eanh va thue hien phep nhan va loai khae ihire hien phep egng. Thu hai la
toe do xu ly (loc do lay man cue dai) phii thuge vao phan eung bj han che. Toe do nay
ly le nghich \oi ihoi gian thirc hien tat ea eac boat dong linh loan so hge giira hai mau
lien tiep. I rong khi cac phep nhan o' day eo the duge lien hanh dong thai thi L phep
egng phai du'gc thuc hien Ian lugt ke tiep nhau lu trai qua phai. Do vay doi hoi thai
gian xu ly la (T,„ + /.i,, ) giay. Trong thire le so man L Ian se dan den thoi gian nay rat
Ion.
1

x(nD) \

; 1

n
U
'

1

. '
* 1
'

D

1
1
1

1*
1

ML-1)

<S>

y(nD)

Hinh 6. So do thuc hien ho loc FIR bae A.

Nhuge diem thu nhat eo the duge giam bat bfmg each kk hgp vao moi phan tu
nhan \o\ phfin tu egng ben canh. T6c do xu ly trong ck\ true tren eo the duge tang len
khi su dung cac bg egng nhanh. Mgl each tic'p can khae la viee xu ly d6ng thai qua viee
ap dung ky ihual duang 6ng. Xem xet kha nang them vao cac bg tre giua cae PE nhu
hinh 7 sau :
x(nD) ;

]
D

/'(O)

1

u

D

[ ^

D "*^ • •-*D

\
''(1

-o

y(nD
H i n h 7. T h u c hien can t r u e Systolic d u o n g 6ng bo loc M R .

1 A


Boi vi dinh va day ctia moi phan tu xu ly duge tre them bai eung mgl lugng nen 2
tin bieu khong bi djeh tuang doi so voi cai khac va boat dong eua cau true khong bi
pha buy. Tac dong duy nhat chi la : loi ra dau lien se bi tre di L.D giay do eo L bg tre
giCra cac phan tu xu ly.

y^ {nD) = Y, h(k) x(nD -kD- LD)
tuc la :

(14)

y^ {^D) = y{nD - LD) vai y{nD) la mau ra cua can true ban dau.

Thai gian tre LD ggi la do tre ban dcm (latency) cua he thong. Neu chi eo phep
nhan va phep egng duge su dung thi bg Ige eo toe do xu ly la bang \l(Xn\ + '^•^)- Nhu
vay, thue te toe do xu ly khong bi giam khi do dai L eua bg Ige tang. Cae bg tre eo the
dirge thiet ke ghep vao eae phan tu xu ly PE nhu hinh 8 sau.

Hinh 8. Phan tii' xii' ly dien hinh.

Can true song song ve eo ban can phai eo 2 khoi bien doi noi tiep-song song va
song song-noi tiep nhu so do khoi Hinh 9.

Ckx;*. iVru J-TM
Jinmpk Pcricsi
T/-1

CiMivcrtL^f

)i(JS^+\l nl4k :) x(^ U l )

^{•W)

yA^)
eWV fVncJ=T

Ml MO
Svslcjn

>(4k+l>

I'.mllrl toScnnl

>M1J

y.;4k.:)

)(-lUA)

Ciinveacr

Hinh 9. Nguyen lac ciia can true Systolic song song.
Trong do khoi MIMO System ciia mot bg Ige duge thiet ke nhu tren Hinh 10.

DAIHOCOUOCGIAHANOI^
TRUNG TAM THON&hNJH^^

0GO6O0GC0iv)


-X

,

lX;^*^

—^-fi^

Ckr

r(t)—^^'"'*^'

T

R
M3l>'2)

^-c

I

T

I

Hinh 10. So a 6 e a u tnic son*? song eho bo loe F H t 3 tap.

v(^7) = ax{n) + /xv(/7 - 1) + cx{n - 2)
yOk) - a.xOk) + lx\(3k - 1) + ex{3k - 2)
.v(3^ + 1) = ^/A-(3^ + 1) + hx{3k) + r.T(3A - 1)
y{3k + 2) = av(3l + 2) + hx{3k + 1) + CA-(3^)
Chu k\ la\ man tin hieu

T

=- T

> -ir

-K2r )

2.7. VLSI, ASIC, FPCAva HDL

Nen eong iighic]i ban dan da lien trien tir cac IC dau lien vao khoang nhung nam
dau cua thap nicn 1970 \a da truang thanh nhanh chong lu do. Do tieh hgp eua eae IC
nga> eang tang, tir cac IC eo do lich hgp ea nho SSI (small-scale integration) chi eo vai
chue transistor roi den cac IC eo do tieh hgp ea trung binh MSI (medium-scale
inlcuralion) roi eac IC c6 do lich hgp ca Ion LSI (large-scale integration) da tieh hgp
nhicu chue nang logic Ion hon, chang ban eik bg \'i xu ly dau lien, \'ao trong mot chip.
Hicn na\ eae IC ed da lich hgp ea rat Ion VLSI (very-large-scale integration) da eung
cap eac hg \i \ir ly 64-bil. bo sung bg nho iruy cap nhanh (cache memory) va eae dan
V! so hgc dau eham dgng (lloaling-poinl arithmetic unit) tren hang chue Iricu transistor
chi iren nigl nueng silie.
\ 01 su ra doi eua \'l SI \ ao nhung nam 80. \ ice thiet ke mgl IC theo yen cau
hoae dap uni: nhu cau cua khach hang eho mgl he ihdng hoae ung dung eu the b^U dau
eluiiu: lo loi leii si) \ oi \ ice sir dune eae IC chuan. Vice thiet ke he thonu vi dien lu Ira

18


thanh van de xac dinh cae chue nang ma ta eo the thue hien, bang each sir dung cac IC
chuan va ke den thue hien cac chue nang logic con lai bang mot hoae nhieu custom IC
(IC do khach hang dat lam, tuy thuge vao khach hang). Nhu vay, VLSI lam eho ta eo
kha nang xay dung mot he thong tu mot so nho ban cae thanh phan bang each ket hgp
nhieu IC chuan trong mot vai custom IC. Viee thiet ke mot he thong vi dien lu voi vai
IC eho phep ta giam gia thanh va cai lien do tin cay.
Khi eae loai custom IC khac nhau bat dau ma ra eho eae loai ung dung khae nliau
duge ggi la eac mgch tieh hgp dung eho ung dung cu the, viet tat la ASIC
(applicatian-speeific integrated chip).
2.7.1. Cac loai ASIC
ASIC duge phan ehia thanh ba loai chinh: full-custom

ASIC, bao gom nhicu (eo

the tat ea) le bao logic (logic cell) va tat ea eae lop mat na theo yen eau eua khach
hang; semicustom ASIC, bao gom cae cell logic duge thiet ke truae va mgl so mat na
tuy thuge khach hang va ASIC lap trinh duge (programmable ASIC), bao gom eae cell
logic duge thiet ke trirae va khong eo lop mat na nao liiy thuge khach hang.
• Ccie full-custom

ASIC

Irong mgl fuILeuslom ASIC, nguoi ky su thiel ke mgl so hoae tat ea eae cell
logic, cae mach hoae layout (so" do bo tri) mgl each eu the eho mot ASIC. Phuong
phap nay chi eo y nghTa neu Idiong san eo eae thu vien cell hien hanh thieh hgp, dieu
nay eo the do cae thu vien cell hien hanh khong du nhanh hoae eae cell logic khong du
nho hoae tieu thu nhieu eong suat. Ngay eang it eac full-custom IC duge thiel ke do eo
nhieu van de voi cae phan dae biet nay eua ASIC. Tuy nhien eo mgl hg thanh vien eua
hg nay dang Ian manh, do la ASIC hon hgp tuang tu - so.
• Ctic semi-custom

ASIC

Bao gom 2 loai: eae ASIC dua tren cell ehuan (standard cell-based ASIC) va eac
ASIC dua Iren dai eong (gale array-based ASIC)
Cac ASIC dua tren cell chuan ha)' IC dua tren cell CBIC (cell-based IC) su dung
eae cell logic duge thiet ke truae (thi du eac eong AND. eae eong OR, eac bg ghep
kenh va eac flipflop) ggi la cae cell ehuan.
Cc'ic ASIC dua tren dai eong. Trong mot ASIC dua tren dai eong (gale aiTaybased ASIC), eae transistor duge xac dinh truae tren mieng silie. Bieu do xac dinh
truae eae Iransislor tren mgl dai eong la dai nen (base array), va thanh phan nho nhat
duge tao ban sao de thuc hien dai nen la cell nen (base cell). Chi eo vai \6p kirn loai

tren dinh. eae lap nay xac dinh lien k^t n6i giua eae transistor, duge xac djnb bai
nguai ihiCt k8 bring each su dung eac mat na tuy thuge vao khach hang.
• die ASIC khci trinh
Bao g6m 2 loai: eae chip logic kha trinh PLD (programmable logic device) va
mang eong kha trinh lai cCm hinh FPGA (field-programmable gate array).
Cae chip logic kha trinh PLD : la cae IC chufm eo sin va duge ban vai so lugng
kVn. Tii>- nhien, cac PLD eo th^ duge eau hinh hoae duge lap trinh de tao ra phan tuy
thuge khach hang eho mgl ung dung eu the.
PLD bao u6m mgl s6 loai nhir ROM. EPROM. EEPROM. UVPROM. ROM eo
M dat tren mgl ASIC bat ky - ROM mat na lap trinh duge (masked-programmed
ROM), cac linh kien logic dai kha trinh PAL (programmable aray logic), dai logic khci
trinh PL A (programmable logic array)
Mang cdng lap trinh duoc FPCiA ; FPGA ihuang Ion ban va phue tap ban PLD
nen doi khi eon duge ggi la PLD phue tap CPLD (complex PLD). Cae FPGA la dang
phal Iricn rat nhanh. ihay tlic hg vi mach TTL Irong cac he thong vi dien tu.
Duoi day di sau \ao khao sat eac chip FPGA
2.7.2.

FPCiA.

• Can tao ciia FPCiA: duge dua ra gioi thieu Ian dau lien giCra nhung nam 1980
boi Xilinx. f PCiA la \ iet lat cua cum lir Field Programmable

Gale Arrays - Mang

cdng kha trinh. FPG/V bat nguon tir sir phal trien cua thiet bi logic kha trinh phue tap
CI*LI) (Complex Programmable Dc\ ices) eo tir giua nhung nam 80 eua the ki truae.
C~PLI) \a 1 PCiA deu chua mgl so lugng Ion cac thanh phan logic kha trinh eo lien
tiuan den nhau. Trong khi mat do eong logic trong CPLD chi eo vai nghin den \'ai chue
nghin ihi trong I-PGA eo khoang Ur \ai chue nghin den \'ai Irieu eong. Tu "Field"

irong ihual ngu FPGA bao ham y nghla \e kha nang lai eau hinh lai phan eung eho
i'PCi.A boi nguo'i dimg cuoi lenduscr) nga\ lai noi su dung ma khong can mang Ira lai
eho nha san xual eau hinh. Do chinh la mot diem manh eua FPGA eung nhu eae thiet
hi PLD khae.
1 P(i.\ ta mgl maeh lich hgp chua rat nhieu te bao logic (logic cell), eo tli6 xem
nhu la eae Inih kicn chuan. Cac logic cell doc lap voi nhau trong eae ihiel k6 mang linh
ca nhan. Cae ceil laeh hiel \oi nhau dv\ge kct noi trong voi nhau btn ma Iran da\' noi va
ehii\en maeh, khi duct kc cac ham logic don gian eho moi cell, nguo'i dung thuc hien
baiiL'. each dicu khicn eae chii\cn mach Irong ma Iran kct noi trong. Mgl mang eae cell

20


va cac ket noi tao nen nhung khoi ket noi eo ban eho maeh. Mot thiel ke phue tap la su
ket noi cua cac khoi tren, tao nen mach mong muon.
Nhu vay, mot each tong quat, cau true eua FPGA bao gom 3 thanh phan:
Cac khoi logic c6 the tai cau hinh CLB ("Configuable Logic Blocks" hay
"Logic Cells") la nai thuc hien eac tinli loan, luu tru thong tin, luS la thanh
phan quan trgng nhat trong FPGA. So logic cell thay doi theo lung hg linh
kien. To hgp logic eua moi cell duge thue hien bang nigl bang Ira dir lieu
LUT (look-up table) hoae la to hgp eua nhieu eong AND.
-

Ma tran lien ket noi (Programmable Interconnect Matrix): la ma Iran
chuyen maeh hang va cot thuc hien ket noi ben Irong giua eac logic cell vai
nhau, va giua khoi I/O va logic cell.
Cac khoi vao/ra (I/O Blocks): Cung cap eae giao tiep vai ben ngoai.

Mot diem khae biet can ehu y giCra FPCiA va CPLD la su eo mat eiia eae he nhung
trong ban bet cae san pham FPGA. Su khae biet quan trgng la eo nhieu FPGA hien dai

ho trg day du hoae nigl phan kha nang lai eau hinh trong he thong, eho phep thiet ke
CO the duge thay doi cung nhu nang cap he thong hoae eho viee can hinh dong Ira lai
nhu la mot phan binh thuang cua he dieu hanh. Mgl vai FPGA eo kha nang cau hinh
rieng eho phep mgl phan ciia thiet bi duge lap trinh lai trong khi nhung phan khac van
boat dong binh thuong.

D D D
Hinh U.

Cau true tong quat ciia FPGA.

Xu huang phal trien gan day la viee ket hgp eae khoi logic, eac lien kct trong
FPGA truyen thong vai vi xu ly nhung va nhung ngoai vi eo lien quan de tao nen mgl
"he thong tren mgl chip kha trinh" hoan Ihien. Ta eo the tim thay nhung thiet k^ do
trong mot so thiet bi nhu Xilinx Virtex-Il PRO va Virtex-4 eo chua mgl hoae nhi6u
loi xu ly nliung Power PC trong pham vi ket eau logic eua FPGA. Nhieu FPGA hien
dai CO kha nang lap trinh lai trong khi dang boat dong, va dieu nay rat quan trgng eho y
tuang cua viee tinh loan tai eau hinh hoae he ihong lai efiu hinh de tir eau hinh lai phii


hgp vai boat dong s^p lai. Nhung eong cu FPGA hien nay ehua hoan loan ho trg day
du eho phuang thue na}'. Hien na\- FPGA khong eo eau true dang bat dau xuat hien. Vi
xir ly cau hinh phAn mam nhu Stretch S5000 chgn huang lien den he lai bang each
cung eip mgl mang eae loi xu ly \ a FPGA giong nhu loi kha trinh tren eung mot chip.
Cac thiet bi khac cung cap cac mang ciia eae d6i lugng kha trinh cap eao nam giu'a
khoi logic cua FPGA \ a eac xu ly phue tap.
• Cong nghe tao lien ket noi trcn FPCiA
Su dung 1-P(]A eho cac ung dung thuc chat la vice lap trinh thiet ke eae lien kct
noi trcn do liiy \'ao bai toan ung dung cu the. Cong nghe lap trinh eo the \'Tnh euu hoae
khong. la khong the pha bo \ iec lap trinh \Tnh eiYu Irong eae FPCiA lap trinh duge

mgl Ian OTP (one-lime programmable). Cae chip xoa duge va lap trinh lai duge
(reprogrammable and erasable chip) c6 the dirge su dung lai nhieu Ian. Co mgl so eong
nghe lap trinh khac nhau:
Cong nghe phan can chi
-

Cong nghe RAM linh (SRAM)

-

CcMig nghe LPROM \'a Ld-TROM

• I'n*:; dunj; FPCiA eho cac can true Systolic.
Cau Iriie Syslolie doi hoi mgl lugng tai nguyen phan eung Ion cung nhu ky thuat
noi SO" do phue lap \ai mgl nguon xung nhip du}' nhal. Can cu vao eae dac diem eua
chip FPCJA ke IrcMi thay rang vice su dung eac chip nay eho viee nghien euu phal trien
cac mau ihu (protoupe) Irong ung dung loai na>' la rat phii hgp. Do la viee thiet ke xay
dung cac bg Igc dc doi ehung cac phuong phap xu ly: bg Igc FIR true tiep, bg Ige FIR
CO cau true Systolic duong ong. song song, bg Ige Fll^ thich nghi vai eae giai thuat
khae nhau.

2.8. Ngon ngfr VHDL
Ban chat eua \'iec thiet ke cae mach dien tu s6 Iren eae chip FPGA la phal Ui6n
cae chucmg irinh phAn mC-m mo la mach de tao cae hen kk n6i eho hang chue ngan,
tham chi hang iricu eong logic. Cae chuong trinh phfin m^m hien nay dua tren mot vai
ngon ngCr lap u-inh. irong do pho hicn la ngon ngu VIIDL.
2.S.I. (ii(Vi thieu ii<;on nofr lap trinh \Til)L
MIDI (\-eiy hiL;h speed integrated circuit Hardware Description Language) la
iiLion iiLiu nio ta phan eunu eho cac mach lich hgp loc do ral eao. dirge phat trien eho

chuong trinh VHSIC cua Bg Quoe Phong My. Muc tieu cua viee phat trien VFIDL la
CO duge mot ngon ngir mo phong phan cung lieu chuan va thong nhat eho phep thu
nghiem eac be thong so nhanh hon cung nliu eho phep de dang dua cac he thong do
vao ung dimg trong thuc te. Ngon ngu VHDL duge ba eong ty Intermeties, IBM va
Texas Instruments bat dau nghien euu phat trien vao thang 7 nam 1983. Phien ban dau
tien duge eong bo vao thang 8 - 1985. Vao nam 1986, VFIDL da duge de nghi la mgl
chuan cua IEEE. Sau nhieu Ian xem xet va sua doi, den thang 12 nam 1987, VHDL
duge chap nhan la ehuan IEEE 1076.
2.8.2. Cau true mot nio huih he thong nio ta bang VHDL
Thong thuang mgl mo hinh VHDL bao gom ba phan: thuc the (Entity), kien
true (Architecture) va eae cau hinh (Configuration). Doi khi la su diing eae goi
(Packages) va mo hinh kiem tra boat dong eua he thong (Testbench).
• Thuc the (Entity)
Tat ca cac Ihiet ke deu duge bieu dien duai dang cac thue the. Mot thue the la
mot khoi xac dinh san eo ban nhal trom' mot thiet ke. Muc eao nhat eiia thiet ke la
thuc the mue dinh (lop-level entity). Neu thiet kc eo thu bae, mo la niue dinh (toplevel description) se eo eae mo la muc thap ban ehua ben trong. Nhung mo la muc
thap hon nay se la eae thue the mue thap hon ehua trong mo ta thuc the muc dinh.
Thue chat eua vice khai bao thue the ehinh la khai bao giao dien eiia he thong vai
ben ngoai. La eo the eo tat ca cae thong tin de ket noi maeh vao maeh khae hoae thiet
ke lae nhan dau vao phue vu eho mue dieh thu nghiem. Tuy nhien boat dong that sir
eua maeh khong nam o phan khai bao nay.
• Kien triic

(Architecture)

Moi mgl khai bao thuc the deu phai di kem vai it nhat mgl kien true tuang ung.
VHDL eho phep tao ra hon mot kien true eho mgl thuc the. Phan Idiai bao kien true eo
the bao gom eac khai bao ve cac tin hieu ben trong, eae phan tu ben trong he thong,
hay cae ham va thu tuc mo ta boat dong eua he thong. Ten eua kien true la nhan duge

dat tuy theo nguai su dung.
Co hai each mo ta kien true eua mot phan tir (hoae he thong) do la mo la a muc
hanh vi (Behavioural deseriplion) hay nio la a mire cau triic (Structural description).
Tuy nhien nigl he thong eo the bao gom ea mo la a mire hanh vi va nio ta a mire cau
triie.
Mo tii 6' mii-e hanh vi (Behavioural description): mo ta cac boat dong ciia he thong
(he thong dap irng voi eac tin hieu vao nhu the nao \'a dua ra kct qua gi ra dau ra) duai

23


dang cae cau triic ngon ngu lap trinh bac eao. Cau triie do eo the la PROCESS, WAII,
IF, CASE, FOR-LOOP...
Mo ta 0" mijc cau trijc (Structural description): Mo hinh eau triie ciia mot phan til"
(hoae he th6ng) eo th^ bao gdm nhik\ cap e£u triic bat dau tir mot eong logic don gian
den xa> dung mo la eho mgl he lh6ng hoan ihien. 1'hue chat eiia vice mo ta a mire eau
Inic la mo ta cac phan lii eon ben Irong he th6ng va su kel noi eiia eae phan tir eon do.
Nhu \ai vi du mo la mo hinh edu Inic mot nip-Hop RS gom hai eong NAND eo the
mo ta eong NAND duge dinh nghTa tuang tu nhu vi du vai eong NOT, sau do mo ta
sa do moe noi eac phan lu NAND tao thanh triga RS.
• Cdu hinh

(Configuration)

Mgl phat bieu eau hinh duge sir dung de gan ket mgl the hien thanh phan
(component instance) \ai mot cap ihue thue hien-kien triic. Mgl can hinh c6 the duge
khao sal giong nhir mot danh saeh cac phan (parts list) eiia mgl ihicl ke. Cau hinh mo
ta hanh \ i nao sir dung eho moi thuc the, giong nhir danh sach cac phan nio la phan
nao su dung eho moi phan trong thiet ke. Khi eau hinh eiia mgl ket hgp thue ihe-kien
Iriic duge djeh trong ihu \ icn. mgl doi lugng kha mo phong duge tao ra.

• Goi (Package)
Mgl Package la mgl lap cae chuong trinh con va eae kieu du lieu pho bien duge
su dung trong mgl ihiet ke. Muc dieh ca ban eiia Package la goi ggn eae phan nho eo
the dirge su dung trong nhieu thiet ke. Package la mgl bien phap thuong dimg d^ luu
tru thong tin eo ihe dirge su dung Irong nhieu Entity. Moi quan he trong Package eho
phep du lieu c6 the dirge tham ehieu boi nhung Entity khiie. Vi the du lieu eo th^ duge
ehia se.
•

Testbench
1 estbcnch duge su dung de kiem tra mgl ihia kt. Testbench eho phep nguai thiet

ke kicm tra chue nang cua thiet kc a moi birae trong he phuong phap dua tren long
hgp VHDL. Khi nguai ihiel ke thue hicn mgl thay doi nho de sua ehua mgl loi, thay
doi na\ CO Ihe dirge kiem tra de dam bao rang khong anh huong d^n eae phan khac cua
thiOt kc. Cae phien ban moi eua thiCn k^ ea ihe duge kiem tra di^ia vao eik kk qua da
hicl de xac nhan linh Uro'ng thich.
I esibeneh o' nuie cao trong he lh6ng ihir bac eua thiet ke.

"•4


2.9. Thuc nghiem: Thiet ke, mo phong va thuc hien cac bo loc
FIR va bo loc thich nghi c6 can true Systolic trcn FPGA
De tai sir dung kit XtremeDSP Virtex-II Pro eiia Xilinx de ti§n hanh thuc nghiem
phat trien cac bg loc so sir dung kien trite Systolic Array bae thSp. Cae chuong trinh
phan mem nbimg duge phat trien dua tren ngon ngu VFIDL va Mallab.
2.9.L Cau hinh phan cung Kit Xtrcme DSP Vertex II - Pro
• Cau hinh ehung :

Phan eirng eiia kit Virtex-II Pro bao gom:

-

FPGA Spartan-II dimg de tao giao tiep PCI hoae USB.

-

2 LED trang thai bien thi 3 mau: cam, do, vang.
Giac cam eho maeh nap JTAG.

-

2 kenh ADC doe lap (ADC 14 bit) voi t6e do lay mau toi da la lOSMhz.

-

2 kenli DAC doc lap (DAC 14 bit) vai t6c do bien d6i toi da ia 160Mhz.

-

2 ranh ZBT SRAM doe lap vai bg nha 512K x 32.

-

FPGA Virtex-II XC2V80-4CS144 de tao clock,

-

FPGA Virtex-II pro XC2VP30-4FF1152 la FPGA ehinh eho nguai sir dung.

Co duang ket noi vai clock ngoai.
Co thaeh anh 65MHz trong mach.
Tong the \ e kit Virtex-II Pro duge mo la nhu hinh 12.
Cae bg phan ehinh la bg chuyen doi tuang tu-s6 (ADC), bg chuyen doi s6-liiang

lu (DAC), bg tao xung ddng hd (FPGA Virtex-II XC2V80-4CS144) ghep n6i \ai
Virlex II Pro.

A i X I Ml. X li ,.i.t
t"<[-r,s,.l M(:X (_i..ci. I

Hinh 12. Mat trcn ciia Kit Virtc\-II pro.

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