Tài liệu Logic Design with VHDL doc

A
B
C
A
B
C
A
B
CA C
AND: C = A B OR: C = A + B
NOT: C = A'
Figure 1-1 Basic Gates
EXCLUSIVE OR: C = A + B
X
Y
Cin
Cout
Sum
FULL
ADDER
X Y Cin CoutSum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Figure 1-2 Full Adder
(a) Full adder module

(b) Truth Table
Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCin
Sum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin
1
1
1
1
1
1
0100 11 10
01
00
11
10
AB
CD
1
X
1
X
1
four corner terms
combine to give B' D'
C
A'BD
F =∑m(0,2,3,5,6,7,8,10,11) + ∑d(14,15)
= C + B' D' + A' BD
= (B' + C + D) (B + C + D') (A'+B')
0 0
0

0 0
4
6
7
5 13
15
14 10
12
1
3
8
9
11
2
0100 11 10
01
00
11
10
AB
CD
0
Figure 1-3 Four-Variable Karnaugh Maps
X
1
1
1
1
1
0100 11 10

01
00
11
10
AB
CD
1
1
A'C'
ACD
A'B'D'
0
1
3
2 6 14 10
7
15 11
4 12
8
5
13
9
X
Figure 1-4 Selection of Prime Implicants
F = A'C' + A'B'D' + ACD + A'BD
or
F = A'C' + A'B'D' + ACD + BCD
1
X
1

X
X
1
1
1
0100 11 10
01
00
11
10
AB
CD
E = F = 0
MS
0
= A'B' + ACD
X
X
X
X
X
X
1
X
X
0100 11 10
01
00
11
10

AB
CD
E = 0, F = 1
MS
2
= AD
X
1
1 X
X
X
X
X X
X
0100 11 10
01
00
11
10
AB
CD
E = 1, F = 0
MS
1
= A'D
1
E
E X
1
X

X
1
F
1
1
0100 11 10
01
00
11
10
AB
CD
G
Figure 1-5
Simplification Using Map-Entered Variables
G = MS + EMS + FMS
= A'B' + ACD + EA'D + FAD
0
2
1
NAND:
NOR:
C = (AB)' = A' + B'
C = (A+B)' = A'B'
C
C
C
C
A
B

A
B
A
B
A
B
Figure 1-6 NAND and NOR Gates
D
C
A
B'
G
E
F
Z
A
G'
D
C'
B'
E
F
Z
Double inversion cancels
Complemented input
cancels inversion
Figure 1-7 Conversion to NOR Gates
(a) AND-OR network
(b) Equivalent NOR-gate network
A

B
C
D
E
F
A
B'
C
D'
E'
F
Added inverter
Added inverter
A
B
C
D
E
F
Bubbles cancel
Figure 1-8
Conversion of AND-OR Network to NAND Gates
(a) AND_OR network
(b) First step in NAND conversion
(c) Completed conversion
Figure 1-9 Elimination of 1-Hazard
0 1
0
1
10

1
0
10
01
00
11
10
A
BC
C
B
A
F
A
F = AB' + BC + AC
(c) Network with hazard removed
C
E
B
A
D
F
0 1
0
1
10
1
0
10
01

00
11
10
A
BC
F = AB' + BC
1 - Hazard
(a) Network with 1-hazard
B
D
E
F
0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns
(b) Timing Chart
B'
DFF
CLK D
QQ'
D Q Q
+
0 0 0
0 1 0
1 0 1
1 1 1
Figure 1-10
Clocked D Flip-flop
with Rising-edge Trigger
Q = D
+
CK

FF
Q' Q
JK
J K Q Q
+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Figure 1-11 Clocked J-K Flip-flop
Q = JQ' + K'Q
+
FF
CLK T
QQ'
T Q Q
+
0 0 0
0 1 1
1 0 1
1 1 0
Figure 1-12 Clocked T Flip-flop
+
Q = QT' + Q'T = Q + T
S
R

P
Q
S R Q Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 –
1 1 1 –
Figure 1-13 S-R Latch
Q = S + R'Q
+
+
Latch
Q
DG
G D Q Q
+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Figure 1-14 Transparent D Latch
D

D
G
Q
Q
+
= DG + G'Q + (DQ)
Figure 1-15 Implementation of D Latch
Combinational
Network
State
Reg
Next state
Inputs (X)
Outputs (Z)
clock
State
Figure 1-16 General Model of Mealy Sequential Machine
S1
S0
S2
S5
S4
S3
S6
0/1
1/00/1
1/0
0/1
0/1
0/0,1/1

1/0
0/0,1/1
0/0,1/1
NC
NC
NC
C
C
C
t
0
t
1
t
2
t
3
PS X = 0 X = 1
NS
S0
S1
S2
S3
S4
S5
S6
S1
S3
S4
S5

S5
S0
S0
S2
S4
S4
S5
S6
S0
–
Z
X = 0 X = 1
1
1
0
0
1
0
1
0
0
1
1
0
1
–
Figure 1-17 State Graph and Table
for Code Converter
(a) Mealy state graph
(b) State Table

From Page 20
I. States which have the same next state (NS) for a given input should be given adjacent
assignments (look at the columns of the state table).
II. States which are the next states of the same state should be given adjacent assignments
(look at the rows).
III. States which have the same output for a given input should be given adjacent assignments.
I. (1,2) (3,4) (5,6) (in the X=1 column, S
1
and S
2
both have NS S
4
;
in the X=0 column, S
3
& S
4
have NS S
5
, and S
5
& S
6
have NS S
0
)
II. (1,2) (3,4) (5,6) (S
1
& S
2

are NS of S
0
; S
3
& S
4
are NS of S
1
;
and S
5
& S
6
are NS of S
4
)
III. (0,1,4,6) (2,3,5)
Figure 1-18(a)
State Assignment Map
0 1
00
01
11
10
Q1
Q2 Q3
S0
S5 S3
S6
S4

S1
S2
Figure 1-17(b) State Table Figure 1-18(b) Transition Table
NS Z Q1
:
Q2
:
Q3
:
Z
PS X=0 X=1 X=0 X=1 Q1Q2Q3 X=0 X=1 X=0 X=1
S0 S1 S2 1 0 000 100 101 1 0
S1 S3 S4 1 0 100 111 110 1 0
S2 S4 S4 0 1 101 110 110 0 1
S3 S5 S5 0 1 111 011 011 0 1
S4 S5 S6 1 0 110 011 010 1 0
S5 S0 S0 0 1 011 000 000 0 1
S6 S0 – 1 – 010 000 xxx 1 x
001 xxx xxx x x
S0 = 000, S1 = 100, S2 = 101, S3 = 111, S4 = 110, S5 = 011, S6 = 010
1
1
0
0
1 1
0
0 X
1
X
0

1
X
0
0
0100 11 10
01
00
11
10
XQ
1
Q
2
Q
3
D
1
= Q
1
+
= Q
2
'
0
1
1
1
1 1
1
1 X

1
X
0
0
X
0
0
0100 11 10
01
00
11
10
XQ
1
Q
2
Q
3
D
2
= Q
2
+
= Q
1
0
1
1
1
0 0

1
0 X
0
X
0
1
X
0
0
0100 11 10
01
00
11
10
XQ
1
Q
2
Q
3
D
3
= Q
3
+
= Q
1
Q
2
Q

3
+ X'Q
1
Q
3
' + XQ
1
'Q
2
'
1
1
1
0
0 1
1
0 X
0
X
0
0
X
1
1
0100 11 10
01
00
11
10
XQ

1
Q
2
Q
3
Z = X'Q
3
' + XQ
3
Figure 1-19
Karnaugh Maps for Figure 1-17
G5
G6
G7
Q1
Q2
Q3
Q1
Q3'
Q1'
Q2'
X
G3
G2
G1
D Q
Q'
D
Q
Q'

D Q
Q'
Z
G4
D3
Q2'
Q1
CLK
Q1
Q1'
Q2
Q2'
Q3'
Q3
X
X'
A1
A2
A3
A5
A6
X'
FF1
FF2
FF3
I1
Figure 1-20 Realization of Code Converter
1
1
0

0
1 1
0
0 X
1
X
0
1
X
0
0
0100 11 10
01
00
11
10
XQ
1
Q
2
Q
3
0
1
1
1
1 1
1
1 X
1

X
0
0
X
0
0
0100 11 10
01
00
11
10
XQ
1
Q
2
Q
3
0
1
1
1
0 0
1
0 X
0
X
0
1
X
0

0
0100 11 10
01
00
11
10
XQ
1
Q
2
Q
3
J
1
K
1
' J
1
Q
1
+
Q
2
+
Q
3
+
J
3
J

3
K
3
'
K
2
'
J
2
1
1
0
0
1 1
0
0 X
1
X
0
1
X
0
0
0100 11 10
01
00
11
10
XQ
1

Q
2
Q
3
Q
1
+
1
X
X
X
X X
X
X X
X
X
0
1
X
0
0
0100 11 10
01
00
11
10
XQ
1
Q
2

Q
3
J
1
= Q
2
'
X
0
1
1
0 0
1
1 X
0
X
X
X
X
X
X
0100 11 10
01
00
11
10
XQ
1
Q
2

Q
3
K
1
= Q
2
J
1
= Q
2
' K
1
= Q
2
J
2
= Q
1
K
2
= Q
1
'
J
3
= X'Q
1
+ XQ
1
'

K
3
= Q
1
' + Q
2
'
Figure 1-21 Derivation of J-K Input Equations
(a) Derivation using separate J-K map
(b) Derivation using the shortcut method
NRZ
NRZI
RZ
Manchester
0 1 1 1 0 0 1 0
bit sequence
1 bit
time
Figure 1-22
Coding Schemes for Serial Data Transmission
Conversion
Network
X
NRZ data
CLK2
Z
Manchester data
S
0
0

S
3
1
S
1
0
S
2
1
0
1 1
1
00
S
0
S
1
S
2
S
3
S
1
S
2
S
1
–
S
3

–
S
3
S
0
X = 0 X = 1
Next State
0
0
1
1
Present
State
Present
Output (Z)
Figure 1-23 Moore network
for NRZ-to-Manchester Conversion
(a) Conversion network
(b) State Graph
(c) State table
0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0X (NRZ)
CLOCK2
State
Z
(Manchester)
S
0
S
1
S

2
S
3
S
0
S
3
S
0
S
3
S
0
S
1
S
2
S
1
S
2
S
3
S
0
S
1
0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0
1 bit
time

1 bit
time
Figure 1-24 Timing for Moore Network