Tài liệu Synthesis Place-and-Route (SP&R) Flow Guide pptx

Synthesis Place-and-Route (SP&R)
Flow Guide
Product Version 4.0.8
May 2001
 2001 Cadence Design Systems, Inc. All rights reserved.
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Synthesis Place-and-Route (SP&R) Flow Guide
May 2001 3 Product Version 4.0.8
Contents
Preface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Other Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
About the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Using Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Using Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1
Introduction—RTL to GDSII
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overall Flow and Associated Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
Getting Started
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Logical (RTL) Design Data (Required) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Physical Design Data (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
GCF File (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Timing Library (Required) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timing Constraints (Required) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Physical Library (Required) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Layer Usages Table (Recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Run Scripts and Encapsulation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command Files—setup.tcl, library.tcl, and design.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

General Setup of PKS Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Example Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SE-PKS Compatibility Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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3
RTL Synthesis
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RTL Synthesis Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RTL Synthesis—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RTL Synthesis—Run Script (do_rtl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
do_rtl (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
RTL Synthesis—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating a Separate floor.tcl File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RTL Synthesis—Example Output Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4
Floorplanning
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Floorplanning Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Floorplanning—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Floorplanning—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power Striping Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
Synthesis, Placement, and Optimization
. . . . . . . . . . . . . . . . . . . . . . 43
SPO—Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SPO—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPO—Run Script (do_pks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
do_pks (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPO—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Running PKS Optimizations Automatically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Handling High Fanout Nets During PKS Optimization . . . . . . . . . . . . . . . . . . . . . . . . 47
6
Clock Tree Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CTPKS—Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CTPKS—Prerequisites for Generating Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CTPKS—Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CTPKS—Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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CTPKS—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CTPKS—Run Script (do_ctpks) Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
do_ctpks (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
do_ctpks (Example2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CTPKS—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7
Post Clock Tree Optimization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Post-CTPKS Optimization—Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Post-CTPKS Optimization—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Post-CTPKS Optimization—Run Script (do_post_ctpks_optimize) . . . . . . . . . . . . 59
do_post_ctpks_optimize (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Post-CTPKS Optimization—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Setup Fixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Hold-Time Fixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8
Global Routing and Post-Groute Optimizations
. . . . . . . . . . . . . . . 61
Global Routing and Post-Groute Optimizations—Tasks . . . . . . . . . . . . . . . . . . . . . . . . . 62

Global Routing and Post Groute Optimizations—Inputs and Outputs . . . . . . . . . . . . . . . 62
Global Routing and Post Groute Optimizations—Run Script (do_groute) . . . . . . . . . . 63
do_groute (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Fixing Hold-Time Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9
Final (Detail) Routing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Final Routing—Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Full Routing with Search-and-Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Final Routing—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Final Routing—Encapsulation Script (do_wroute) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
do_wroute—Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
do_wroute—Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
do_wroute—Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
do_wroute—Example Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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Final Routing—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10
Parasitic Extraction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Parasitic Extraction—Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Parasitic Extraction—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Parasitic Extraction—Encapsulation Script (do_hyperextract) . . . . . . . . . . . . . . . . . 74
do_hyperextract—Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
do_hyperextract—Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
do_hyperextract—Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
do_hyperextract—Example Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Parasitic Extraction—Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Generating A Cross-Coupling File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11
Static Timing and In-Place Optimizations
. . . . . . . . . . . . . . . . . . . . . 77
Static Timing and IPO—Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Static Timing—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Static Timing—Run Script (do_post_route_optimize) . . . . . . . . . . . . . . . . . . . . . . . 79
do_post_route_optimize (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IPO—Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IPO—Encapsulation Script (do_post_route_eco) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
do_post_route_eco—Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
do_post_route_eco—Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
do_post_route_eco—Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
do_post_route_eco—Example Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12
Verification
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Verification—Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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A
Complete Sample Run Script
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B
Documentation Sources
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
C
A More Sophisticated Directory Structure
. . . . . . . . . . . . . . . . . . . . . 93
D
Inputting Floorplanning Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Setting the Die Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Automatically Calculating the Die Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Automatic Growing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Supporting Floorplan Generation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Generating the Initial Floorplan from a DEF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
E
Setting Appropriate PKS Controls for Synthesis, Placement,
and Optimization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Setting the Appropriate PKS Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Timing-Driven Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
F
CTPKS Constraint File Example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
CTPKS Constraint File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
CTPKS Clock Tree Structure File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
CTPKS Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
CTPKS Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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G
Post Clock Tree Optimization Constraints
. . . . . . . . . . . . . . . . . . . . 111
Clock Insertion Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
H
Performing Global Routing, In-Place Timing Corrections, and
Post Groute Optimizations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Performing Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Performing In-Place Timing Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Performing Post Groute Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
I
Final (Detail) Route Options and Commands
. . . . . . . . . . . . . . . . 117
Setting the Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Running Wroute in Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Stopping Wroute in Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Running Wroute from within the SE GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
J
Running HyperExtract in Standalone Mode
. . . . . . . . . . . . . . . . . . 119
HyperExtract Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HyperExtract Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Running HyperExtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
dlcInitFile Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
K
Pearl Commands used to Create an SDF
. . . . . . . . . . . . . . . . . . . . 121
Creating An SDF With Pearl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Delay Calculation—Run Script (do_delay_calc) . . . . . . . . . . . . . . . . . . . . . . . . . 122
do_delay_calc—Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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do_delay_calc—Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
L
GCF File to Load Timing Libraries
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

example_gcf_file.gcf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
M
Command Syntax for Encapsulation Scripts
. . . . . . . . . . . . . . . . . 125
The do_ctpks Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
The do_wroute Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Wroute Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Required Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
The do_hyperextract Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
HyperExtract Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Required Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
The do_post_route_eco Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Wroute Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Required Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Synthesis Place-and-Route (SP&R) Flow Guide

May 2001 10 Product Version 4.0.8
N
Synopsys Conversion Utility
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Synthesis Place-and-Route (SP&R) Flow Guide
May 2001 11 Product Version 4.0.8
Preface
This preface contains the following sections:
■
About This Manual on page 11
■
Other Information Sources on page 11
■
Syntax Conventions on page 12
■
About the Graphical User Interface on page 13
About This Manual
This document describes the Cadence
®
synthesis place-and-route (SP&R) flow. The SP&R
flow integrates the Cadence
®
physically knowledgeable synthesis (PKS) tool with the Silicon
Ensemble™ place-and-route (SE) tool to take your complex deep sub-micron digital IC
designs all the way from RTL to GDSII.
Other Information Sources
For more information about Ambit BuildGates Synthesis and other related products, you can
consult the sources listed here.
■
Ambit BuildGates Synthesis User Guide

■
Command Reference for Ambit BuildGates Synthesis and Cadence PKS
■
Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS
■
Test Synthesis for Ambit BuildGates Synthesis and Cadence PKS
■
HDL Modeling for Ambit BuildGates Synthesis
■
Distributed Processing of Ambit BuildGates Synthesis
■
Constraint Translator for Ambit BuildGates Synthesis and Cadence PKS
Synthesis Place-and-Route (SP&R) Flow Guide
Preface
May 2001 12 Product Version 4.0.8
Depending on the product licenses your site has purchased, you could also have these
documents.
■
Datapath Option of Ambit BuildGates Synthesis and Cadence PKS
■
Low Power Option of Ambit BuildGates Synthesis and Cadence PKS
■
PKS User Guide
BuildGates synthesis is often used with other Cadence
®
tools during various design flows.
The following documents provide information about these tools and flows. Availability of these
documents depends on the product licenses your site has purchased.
■
Cadence Timing Library Format Reference

■
Cadence Pearl Timing Analyzer User Guide
■
Cadence General Constraint Format Reference
The following books are helpful references.
■
IEEE 1364 Verilog HDL LRM
■
TCL Reference,
Tcl and the Tk Toolkit
, John K. Ousterhout, Addison-Wesley
Publishing Company
Syntax Conventions
This section provides the Text Command Syntax used in this document.
Text Command Syntax
The list below describes the syntax conventions used for the Ambit BuildGates synthesis text
interface commands.
Important
Command names and arguments are case sensitive. User-defined information is
case sensitive for Verilog designs and, depending on the value specified for the
global variable
hdl_vhdl_case, may be case sensitive as well.
literal
Nonitalic words indicate keywords that you must enter literally.
These keywords represent command or option names.
Synthesis Place-and-Route (SP&R) Flow Guide
Preface
May 2001 13 Product Version 4.0.8
argument
Words in italics indicate user-defined arguments or information

for which you must substitute a name or a value.
|
Vertical bars (OR-bars) separate possible choices for a single
argument.
[ ]
Brackets denote optional arguments. When used with OR-bars,
they enclose a list of choices from which you can choose one.
{ }
Braces are used to indicate that a choice is required from the list
of arguments separated by OR-bars. You must choose one from
the list.
{ argument1 | argument2 | argument3 }
{ }
Bold braces are used in Tcl commands to indicate that the
braces must be typed in literally.
...
Three dots (...) indicate that you can repeat the previous
argument. If the three dots are used with brackets (that is,
[argument]...), you can specify zero or more arguments. If
the three dots are used without brackets (argument...),you
must specify at least one argument, but can specify more.
# The pound sign precedes comments in command files.
About the Graphical User Interface
This section describes the conventions used for the BuildGates synthesis graphical user
interface (GUI) commands and describes how to use the menus and forms in the BuildGates
synthesis software.
Using Menus
The GUI commands are located on menus at the top of the window. They can take one of
three forms.
CommandName

A command name with no dots or arrow executes immediately.
CommandName
… A command name with three dots displays a form for choosing
options.
Synthesis Place-and-Route (SP&R) Flow Guide
Preface
May 2001 14 Product Version 4.0.8
CommandName
-> A command name with a right arrow displays an additional menu
with more commands. Multiple layers of menus and commands
are presented in what are called command sequences, for
example:
File – Import – LEF
. In this example, you go to the File
menu, then the Import submenu, and, finally, the LEF command.
Using Forms
… A menu button that contains only three dots provides browsing
capability. When you select the browse button, a list of choices
appears.
Ok The
Ok
button executes the command and closes the form.
Cancel The
Cancel
button cancels the command and closes the form.
Defaults The
Defaults
button displays default values for options on the
form.
Apply The

Apply
button executes the command but does not close the
form.
Help The
Help
button provides information about the command.
Synthesis Place-and-Route (SP&R) Flow Guide
May 2001 15 Product Version 4.0.8
1
Introduction—RTL to GDSII
This document describes the Cadence
®
synthesis place-and-route (SP&R) flow. The SP&R
flow integrates the Cadence physically knowledgeable synthesis (PKS) tool with the Silicon
Ensemble™ place-and-route (SE) tool to take your complex deep sub-micron digital IC
designs all the way from RTL to GDSII.
RTL
GDSII
SP&R
Synthesis Place-and-Route (SP&R) Flow Guide
Introduction—RTL to GDSII
May 2001 16 Product Version 4.0.8
This SP&R flow has been developed to address the issues of timing closure and design
reliability, both of which are gaining significance as device geometries continue to shink
further into the deep sub-micron realm. Confronting these issues requires new levels of
integration between logic design and physical implementation technologies.
The SP&R flow tightly integrates RTL synthesis with final placement and routing. This new
flow yields greater timing correlation at all stages of the design process, which results in
smaller designs and faster completion.
There are many ways a design may be conveyed from RTL through GDSII; this document

describes a typical base flow. You can make modifications to this flow to suit your specific
requirements. Each step in the SP&R flow provides the required inputs and resulting outputs,
the setup requirements, the command files, and recommended practices. It also includes
descriptions of the utilities available to automate the steps in the SP&R flow, explanations of
how and where they are used, and information on how to get these utilities.
A comprehenisve list of documentation sources, including application notes, pertinentto each
step in the flow is provided to help you quickly locate more detailed information as needed.
To keep the descriptions simple, unless otherwise noted, it’s assumed that the logical design
at the RTL-level is represented in Verilog, but it can also be represented in VHDL. Similarly,
it’s assumed that gate-level logical netlists are described with Verilog, but they can also be
described with VHDL or EDIF.
The following diagram shows the high-level interaction between the two main technologies
(PKS and SE) within the SP&R flow.
Synthesis Place-and-Route (SP&R) Flow Guide
Introduction—RTL to GDSII
May 2001 17 Product Version 4.0.8
Overall Flow and Associated Commands
PKS
Floorplanning
use SE interface
Synthesis, Placement,
Optimization
do_pks
Clock Tree
Generation
do_ctpks
Post Clock Tree
Optimizations
do_post_ctpks_optimize
Global Routing

do_groute
Parasitic
Extraction
do_hyperextract
Delay
Calculation
do_delay_calc
Static Timing and
In-place Optimizations
do_post_route_optimize
do_post_route_eco
Verification
use HECK interface
use SE interface
Pre-Placement Optimization
Timing Driven Placement
Post-Placement Optimization
RTL Synthesis
Initial Area Estimation and
Timing Driven Block Placement
Generate CTPKS command
and constraint files, then
generate the clock tree
Propagated Clocks
Post Clock Tree Optimization
Verify Geometry
Verify Connectivity
Parasitic reduction and delay
calculation
SDF Back Annotation

Timing Correction
Hold Time Fixing
Formal Verification
HECK
RTL Synthesis
3rd Party Synthesis
RTL Synthesis
do_rtl
SE
Block Refinement
Power Routing
LEGEND
Main Steps
Commands
Timing Driven Global Routing
Post Route Optimizations
Hold Time Fixing
WROUTE
Final Route
Search and Repair
HyperExtract
2.5D Parasitic extraction
Final (Detail) Routing
do_wroute
RTL Synthesis
Floorplanning
Synthesis, Placement,
and Optimization
Clock Tree Generation
Post Clock Tree

Optimizations
Global Routing
Final (Detail) Routing
Parasitic Extraction
Verification
Static Timing and In-
Place Optimizations
Synthesis Place-and-Route (SP&R) Flow Guide
Introduction—RTL to GDSII
May 2001 18 Product Version 4.0.8
Synthesis Place-and-Route (SP&R) Flow Guide
May 2001 19 Product Version 4.0.8
2
Getting Started
This chapter describes the initial requirements you must meet before getting started with the
Cadence
®
synthesis place-and-route (SP&R) flow.
Initial Input Files
Several input files and libraries must be available before starting the SP&R flow. Figure 2-1
shows how the input files and libraries are categorized along with their supported formats.
Figure 2-1 Initial Files and Libraries Required By the SP&R Flow
Logical (RTL) Design Data (Required)
The original logical design data is presented in register transfer level (RTL) format and can
contain a mixture of high-level statements, gate-level netlists, and macro instantiations.
Verilog
VHDL
Logical (RTL)
Design Data
Physical

Design Data
DEF
PDEF
Timing
Library
TLF ALF
OLA (DCL)
Physical
Library
LEF
Timing
Constraints
TCL
LUT
LEF required,
LUT recommended
Only one type
is required
Optional
(see notes)
Only one type is required, but multiple
types can be used (see notes)
Required
Synthesis Place-and-Route (SP&R) Flow Guide
Getting Started
May 2001 20 Product Version 4.0.8
Physical Design Data (Optional)
Physical design data can be represented using the de facto standard DEF or industry
standard PDEF formats. (Note that PDEF can only describe placement and bounding box
data, while DEF can include additional information such as routing grids, power grids, pre-

routes, and rows.) This physical data is an optional input that would typically be available if
this were a redesign of an existing device. Also note that Cadence physically knowledgeable
synthesis (PKS) provides simple floorplanning features and can automatically generate an
initial floorplan. More detailed design data becomes available as you proceed through the
SP&R flow.
GCF File (Optional)
A GCF file may be generated from PKS for use in standalone versions of delay calculation
(Pearl), clock tree synthesis (CTGen), or the timing-driven place-and-route tools (Qplace and
Wroute). However, each of these functions are available in the PKS 4.0 release do not require
that you create a GCF file. When running the standalone tools as noted above, the GCF file
loads timing libraries and sets the operating conditions for the library. (An example GCF file
is shown in
GCF File to Load Timing Libraries on page 123.)
Supported Formats Source
Verilog Generated manually or from design capture tools, including block
diagram, schematic, state diagram, flow chart, truth table, and
textual HDL editors.
VHDL
Supported Formats Source
DEF 5.1+ Generated by a physical design tool such as a floor planner or a
placement engine.
PDEF 2.0
Supported Formats
GCF 1.3
GCF 1.4
Synthesis Place-and-Route (SP&R) Flow Guide
Getting Started
May 2001 21 Product Version 4.0.8
Timing Library (Required)
A timing library includes all of the timing information associated with a particular

manufacturing process. Only a single timing library is required by the SP&R flow, but it is
possible to use a mixture of timing libraries if you wish. For example, you may want to use an
ALF for standard cells and a TLF for macro libraries.
Note: If you use multiple timing library formats within the flow, you must ensure that they are
well correlated
.
Timing Constraints (Required)
The timing constraints are presented to the SP&R flow in the form of a TCL file (this file is
named constraints.tcl throughout this document).
Note: Be sure to run check_timing to validate that your constraints are correct.
Supported Formats Source
ALF 3.0 Timing libraries can come from various sources. Most common
are ASIC vendors or foundries, internal CAD library development
departments, or library vendors. Alternatively, new timing library
formats can be derived from existing timing libraries. For
example, translators exist to generate TLF or ALF libraries from
the Synopsys .LIB format.
Note that you may use the syn2tlf utility with the -4.3 option
to create new TLF 4.3 models (recommended).
OLA (DCL)
TLF 4.3
a
a.Using TLF 4.3 provides a significant number of timing engine enhancements versus using CTLF 3.x or TLF 4.1.
TLF 4.3 provides the slew measurement points (20%/80% or 10%/90%) resulting in better timing. Using TLF 4.3
is recommended, but if you must use CTLF 3.x or TLF 4.1, do the following:
set_global auto_slew_and_delay_degradation false
Supported Format Source
TCL The initial constraints are generated manually or
programmatically and are derived from the design’s timing
specification. (Note that a conversion utility that can convert

Synopsys write-script into TCL is provided with the SP&R flow.
See
Synopsys Conversion Utility on page 135 for more
information.
Synthesis Place-and-Route (SP&R) Flow Guide
Getting Started
May 2001 22 Product Version 4.0.8
Physical Library (Required)
The physical library describes the physical characteristic for a particular standard cell library.
This includes information like physical footprints, pin locations, and so on.
Note: In order to achieve the most accurate results possible, it is important that the R and C
values in the LEF are well correlated with the results from
HyperExtract
(HE). This means
that the library development team should use the lefCap.pl functionality to take the output
from HE and update the LEF. (For values that are non-design-specific, this tuning can be
performed using a representative design at the high-end of the typical utilization spectrum.)
Check with your Cadence representative for more information. If you are not using
HyperExtract
, you must make sure your LEF R and C values correlate well with the
extraction tool you are using.
Note: Be sure to run check_library to verify that your physical and timing libraries match.
Layer Usages Table (Recommended)
The layer usages table (LUT) is an ASCII text file used to provide information to the fast router
in PKS. This information guides PKS in its initial estimation phase to use the specified
percentages of each metalization layer for horizontal and vertical routes. For example,
horizontal tracks = 35% on metal layer 1, 40% on metal layer 3, and 25% on metal layer 6;
vertical tracks = 45% on metal layer 2, 45% on metal layer 4, and 10% on metal layer 6 (the
actual percentages used will be based on empirical data gathered from previous designs).
The LUT also includes resistance information for vias, the average number of vias that

typically appear on straight routes, and so on. (Different values for this data can be associated
with different route lengths.)
Supported Formats Source
LEF 5.2 As with timing libraries, physical libraries are generated primarily
by ASIC vendors, foundries, internal CAD library development
groups, or library vendors.
LEF 5.3
LEF 5.3.1
Supported Format Source
ASCII text
(see Note below)
Based on empirical data gathered from previous designs.
Synthesis Place-and-Route (SP&R) Flow Guide
Getting Started
May 2001 23 Product Version 4.0.8
Note: The LUT is considered to be part of the physical library data and is recommended
every time a LEF physical library is used.
An example LUT for a four-layer device technology is shown below. Further details can be
found in
Appendix A of the
PKS User Guide
.
Layer_Usages () {
Length_Range (0) {
Utilization_Horizontal: "0.229 0.005 0.765 0.001" ;
Utilization_Vertical: "0.002 0.585 0.001 0.412" ;
Contact_Spacing_Vertical: "20" ;
Contact_Spacing_Horizontal: "20" ;
}
}

To view the layer usages tables used in the system, use the write_layer_usages
command found in the
Command Reference for Ambit BuildGates Synthesis and
Cadence PKS
.
Run Scripts and Encapsulation Scripts
Each step in the design flow can be controlled manually or by using run scripts and
encapsulation scripts to define the flow environment. Note that you can load the appropriate
libraries and design data by keying in individual instructions, but this approach is prone to
errors. It is recommended that you use the following run scripts and encapsulation scripts to
define the flow environment and to load the appropriate libraries and design data:
Script Type Design Flow Script Description
Run script do_rtl Performs RTL synthesis.
Run script do_pks Performs synthesis, placement, and
optimization.
Run script do_ctpks Performs clock tree generation.
Run script do_post_ctpks_optimize Performs post clock tree optimizations.
Run script do_groute Performs global routing and optimization.
Encapsulation do_wroute Performs final (detail) routing.
Encapsulation do_hyperextract Performs parasitic extraction.
Run script do_delay_calc Performs delay calculations.
Run script do_post_route_optimize Performs post route optimizations.
Synthesis Place-and-Route (SP&R) Flow Guide
Getting Started
May 2001 24 Product Version 4.0.8
These scripts correspond to the steps in the flow and are discussed in more detail in the
following sections. However, you should note the following:
■
Run Scripts
Because each design flow is unique, it is necessary for you to create your own run

scripts. The run scripts presented in this document are intended to offer a starting point
and can be customized to meet your own unique requirements.
■
Encapsulation Scripts
Encapsulation scripts automatically generate appropriate command and constraint files
and then execute a specific function. These scripts are provided in the release hierarchy
under the release/BuildGates/version/examples/spnr_flow directory
in a file called spnr_utils.tcl.
Note that standalone run scripts are used throughout this document to show you how to
perform each step. By comparison,
Complete Sample Run Script on page 85 provides a
complete example script that takes you through the flow from start to finish without the
necessity of going in and out of sub-scripts.
Command Files—setup.tcl, library.tcl, and design.tcl
One way to create your run scripts is as a series of discrete (in-line) commands that explicitly
reference each and every file as shown in the example below:
example_run_script.tcl
read_alf <library>.alf
read_lef <library>.lef
read_verilog <design>.v
do_build_generic
source <timing_constraints.tcl>
source <physical_constraints.tcl>
do_optimize –pks
:
etc.
Encapsulation do_post_route_eco Performs post route engineering
changes.
Script Type Design Flow Script Description
Synthesis Place-and-Route (SP&R) Flow Guide

Getting Started
May 2001 25 Product Version 4.0.8
However, this technique can prove to be unwieldy should you wish to make any modifications
to your flow (such as using an alternative library). For this reason, it is recommended that you
use a combination of global variables and command files. The initial set of global variables
you might consider are as follows:
You will notice that the bulk of these discussions are based on the concept that all of your
working files are located in a single working directory. It is possible to create more
sophisticated environments as discussed in
A More Sophisticated Directory Structure on
page 93.
Next, it is suggested that you create the following three TCL command files as shown below.
setup.tcl (example)
set library_root <path_to_library_data>
set work_dir <path_to_current working directory>
source ${library_root}/library.tcl
Note the reference to the library.tcl file from within the setup.tcl file. This illustrates
that the library.tcl file is typically stored alongside its associated library files in some
central location.
Global Variable Description
design_root The path to the design’s top level/directory.
library_root The path to the library files which are usually stored in some
central location.
work_dir The path to your current working directory.
opt_flow The current optimization flow you wish to perform (that is,
working with RTL or a gate-level netlist).
TCL Command Files Description
setup.tcl Initializes the environment.
library.tcl Loads the libraries.
design.tcl Loads the design data.