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CS/ECEn 124 Exam I Pre-test
1.

Which computer can solve the hardest problems?
8-bit
16-bit
32-bit
64-bit

2.

No difference.
The ISA implements the micro-architecture
True

3.

False
What level of abstraction defines addressing modes?
Algorithms
Languages
ISA
Micro-archecture
Circuits

4.

Devices
A low-level language is translated to machine code by
a compiler
a simulator

an assembler
an ISA

5.

None of the above.
English makes for a good programming language.
True

6.

False
A compiler and assembler perform the same functions.
True

7.

False
What results in overflow?
The carry-in is not equal to the carry-out of the MSB.
The result of the operation cannot be stored in the data type.
The sum of two negative numbers is positive.
The sum of two positive numbers is negative.

8.

All of the above.
What is the decimal value of the 16-bit 2’s complement hex number 0xFFFC?
-12
-8

-4


-2
2

9.

4
What is the binary representation of the decimal number -39 (using 2’s-complement)?
1011001
1101001
1110001
01011001

10.

11011001
What is the decimal value of the 12-bit 2’s complement binary number 111111010001?
-57
-53
-47
-43
43

11.

47
The decimal value of the 8-bit 2's complement hex number 0xFA is
250

7
6
-5
-6
-7

12.

-250
The decimal number 92 is equivalent to which unsigned binary number?
1011100
1101100
1110110
1111111

13.

92
How many bits are required to store the unsigned number 256?
3
4
8
9

14.

10
How many different 2's complement non-negative numbers can be stored in 6 bits?
30

31
32
63
64
127

15.

128
The 8-bit 2’s-complement hexadecimal number 0xED sign-extended to 16 bits is
0x00ED
0xFED0
0xFFED
0b11101101
0b011101101

16.

0b0000000011101101
What are the two properties of data types?
Cardinality and representation.
Describability and correctness.
Integers and alphanumeric.
Sets of values and allowable operations on those values.

17.

Interpretation and representation.
What is 00110111 - 11110111 (2’s complement)?

00101110
00101111
00110001
01000000
11000000
11110111

18.

What type of gate is shown to the right?
AND
a.
NAND
b.
OR
c.
NOR
d.
NOT
e.


23.

Assume s=1, r=1, q=0, what is q after s=0?
0
a.
1
b.
Undefined

c.

26.

a.

b.

.
27.

f.

29.

30.

31.

32.

33.

e.

a.

b.

c.

d.

e.

a.

b.

c.

d.

e.

a.

b.

c.

d.

e.

a.

b.

c.

d.

e.

a.

b.

c.

d.

e.

a.

b.

c.

d.

e.

g.

Which symbol is used for the OR gate?
f.

d.

g.

Which symbol is used for the NOT gate?
f.

c.

g.

Which symbol is used for the NOR gate?
f.

b.

g.

Which symbol is used for the NAND gate?
f.

a.

g.

Which symbol is used for the multiplexor gate?
f.

e

g.

Which symbol is used for the decoder gate?
f.

d.

g.

Which symbol is used for the AND gate?
f.

28.

c.

g.


34.

What is the truth table for S0'?
a.

b.

c.

d.

38.

T R S0 S1 S0'
1 0 0

0

1

1 0 0

1

1

1 0 1

0

0

1 0 1

1

0

T R S0 S1 S0'
1 0 0

0

0

1 0 0

1

1

1 0 1

0

0

1 0 1

1

0

T R S0 S1 S0'
1 0 0

0

1

1 0 0

1

0

1 0 1

0

0

1 0 1

1

1

T R S0 S1 S0'
1 0 0

0

0

1 0 0

1

1

1 0 1

0

1

1 0 1

1

1

What is the logical Boolean expression for S1'?
T * -R * (S0 * -S1 + -S0 * S1)
a.


T * -R * S0 * -S1 + -S0 * S1
b.
T * R * S0 * S1
c.
T * -R + S0 * -S1 + -S0 * S1
d.
42. How are RISC and CISC instruction sets the same?
Both are compiler friendly.
a.
Both are forms of an ISA.
b.
Both are pipeling friendly.
c.

Both emphasize software and hardware.
d.
Both produce approximately the same code size.
e.
Both require about the same number of transistors to implement.
f.
Both take multiple cycles to execute instructions.
g.
49. The PC is incremented during which phase of an instruction execution?
FETCH
a.
DECODE
b.
SOURCE OPERAND FETCH
c.
DESTINATION OPERAND FETCH
d.
EXECUTE
e.
STORE
f.
55. Address space and addressability are names for a memory address.
True

56.

False
The fast the system clock, the faster the machine.
True

False
If the source register is R4, which source addressing mode does NOT require an extension word?
Register
a.
Indexed
b.
Indirect
c.
Indirect auto-increment
d.
Absolute
e.
Symbolic
f.
Immediate
g.
a and b
h.
a, and c
i.
a, c, and d
j.
67. What operand is generated when using a source operand of @R3+?
57.


-1
a.
0
b.

1
c.
2
d.
4
e.
8
f.
73. What are emulated instructions?
Additional CPU instructions made from undefined op-codes.
a.
Instructions automatically replaced by defined CPU instruction.
b.
Instructions replaced by multiple instructions.
c.
Instructions that look like other instructions.
d.
All of the above.
e.
78. Knowing how many cycles are required to execute an instruction is important because?
Instruction cycles are equated to power consumption.
a.
Instruction cycles are directly related to execution timing.
b.
Instruction cycles help in choosing which addressing mode to use.
c.
All of the above.
d.
82. What is NOT true of all MSP430 Ports?
Digital I/O 8-bit memory locations.

a.
All have independent bit access.
b.
All have input/output capability.
c.
All have interrupt functionality.
d.
All have read/write access using regular MSP430 byte instructions.
e.
All of the above are true of MSP430 Ports.
f.