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10
TRANSISTOR AMPLIFIER DESIGN
Ampli®ers are among the basic building blocks of an electronic system. While
vacuum tube devices are still used in high-power microwave circuits, transistorsÐ
silicon bipolar junction devices, GaAs MESFET, heterojunction bipolar transistors
(HBT), and high-electron mobility transistors (HEMT)Ðare common in many RF
and microwave designs. This chapter begins with the stability considerations for a
two-port network and the formulation of relevant conditions in terms of its scattering
parameters. Expressions for input and output stability circles are presented next to
facilitate the design of ampli®er circuits. Design procedures for various small-signal
single-stage ampli®ers are discussed for unilateral as well as bilateral transistors.
Noise ®gure considerations in ampli®er design are discussed in the following
section. An overview of broadband ampli®ers is included. Small-signal equivalent
circuits and biasing mechanisms for various transistors are also summarized in
subsequent sections.
10.1 STABILITY CONSIDERATIONS
Consider a two-port network that is terminated by load Z
L
as shown in Figure 10.1.
A voltage source V
S
with internal impedance Z
S
is connected at its input port.
Re¯ection coef®cients at its input and output ports are G
in
and G
out
, respectively. The
source re¯ection coef®cient is G
S
while the load re¯ection coef®cient is G
L
.
Expressions for input and output re¯ection coef®cients were formulated in the
preceding chapter (Examples 9.6 and 9.7).
385
Radio-Frequency and Microwave Communication Circuits: Analysis and Design
Devendra K. Misra
Copyright # 2001 John Wiley & Sons, Inc.
ISBNs: 0-471-41253-8 (Hardback); 0-471-22435-9 (Electronic)
For this two-port to be unconditionally stable at a given frequency, the following
inequalities must hold:
jG
S
j < 1 10:1:1
jG
L
j < 1 10:1:2
jG
in
j S
11
S
21
S
12
G
L
1 À S
22
G
L
< 1 10:1:3
and,
jG
out
j S
22
S
21
S
12
G
S
1 À S
11
G
S
< 1 10:1:4
Condition (10.1.3) can be rearranged as follows:
S
11
S
22
S
21
S
12
G
L
S
12
S
21
À S
12
S
21
S
22
1 À S
22
G
L
< 1
or,
1
S
22
D
S
21
S
12
1 À S
22
G
L
< 1 10:1:5
where,
D S
11
S
22
À S
12
S
21
10:1:6
Since
1 À S
22
G
L
3
G
L
1
1 À S
22
1 ÀjS
22
j expjyA 10:1:7
Figure 10.1 A two-port network with voltage source at its input and a load terminating the
output port.
386
TRANSISTOR AMPLIFIER DESIGN
This traces a circle on the complex plane as y varies from zero to 2p. It is illustrated
in Figure 10.2. Further, 1=1 ÀjS
22
j exp jy represents a circle of radius r with its
center located at d, where
r
1
2
1
1 ÀjS
22
j
À
1
1 jS
22
j
jS
22
j
1 ÀjS
22
j
2
10:1:8
and,
d
1
2
1
1 jS
22
j
1
1 ÀjS
22
j
1
1 ÀjS
22
j
2
10:1:9
Hence, for jG
L
j 1and G
L
y, condition (10.1.5) may be written as follows:
1
jS
22
j
D S
21
S
12
1 jS
22
j exp jy
1 ÀjS
22
j
2
< 1
or,
1
jS
22
j
D
S
12
S
21
1 ÀjS
22
j
2
S
12
S
21
jS
22
j exp jy
1 ÀjS
22
j
2
< 1 10:1:10
Now, using the Minkowski inequality,
P
n
k1
ja
k
b
k
j
p
1=p
P
n
k1
ja
k
j
p
1=p
P
n
k1
jb
k
j
p
1=p
10:1:11
we ®nd that (10.1.10) is satis®ed if
1
jS
22
j
D
S
12
S
21
1 ÀjS
22
j
2
jS
12
S
21
j
1 ÀjS
22
j
2
< 1
or,
1
jS
22
j
D
S
12
S
21
1 ÀjS
22
j
2
< 1 À
jS
12
S
21
j
1 ÀjS
22
j
2
10:1:12
Since the left-hand side of (10.1.12) is always a positive number, this inequality will
be satis®ed if the following is true
1 ÀjS
22
j
2
ÀjS
12
S
21
j > 0 10:1:13
STABILITY CONSIDERATIONS
387
Similarly, stability condition (10.1.4) will be satis®ed if
1 ÀjS
11
j
2
ÀjS
12
S
21
j > 0 10:1:14
Adding (10.1.13) and (10.1.14), we get
2 ÀjS
11
j
2
ÀjS
22
j
2
À 2jS
12
S
21
j > 0
or,
1 À
1
2
jS
11
j
2
jS
22
j
2
> jS
12
S
21
j10:1:15
From (10.1.6) and (10.1.15), we have
jDj < jS
11
S
22
jjS
12
S
21
j < jS
11
S
22
j1 À
1
2
jS
11
j
2
jS
22
j
2
or,
jDj < 1 À
1
2
jS
11
jÀjS
22
j
2
AjDj < 1 10:1:16
Multiplying (10.1.13) and (10.1.14), we get
1 ÀjS
22
j
2
ÀjS
12
S
21
j1 ÀjS
11
j
2
ÀjS
12
S
21
j > 0
or,
1 ÀjS
11
j
2
ÀjS
22
j
2
À 2jS
12
S
21
jz > 0 10:1:17
Figure 10.2 A graphical representation of (10.1.7).
388
TRANSISTOR AMPLIFIER DESIGN
where,
z jS
11
j
2
jS
22
j
2
jS
12
S
21
j
2
jS
12
S
21
jjS
11
j
2
jS
22
j
2
From the self-evident identity,
jS
12
S
21
jjS
11
jÀjS
22
j
2
! 0
it can be proved that
z jDj
2
Therefore, (10.1.17) can be written as follows:
1 ÀjS
11
j
2
ÀjS
22
j
2
À 2jS
12
S
21
jjDj
2
> 0
or,
1 ÀjS
11
j
2
ÀjS
22
j
2
jDj
2
> 2jS
12
S
21
j
or,
1 ÀjS
11
j
2
ÀjS
22
j
2
jDj
2
2jS
12
S
21
j
> 1
Therefore,
k
1 ÀjS
11
j
2
ÀjS
22
j
2
jDj
2
2jS
12
S
21
j
> 1 10:1:18
If S-parameters of a transistor satisfy conditions (10.1.16) and (10.1.18) then it is
stable for any passive load and generator impedance. In other words, this transistor is
unconditionally stable. On the other hand, it may be conditionally stable (stable for
limited values of load or source impedance) if one or both of these conditions are
violated. It means that the transistor can provide stable operation for a restricted
range of G
S
and G
L
. A simple procedure to ®nd these stable regions is to test
inequalities (10.1.3) and (10.1.4) for particular load and source impedances. An
alternative graphical approach is to ®nd the circles of instability for load and
generator re¯ection coef®cients on a Smith chart. This latter approach is presented
below.
STABILITY CONSIDERATIONS
389
From the expression of input re¯ection coef®cient (9.4.7), we ®nd that
G
in
S
11
S
21
S
12
G
L
1 À S
22
G
L
A G
in
1 À S
22
G
L
S
11
1 À S
22
G
L
S
21
S
12
G
L
or,
G
in
S
11
À G
L
S
11
S
22
À S
12
S
21
À G
in
S
22
AG
L
S
11
À G
in
D À G
in
S
22
or,
G
L
S
11
À G
in
D À G
in
S
22
S
22
S
22
1
S
22
S
11
S
22
À G
in
S
22
À S
12
S
21
S
12
S
21
D À G
in
S
22
or,
G
L
1
S
22
1
S
12
S
21
D À G
in
S
22
1
DS
22
D
S
12
S
21
1 À G
in
D
À1
S
22
10:1:19
As before, 1 À G
in
S
22
D
À1
represents a circle on the complex plane. It is centered
at 1 with radius jG
in
S
22
D
À1
j; the reciprocal of this expression is another circle with
center at
1
2
1
1 jD
À1
S
22
j
1
1 ÀjD
À1
S
22
j
1
1 ÀjD
À1
S
22
j
2
and radius
1
2
1
1 ÀjD
À1
S
22
j
1
1 jD
À1
S
22
j
jD
À1
S
22
j
1 ÀjD
À1
S
22
j
2
Since jG
in
j < 1, the region of stability will include all points on the Smith chart
outside this circle. From (10.1.19), the center of the load impedance circle, C
L
,is
C
L
1
DS
22
D
S
12
S
21
1 ÀjD
À1
S
22
j
2
1
DS
22
D
S
12
S
21
jDj
2
jDj
2
ÀjS
22
j
2
or,
C
L
1
S
22
1
S
12
S
21
D*
jDj
2
ÀjS
22
j
2
1
S
22
jDj
2
ÀjS
22
j
2
S
12
S
21
D*
jDj
2
ÀjS
22
j
2
390
TRANSISTOR AMPLIFIER DESIGN
or,
C
L
1
S
22
D*D S
12
S
21
ÀjS
22
j
2
jDj
2
ÀjS
22
j
2
1
S
22
D*S
11
S
22
ÀjS
22
j
2
jDj
2
ÀjS
22
j
2
Therefore,
C
L
D*S
11
À S*
22
jDj
2
ÀjS
22
j
2
S
22
À DS**
11
*
jS
22
j
2
ÀjDj
2
10:1:20
Its radius, r
L
, is given by
r
L
1
jDS
22
j
S
12
S
21
jD
À1
S
22
j
1 ÀjD
À1
S
22
j
2
S
12
S
21
jDj
2
ÀjS
22
j
2
10:1:21
As explained following (10.1.19), this circle represents the locus of points over
which the input re¯ection coef®cient G
in
is equal to unity. On one side of this circle,
the input re¯ection coef®cient is less than unity (stable region) while on its other side
it exceeds 1 (unstable region). When load re¯ection coef®cient G
L
is zero (i.e., a
matched termination is used), G
in
is equal to S
11
. Hence, the center of the Smith
chart (re¯ection coef®cient equal to zero) represents a stable point if jS
11
j is less than
unity. On the other hand, it represents unstable impedance for jS
11
j greater than
unity. If G
L
0 is located outside the stability circle and is found stable then all
outside points are stable. Similarly, if G
L
0 is inside the stability circle and is
found stable then all enclosed points are stable. If G
L
0 is unstable then all points
on that side of the stability circle are unstable.
Similarly, the locus of G
S
can be derived from (10.1.4), with its center C
S
and its
radius r
S
given as follows:
C
S
D*S
22
À S**
11
jDj
2
ÀjS
11
j
2
S
11
À DS**
22
*
jS
11
j
2
ÀjDj
2
10:1:22
and,
r
S
1
jDS
11
j
S
12
S
21
jD
À1
S
11
j
1 ÀjD
À1
S
11
j
2
S
12
S
21
jDj
2
ÀjS
11
j
2
10:1:23
This circle represents the locus of points over which output re¯ection coef®cient
G
out
is equal to unity. On one side of this circle, output re¯ection coef®cient is less
than unity (stable region) while on its other side it exceeds 1 (unstable region). When
the source re¯ection coef®cient G
S
is zero then G
out
is equal to S
22
. Hence, the center
of the Smith chart (re¯ection coef®cient equal to zero) represents a stable point if
jS
22
j is less than unity. On the other hand, it represents an unstable impedance point
for jS
22
j greater than unity. If G
S
0 is located outside the stability circle and is
STABILITY CONSIDERATIONS
391
found stable then all outside source-impedance points are stable. Similarly, if G
S
0
is inside the stability circle and is found stable then all enclosed points are stable. If
G
S
0 is unstable then all points on that side of the stability circle are unstable.
Example 10.1: S-parameters of a properly biased transistor are found at 2 GHz as
follows (50-O reference impedance):
S
11
0:894À60:6
; S
12
0:02 62:4
; S
21
3:122 123:6
;
S
22
0:781À27:6
Determine its stability and plot the stability circles if the transistor is potentially
unstable (see Figure 10.3).
From (10.1.16) and (10.1.18), we get
jDjjS
11
S
22
À S
12
S
21
j0:6964
and,
k
1 jDj
2
ÀjS
11
j
2
ÀjS
22
j
2
2jS
12
S
21
j
0:6071
Figure 10.3 Input and output stability circles for Example 10.1.
392
TRANSISTOR AMPLIFIER DESIGN
Since one of the conditions for stability failed above, this transistor is potentially
unstable.
Using (10.1.20)±(10.1.23), we can determine the stability circles as follows. For
the output stability circle:
C
L
1:36 46:7
and,
r
L
0:5
Since jS
11
j is 0.894, G
L
0 represents a stable load point. Further, this point is
located outside the stability circle, and therefore, all points outside this circle are
stable.
For the input stability circle:
C
S
1:13 68:5
and,
r
S
0:2
Since jS
22
j is 0.781, G
S
0 represents a stable source impedance point. Further, this
point is located outside the stability circle, and therefore, all points outside this circle
are stable.
For the output stability circle, draw a radial line at 46.7
. With the radius of the
Smith chart as unity, locate the center at 1.36 on this line. It can be done as follows.
Measure the radius of the Smith chart using a ruler scale. Supposing that it is d mm.
Location of the stability circle is then at 1.36 d mm away on this radial line.
Similarly, the radius of the stability circle is 0.5 d mm. Load impedance must lie
outside this circle for the circuit to be stable. Following a similar procedure, the input
stability circle is drawn with its radius as 0.2 d mm and center at 1.13 d mm on the
radial line at 68.5
. In order to have a stable design, the source impedance must lie
outside this circle.
10.2 AMPLIFIER DESIGN FOR MAXIMUM GAIN
In this section, ®rst we consider the design of an ampli®er that uses a unilateral
transistor (S
12
0) and has maximum possible gain. A design procedure using a
bilateral transistor (S
12
T 0) is developed next that requires simultaneous conjugate
matching at its two ports.
AMPLIFIER DESIGN FOR MAXIMUM GAIN
393
Unilateral Case
When S
12
is zero, the input re¯ection coef®cient G
in
reduces to S
11
while the output
re¯ection coef®cient G
out
simpli®es to S
22
. In order to obtain maximum gain, source
and load re¯ection coef®cients must be equal to S*
11
and S*
22
; respectively. Further,
the stability conditions for a unilateral transistor simplify to
jS
11
j < 1
and,
jS
22
j < 1
Example 10.2: S-parameters of a properly biased BJT are found at 1 GHz as
follows (with Z
o
50 O):
S
11
0:606À155
; S
22
0:48À20
; S
12
0; and S
21
6 180
Determine the maximum gain possible with this transistor and design an RF circuit
that can provide this gain.
(i) Stability check:
k
1 ÀjS
11
j
2
ÀjS
22
j
2
jDj
2
2jS
12
S
21
j
I; , S
12
0
and,
jDjjS
11
S
22
À S
12
S
21
jjS
11
S
22
j0:2909
Since both of the conditions are satis®ed, the transistor is unconditionally stable.
(ii) Maximum possible power gain of the transistor is found as
G
TU
1 ÀjG
S
j
2
j1 À G
11
G
S
j
2
? jS
21
j
2
?
1 ÀjG
L
j
2
j1 À S
22
G
L
j
2
and
G
TU
max
1 ÀjS*
11
j
2
j1 ÀjS
11
j
2
j
2
? jS
21
j
2
?
1 ÀjS*
22
j
2
j1 ÀjS
22
j
2
j
2
1
1 À 0:606
2
? 6
2
?
1
1 À 0:48
2
73:9257
394
TRANSISTOR AMPLIFIER DESIGN
or,
G
TU
max
10 log
10
73:9257dB 18:688 dB
(iii) For maximum unilateral power gain,
G
S
S*
11
0:606 155
; and G
L
S*
22
0:48 20
Component values are determined from the Smith chart as illustrated in Figure 10.4.
Corresponding to the re¯ection coef®cient's magnitude 0.606, VSWR is 4.08.
Hence, point D in Figure 10.4 represents the source impedance Z
S
. Similarly, point B
can be identi®ed as the load impedance Z
L
. Alternatively, the normalized impedance
can be computed from the re¯ection coef®cient. Then, points D and B can be located
on the Smith chart. Now, we need to transform the zero re¯ection coef®cient
(normalized impedance of 1) to G
S
(point D) at the input and to G
L
(point B) at the
output. One way to achieve this is to move ®rst on the unity conductance circle from
the center of the chart to point C and then on the constant resistance circle to reach
point D. Thus, it requires a shunt capacitor and then a series inductor to match at the
input. Similarly, we can follow the unity resistance circle from 1 to point A and then
the constant conductance circle to reach point B. Thus, a capacitor is connected in
series with the load and then an inductor in shunt to match its output side. Actual
values of the components are determined as follows.
Normalized susceptance at point C is estimated as j1:7. Hence, the shunt
capacitor on the source side must provide a susceptance of 1:7=50 0:034 S.
Figure 10.4 Smith chart illustrating the design of Example 10.2.
AMPLIFIER DESIGN FOR MAXIMUM GAIN
395
Since the signal frequency is 1 GHz, this capacitance must be 5.411 pF. Now, the
change in normalized reactance from point C to point D is determined as
j0:2 ÀÀj0:45j0:65. The positive sign indicates that it is an inductor of
reactance 0:65 ? 50 32:5 O. The corresponding inductance is found as 5.1725 nH.
Similarly, the normalized reactance at point A is estimated as Àj1:38. Hence,
the load requires a series capacitor of 2.307 pF. For transforming the susceptance
of point A to that of point B, we need an inductance of À0:16 À 0:48=
50 À0:0128 S. It is found to be a shunt inductor of 12.434 nH. This circuit is
illustrated in Figure 10.5.
Bilateral Case (Simultaneous Conjugate Matching)
In order to obtain the maximum possible gain, a bilateral transistor must be matched
at both its ports simultaneously. This is illustrated in Figure 10.6. While its output
port is properly terminated, the input side of the transistor is matched with the source
such that G
in
G
S
*. Similarly, the output port of transistor is matched with the load
while its input is matched terminated.
Mathematically,
G
in
G
S
*
and
G
out
G
L
*
Figure 10.5 RF circuit designed for Example 10.2.
Figure 10.6 A bilateral transistor with input and output matching networks.
396
TRANSISTOR AMPLIFIER DESIGN
Therefore,
G
S
* S
11
S
12
S
21
G
L
1 À S
22
G
L
10:2:1
and,
G
L
* S
22
S
12
S
21
G
S
1 À S
11
G
S
10:2:2
From (10.2.1),
G
S
S*
11
S*
12
S*
21
1
G
L
*
À S*
22
10:2:3
and from (10.2.2),
G
L
*
S
22
ÀS
11
S
22
À S
12
S
21
G
S
1 À S
11
G
S
S
22
À G
S
D
1 À S
11
G
S
10:2:4
Substituting (10.2.4) in (10.2.3), we have
G
S
S*
11
S*
12
S*
21
1 À S
11
G
S
S
22
À G
S
D
À S*
22
or,
G
S
S*
11
S*
12
S*
21
S
22
À G
S
D
1 À S
11
G
S
ÀjS
22
j
2
G
S
S*
22
D
S*
11
S*
12
S*
21
S
22
À G
S
D
1 ÀjS
22
j
2
ÀS
11
À S*
22
DG
S
or,
1 ÀjS
22
j
2
G
S
ÀS
11
À S*
22
DG
2
S
S*
11
1 ÀjS
22
j
2
ÀS*
11
S
11
À S*
22
DG
S
S*
12
S*
21
S
22
À G
S
D
or,
S
11
À S*
22
DG
2
S
jDj
2
ÀjS
11
j
2
jS
22
j
2
À 1G
S
S*
11
À S
22
D*0
AMPLIFIER DESIGN FOR MAXIMUM GAIN
397
This is a quadratic equation in G
S
and its solution can be found as follows:
G
S
B
1
Æ
B
2
1
À 4jC
1
j
2
q
2C
1
G
MS
10:2:5
where,
B
1
1 jS
11
j
2
ÀjS
22
j
2
ÀjDj
2
and
C
1
S
11
À S*
22
D
Similarly, a quadratic equation for G
L
can be formulated. Solutions to that
equation are found to be
G
ML
B
2
Æ
B
2
2
À 4jC
2
j
2
q
2C
2
10:2:6
where
B
2
1 jS
22
j
2
ÀjS
11
j
2
ÀjDj
2
and,
C
2
S
22
À S*
11
D:
If jB
1
=2C
1
j > 1 and B
1
> 0 in equation (10.2.5) above, then the solution with a
minus sign produces jG
MS
j < 1 and that with a positive sign produces jG
MS
j > 1.
On other hand, if jB
1
=2C
1
j > 1 with B
1
< 0 in this equation, the solution with a plus
sign produces jG
MS
j < 1 and the solution with a minus sign produces jG
MS
j > 1.
Similar considerations apply to equation (10.2.6) as well.
OBSERVATION: jB
i
=2C
i
j > 1 implies that jkj > 1.
Proof:
B
i
2C
i
> 1 A
1 jS
11
j
2
ÀjS
22
j
2
ÀjDj
2
2S
11
À S*
22
D
> 1
398
TRANSISTOR AMPLIFIER DESIGN
or,
j1 jS
11
j
2
ÀjS
22
j
2
ÀjDj
2
j > 2jS
11
À S*
22
Dj
Squaring on both sides of this inequality, we get
j1 jS
11
j
2
ÀjS
22
j
2
ÀjDj
2
j
2
> 4jS
11
À S*
22
Dj
2
and,
jS
11
À S*
22
Dj
2
S
11
À S*
22
DS*
11
À S
22
D*jS
12
S
21
j
2
1 ÀjS
22
j
2
jS
11
j
2
ÀjDj
2
Therefore,
j1 jS
11
j
2
ÀjS
22
j
2
ÀjDj
2
j
2
> 4jS
12
S
21
j
2
41 ÀjS
22
j
2
jS
11
j
2
ÀjDj
2
or,
j1 jS
11
j
2
ÀjS
22
j
2
ÀjDj
2
j
2
À 41 ÀjS
22
j
2
jS
11
j
2
ÀjDj
2
> 4jS
12
S
21
j
2
or,
1 ÀjS
22
j
2
ÀjS
11
j
2
jDj
2
2
> 4jS
12
S
21
j
2
or,
j1 ÀjS
22
j
2
ÀjS
11
j
2
jDj
2
j > 2jS
12
S
21
j
Therefore,
j1 ÀjS
22
j
2
ÀjS
11
j
2
jDj
2
j
2jS
12
S
21
j
> 1 A k > 1
Also, it can be proved that jDj < 1 implies that B
1
> 0 and B
2
> 0. Therefore,
minus signs must be used in equations (10.2.5) and (10.2.6). Since,
G
T
max
1 ÀjG
MS
j
2
jS
21
j
2
1 ÀjG
ML
j
2
j1 À S
11
G
MS
1 À S
22
G
ML
ÀS
12
S
21
G
ML
G
MS
j
2
substituting equations (10.2.5), (10.2.6), and k from (10.1.18) gives
G
T
max
jS
21
j
jS
12
j
k À
k
2
À 1
p
10:2:7
AMPLIFIER DESIGN FOR MAXIMUM GAIN
399
Maximum stable gain is de®ned as the value of G
T
max
when k 1. Therefore,
G
MSG
S
21
S
12
10:2:8
Example 10.3: S-parameters of a properly biased GaAs FET HFET-1101 are
measured using a 50-O network analyzer at 6 GHz as follows:
S
11
0:614À167:4
; S
21
2:187 32:4
; S
12
0:046 65
; S
22
0:716À83
Design an ampli®er using this transistor for a maximum possible gain.
First we need to test for stability using (10.1.16) and (10.1.18).
jDjjS
11
S
22
À S
12
S
21
j0:3419
and,
k
1 ÀjS
11
j
2
ÀjS
22
j
2
jDj
2
2jS
12
S
21
j
1:1296
Since both of the conditions are satis®ed, the transistor is unconditionally stable.
For the maximum possible gain, we need to use simultaneous conjugate
matching. Therefore, the source and load re¯ection coef®cients are determined
from (10.2.5) and (10.2.6) as follows:
G
MS
B
1
À
B
2
1
À 4jC
1
j
2
q
2C
1
0:8673 169:76
and,
G
ML
B
2
À
B
2
2
À 4jC
2
j
2
q
2C
2
0:9011 84:48
There are many ways to synthesize these circuits. The design of one of the circuits
is discussed here. As illustrated in Figure 10.7, normalized impedance points A and
C are identi®ed corresponding to G
MS
and G
ML
, respectively. The respective
normalized admittance points B and D are next located. One way to transform the
normalized admittance of unity to that of point B is to add a shunt susceptance
(normalized) of about j2:7 at point E. This can be achieved with a capacitor or a stub
of 0:194 l as shown in Figure 10.8. Now, for moving from point E to point B, we
require a transmission line of about 0:065 l. Similarly, an open-circuited shunt stub
400
TRANSISTOR AMPLIFIER DESIGN
of 0:297 l will transform the unity value to 1 À j3:4 at point F and a transmission
line length of 0:09 l will transform it to the desired value at point D.
Note that both of the shunt stubs are asymmetrical about the main line. A
symmetrical stub is preferable. It can be achieved via two shunt-connected stubs of
susceptance j1:35 at the input end and of Àj1:7 at the output. This circuit is
illustrated in Figure 10.9.
Figure 10.7 Design of input and output side matching networks.
Figure 10.8 RF part of the ampli®er circuit for Example 10.3.
AMPLIFIER DESIGN FOR MAXIMUM GAIN
401
The value of the gain is evaluated from (10.2.7) as follows:
G
T
max
jS
21
j
jS
12
j
k À
k
2
À 1
p
28:728 A 10 ? log28:72814:58 dB
Unilateral Figure of Merit: In preceding examples, we ®nd that the design with a
bilateral transistor is a bit complex in comparison with a unilateral case. Procedure
for the bilateral transistor becomes even more cumbersome when the speci®ed gain
is less than its maximum possible value. It can be simpli®ed by assuming that a
bilateral transistor is unilateral. The unilateral ®gure of merit provides an estimate of
the error associated with this assumption. It can be formulated from (9.4.8) and
(9.4.10) as follows:
G
T
G
TU
j1 À S
22
G
L
j
2
j1 À G
out
G
L
j
2
1 À S
22
G
L
1 À S
22
G
L
À
S
12
S
21
G
S
G
L
1 À S
11
G
S
2
1
1 À
S
12
S
21
G
S
G
L
1 À S
22
G
L
1 À S
11
G
S
2
or,
G
T
G
TU
1
1 À X
2
Figure 10.9 RF part of the ampli®er circuit with symmetrical stubs.
402
TRANSISTOR AMPLIFIER DESIGN
where
X
S
12
S
21
G
S
G
L
1 À S
22
G
L
1 À S
11
G
S
Therefore, the bounds of this gain ratio are given by
1
1 jXj
2
<
G
T
G
TU
<
1
1 ÀjXj
2
When G
S
S*
11
and G
L
S*
22
, G
TU
has a maximum value. In this case, the
maximum error introduced by using G
TU
in place of G
T
ranges as follows:
1
1 U
2
<
G
T
G
TU
<
1
1 À U
2
10:2:9
where,
U
jS
12
kS
21
kS
11
kS
22
j
1 ÀjS
11
j
2
1 ÀjS
22
j
2
10:2:10
The parameter U is known as the unilateral ®gure of merit.
Example 10.4: The scattering parameters of two transistors are given below.
Compare the unilateral ®gures of merit of the two.
Transistor A
S
11
0:45 150
; S
12
0:01À10
S
21
2:05 10
; S
22
0:4À150
Transistor B
S
11
0:641À171:3
; S
12
0:057 16:3
S
21
2:058 28:5
; S
22
0:572À95:7
From (10.2.10), we ®nd that
U
0:01 Ã 2:05 Ã 0:45 Ã 0:4
1 À 0:45
2
1 À 0:4
2
0:00551 U
A
for transistor A.
AMPLIFIER DESIGN FOR MAXIMUM GAIN
403
Similarly, for transistor B,
U
0:057 Ã 2:058 Ã 0:641 Ã 0:572
1 À 0:641
2
1 À 0:572
2
0:1085 U
B
Hence, the error bounds for these two transistors can be determined from (10.2.9)
as follows. For transistor A,
0:9891 <
G
T
G
TU
< 1:0055
and for transistor B,
0:8138 <
G
T
G
TU
< 1:2582
Alternatively, these two results can be expressed in dB as follows:
À0:0476 dB <
G
T
G
TU
< 0:0238 dB
and,
À0:8948 dB <
G
T
G
TU
< 0:9976 dB
CONCLUSION: If S
12
0 can be assumed for a transistor without introducing
signi®cant error, the design procedure will be much simpler in comparison with that
of a bilateral case.
10.3 CONSTANT GAIN CIRCLES
In the preceding section, we considered the design of ampli®ers for maximum
possible gains. Now, let us consider the design procedure for other ampli®er circuits.
We split it again into two cases, namely, the unilateral and the bilateral transistors.
Unilateral Case
We consider two different cases of the unilateral transistors. In one case, it is
assumed that the transistor is unconditionally stable because jS
11
j and jS
22
j are less
than unity. In the other case, one or both of these parameters may be greater than
unity. Thus, it makes jDj greater than 1.
404
TRANSISTOR AMPLIFIER DESIGN
From (9.4.10)
G
TU
1 ÀjG
S
j
2
j1 À S
11
G
S
j
2
? jS
21
j
2
?
1 ÀjG
L
j
2
j1 À S
22
G
L
j
2
G
S
? G
o
? G
L
Expressions of G
S
and G
L
in this equation are similar in appearance. Therefore,
we can express them by the following general form:
G
i
1 ÀjG
i
j
2
j1 À S
ii
G
i
j
2
;
i S; ii 11
i L; ii 22
10:3:1
Now, let us consider two different cases of unilateral transistors. In one case the
transistor is unconditionally stable and in the other case it is potentially unstable.
(i) If the unilateral transistor is unconditionally stable then jS
ii
j < 1. Therefore,
maximum G
i
in (10.3.1) will be given as
G
imax
1
1 ÀjS
ii
j
2
10:3:2
Impedances that produce G
imax
G
i
S
ii
* are called optimum terminations. There-
fore,
0 G
i
G
imax
Values of G
i
that produce a constant gain G
i
lie in a circle on the Smith chart. These
circles are called constant gain circles.
We de®ne the normalized gain factor g
i
as follows:
g
i
G
i
G
imax
G
i
1 ÀjS
ii
j
2
10:3:3
Hence,
0 g
i
1
From (10.3.1) and (10.3.2), we can write
g
i
1 ÀjG
i
j
2
j1 À S
ii
G
i
j
2
1 ÀjS
ii
j
2
Ag
i
j1 À S
ii
G
i
j
2
1 ÀjG
i
j
2
1 ÀjS
ii
j
2
or,
g
i
1 À S
ii
G
i
1 À S*
ii
G
i
*1 ÀjS
ii
j
2
ÀjG
i
j
2
jG
i
j
2
jS
ii
j
2
CONSTANT GAIN CIRCLES
405
or,
g
i
1 À S
ii
G
i
À S*
ii
G
i
* jS
ii
j
2
jG
i
j
2
1 ÀjS
ii
j
2
ÀjG
i
j
2
1 ÀjS
ii
j
2
or,
g
i
jS*
ii
j
2
1 ÀjS
ii
j
2
jG
i
j
2
À g
i
S
ii
G
i
S
ii
*G
i
*1 À g
i
ÀjS
ii
j
2
or,
G
i
G
i
* À g
i
S
ii
G
i
S*
ii
G
i
*
1 À1 À g
i
jS
ii
j
2
g
2
i
jS
ii
j
2
1 À1 À g
i
jS
ii
j
2
2
1 À g
i
ÀjS
ii
j
2
1 À1 À g
i
jS
ii
j
2
g
2
i
jS
ii
j
2
1 À1 À g
i
jS
ii
j
2
2
Therefore,
G
i
À
g
i
S*
ii
1 À1 À g
i
jS
ii
j
2
2
1 À g
i
ÀjS
ii
j
2
1 À1 À g
i
jS
ii
j
2
jS
ii
j
2
g
2
i
1 À1 À g
i
jS
ii
j
2
2
10:3:4
which is the equation of a circle, with its center d
i
and radius R
i
given as follows:
d
i
g
i
S*
ii
1 À1 À g
i
jS
ii
j
2
10:3:5
and,
R
i
1 ÀjS
ii
j
2
1 À g
i
p
1 À1 À g
i
jS
ii
j
2
10:3:6
Example 10.4: S-parameters of a MESFET are given in the table below
(Z
o
50 O). Plot the constant gain circles at 4 GHz for G
L
0 dB and 1 dB, and
G
S
2 dB and 3 dB. Using these plots, design an ampli®er for a gain of 11 dB.
Calculate and plot its transducer power gain and input return loss in the frequency
band of 3 GHz to 5 GHz.
f (GHz) S
11
S
21
S
12
S
22
30:8À90
2:8 100
00:66À50
40:75À120
2:5 80
00:6À70
50:71À140
2:3 60
00:68À85
406
TRANSISTOR AMPLIFIER DESIGN
Since S
12
is zero, this transistor is unilateral. Hence,
k I; and jDj < 1; because jS
11
j < 1 and jS
22
j < 1
Therefore, it is unconditionally stable. From (9.4.14)±(9.4.16) we have
G
Smax
1
1 ÀjS
11
j
2
1
1 À 0:75
2
2:28857 3:59 dB
G
Lmax
1
1 ÀjS
22
j
2
1
1 À 0:6
2
1:5625 1:92 dB
and,
G
o
jS
21
j
2
2:5
2
6:25 7:96 dB
;G
TUmax
3:59 1:92 7:96 13:47 dB
Thus, maximum possible gain is 2.47 dB higher than the desired value of 11 dB.
Obviously, this transistor can be used for the present design.
The constant gain circles can be determined from (10.3.5) and (10.3.6). These
results are tabulated here.
G
S
3dB% 2 g
S
0:875 d
S
0:706 120
R
S
0:166
G
S
2dB 1:58 g
S
0:691 d
S
0:627 120
R
S
0:294
G
L
1dB 1:26 g
L
0:8064 d
L
0:52 70
R
L
0:303
G
L
0dB 1 g
L
0:64 d
L
0:44 70
R
L
0:44
As illustrated in Figure 10.10, the gain circles are drawn from this data. Since G
o
is found as 8 dB (approximately), the remaining 3 dB need to be obtained through
G
S
and G
L
. If we select G
S
as 3 dB then G
L
must be 0 dB. Alternatively, we can use
G
S
and G
L
as 2 dB and 1 dB, respectively, to obtain a transducer power gain of
7:96 2 1 % 11 dB.
Let us select point A on a 2-dB G
S
circle and design the input side network. The
corresponding admittance is found at point B, and therefore, a normalized capacitive
susceptance of j0:62 is needed in parallel with the source admittance to reach the
input VSWR circle. An open-ended, 0.09-l-long shunt-stub can be used for this. The
normalized admittance is now 1 j0:62. This admittance can be transformed to that
of point B by a 0.183-l-long section of transmission line. Similarly, point C can be
used to obtain G
L
1 dB. A normalized reactance of j0:48 in series with a 50-O
load can be used to synthesize this impedance. Alternatively, the corresponding
admittance point D is identi®ed. Hence, a shunt susceptance of Àj0:35 (an open-
circuit stub of 0:431 l) and then a transmission line length of 0:044 l can provide the
desired admittance. This circuit is illustrated in Figure 10.11.
CONSTANT GAIN CIRCLES
407
The return-loss is found by expressing jG
in
j in dB. Since
G
in
S
11
S
12
S
21
G
L
1 À S
22
G
L
and S
12
0, G
in
S
11
, therefore, jG
in
3 GHzj 0:8, jG
in
4 GHzj 0:75, and
jG
in
5 GHzj 0:71.
Return loss at 3 GHz 20 log
10
0:8À1:94 dB.
Return loss at 4 GHz 20 log
10
0:75À2:5dB.
Figure 10.11 RF circuit designed for Example 10.4.
Figure 10.10 Constant gain circles and the network design for Example 10.4.
408
TRANSISTOR AMPLIFIER DESIGN
Return loss at 5 GHz 20 log
10
0:71À2:97 dB.
Transducer power gain at 4 GHz is 11 dB (because we designed the circuit for this
gain). However, it will be different at other frequencies. We can evaluate it from
(9.4.16) as follows.
G
TU
1 ÀjG
S
j
2
j1 À S
11
G
S
j
2
? jS
21
j
2
?
1 ÀjG
L
j
2
j1 À S
22
G
L
j
2
Note that G
S
, G
L
, and S-parameters of the transistor are frequency dependent.
Therefore, we need to determine re¯ection coef®cients at other frequencies before
using the above formula. For a circuit designed with reactive discrete components,
the new reactances can be easily evaluated. The corresponding re¯ection coef®cients
can, in turn, be determined using the appropriate formula. However, we used
transmission lines in our design. Electrical lengths of these lines will be different
at other frequencies. We can calculate new electrical lengths by replacing l as
follows:
l 3
f
new
f
design
l
new
At 3 GHz, original lengths must be multiplied by 3=4 0:75 to adjust for the
change in frequency. Similarly, it must be multiplied by 5=4 1:25 for 5 GHz. The
new re¯ection coef®cients can be determined using the Smith chart. The results are
summarized below.
G
S
CALCULATIONS:
Lengths at 4 GHz 3 GHz 5 GHz
Lengths and G
S
Lengths and G
S
0.09 0.068 0:24 158
0.113 0:41 81
0.183 0.137 0.229
G
L
CALCULATIONS:
Lengths at 4 GHz 3 GHz 5 GHz
Lengths and G
L
Lengths and G
L
0.044 0.033 0:72 109
0.055 0:15À151
0.431 0.323 0.539
CONSTANT GAIN CIRCLES
409
