Tài liệu ARM Architecture Reference Manual- P14 ppt

Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-87
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Alignment If the memory address is not word-aligned and no data abort occurs, the value written to
memory is
UNPREDICTABLE.
If an implementation includes a System Control coprocessor (see Chapter B2 The System
Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00
causes an alignment exception (a type of data abort).
Equivalent ARM syntax and encoding
STR <Rd>, [<Rn>, #<immed_5> * 4]
31302928272625242322212019 1615 1211109876 210
111001011000 Rn Rd 00000 immed_5 00
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Thumb Instructions
A7-88
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.53 STR (2)
This form of STR allows 32-bit data from a general-purpose register to be stored to memory. The addressing
mode is useful for pointer + large offset arithmetic, and for accessing a single element of an array.
Syntax
STR <Rd>, [<Rn>, <Rm>]
where:
<Rd> Is the register that contains the word to be stored to memory.
<Rn> Is the register containing the first value used in forming the memory address.
<Rm> Is the register containing the second value used in forming the memory address.

Architecture version
All T variants
Exceptions
Data Abort
Operation
address = Rn + Rm
if address[1:0] == 0b00
Memory[address,4] = Rd
else
Memory[address,4] = UNPREDICTABLE
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Alignment If the memory address is not word-aligned and no data abort occurs, the value written to
memory is
UNPREDICTABLE.
If an implementation includes a System Control coprocessor (see Chapter B2 The System
Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00
causes an alignment exception (a type of data abort).
15 14 13 12 11 10 9 8 6 5 3 2 0
0101000 Rm Rn Rd
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-89
Equivalent ARM syntax and encoding
STR <Rd>, [<Rn>, <Rm>]
31302928272625242322212019 1615 1211109876543 0
111001111000 Rn Rd 00000000 Rm

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Thumb Instructions
A7-90
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.54 STR (3)
This form of STR allows 32-bit data from a general-purpose register to be stored to memory. The addressing
mode is useful for accessing stack data. In this case, STR stores a word from register <Rd> to memory.
Syntax
STR <Rd>, [SP, #<immed_8> * 4]
where:
<Rd> Is the register that contains the word to be stored to memory.
SP Is the stack pointer. Its value is used to calculate the memory address.
<immed_8> Is an 8-bit value that is multiplied by 4 and added to the value of the SP to form the memory
address.
Architecture version
All T variants
Exceptions
Data Abort
Operation
address = SP + (immed_8 * 4)
if address[1:0] == 0b00
Memory[address,4] = Rd
else
Memory[address,4] = UNPREDICTABLE
15 14 13 12 11 10 8 7 0
10010 Rd immed_8
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Thumb Instructions
ARM DDI 0100E

Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-91
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Alignment If the memory address is not word-aligned and no data abort occurs, the value written to
memory is
UNPREDICTABLE.
If an implementation includes a System Control coprocessor (see Chapter B2 The System
Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00
causes an alignment exception (a type of data abort).
Equivalent ARM syntax and encoding
STR <Rd>, [SP, #<immed_8> * 4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 2 1 0
1110010110001101 Rd 00 immed_8 00
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Thumb Instructions
A7-92
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.55 STRB (1)
This form of the STRB (Store Register Byte) instruction allows 8-bit data from a general-purpose register
to be stored to memory. The addressing mode is useful for accessing structure (record) fields.
With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
STRB <Rd>, [<Rn>, #<immed_5>]
where:
<Rd> Is the register whose least significant byte is stored to memory.
<Rn> Is the register containing the base address for the instruction.
<immed_5> Is a 5-bit immediate value that is added to the value of <Rn> to form the memory address.

Architecture version
All T variants
Exceptions
Data Abort
Operation
address = Rn + immed_5
Memory[address,1] = Rd[7:0]
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Equivalent ARM syntax and encoding
STRB <Rd>, [<Rn>, #<immed_5>]
15 14 13 12 11 10 6 5 3 2 0
01110 immed_5 Rn Rd
31302928272625242322212019 1615 121110987654 0
111001011100 Rn Rd 0000000 immed_5
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-93
7.1.56 STRB (2)
This form of STRB allows 8-bit data from a general-purpose register to be stored to memory. The
addressing mode is useful for pointer + large offset arithmetic, and for accessing a single element of an
array.
Syntax
STRB <Rd>, [<Rn>, <Rm>]
where:
<Rd> Is the register whose least significant byte is stored to memory.
<Rn> Is the register containing the first value used in forming the memory address.

<Rm> Is the register whose value is added to <Rn> to form the memory address.
Architecture version
All T variants
Exceptions
Data Abort
Operation
address = Rn + Rm
Memory[address,1] = Rd[7:0]
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Equivalent ARM syntax and encoding
STRB <Rd>, [<Rn>, <Rm>]
15 14 13 12 11 10 9 8 6 5 3 2 0
0101010 Rm Rn Rd
31302928272625242322212019 1615 1211109876543 0
111001111100 Rn Rd 00000000 Rm
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Thumb Instructions
A7-94
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.57 STRH (1)
This form of the STRH (Store Register Halfword) instruction allows 16-bit data from a general-purpose
register to be stored to memory. The addressing mode is useful for accessing structure (record) fields. With
an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
STRH <Rd>, [<Rn>, #<immed_5> * 2]
where:
<Rd> Is the register whose least significant halfword is stored to memory.

<Rn> Is the register containing the base address for the instruction.
<immed_5> Is a 5-bit immediate value that is multiplied by two and added to the value of <Rn> to form
the memory address.
Architecture version
All T variants
Exceptions
Data Abort
Operation
address = Rn + (immed_5 * 2)
if address[1:0] == 0
Memory[address,2] = Rd[15:0]
else
Memory[address,2] = UNPREDICTABLE
15 14 13 12 11 10 6 5 3 2 0
10000 immed_5 Rn Rd
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-95
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Alignment If the memory address is not halfword-aligned and no data abort occurs, the value written
to memory is
UNPREDICTABLE.
If an implementation includes a System Control coprocessor (see Chapter B2 The System
Control Coprocessor) and alignment checking is enabled, an address with bit[0] != 0 causes
an alignment exception (a type of data abort).
Equivalent ARM syntax and encoding

STRH <Rd>, [<Rn>, #<immed_5> * 2]
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 1 0
111000011100 Rn Rd 00
immed
[4:3]
1011
immed
[2:0]
0
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Thumb Instructions
A7-96
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.58 STRH (2)
This form of STRH allows 16-bit data from a general-purpose register to be stored to memory. The
addressing mode is useful for pointer + large offset arithmetic and for accessing a single element of an array.
Syntax
STRH <Rd>, [<Rn>, <Rm>]
where:
<Rd> Is the register whose least significant halfword is stored to memory.
<Rn> Is the register containing the first value used in forming the memory address.
<Rm> Is the register whose value is added to <Rn> to form the memory address.
Architecture version
All T variants
Exceptions
Data Abort
Operation
address = Rn + Rm
if address[1:0] == 0

Memory[address,2] = Rd[15:0]
else
Memory[address,2] = UNPREDICTABLE
Notes
Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted
instructions on page A2-17.
Alignment If the memory address is not halfword-aligned and no data abort occurs, the value written
to memory is
UNPREDICTABLE
If an implementation includes a System Control coprocessor (see Chapter B2 The System
Control Coprocessor) and alignment checking is enabled, an address with bit[0] != 0 causes
an alignment exception (a type of data abort).
15 14 13 12 11 10 9 8 6 5 3 2 0
0101001 Rm Rn Rd
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-97
Equivalent ARM syntax and encoding
STRH <Rd>, [<Rn>, <Rm>]
31302928272625242322212019 1615 1211 876543210
111000011000 Rn Rd SBZ 1011 Rm
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Thumb Instructions
A7-98
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.59 SUB (1)
This form of the SUB (Subtract) instruction subtracts a small constant value from the value of a register and

stores the result in a second register. The condition code flags are updated, based on the result.
Syntax
SUB <Rd>, <Rn>, #<immed_3>
where:
<Rd> Is the destination register for the operation.
<Rn> Is the register containing the first operand for the subtraction.
<immed_3> Is a 3-bit immediate value (values 0 to 7) that is subtracted from <Rn>.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rn - immed_3
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = NOT BorrowFrom(Rn - immed_3)
V Flag = OverflowFrom(Rn - immed_3)
Equivalent ARM syntax and encoding
SUBS <Rd>, <Rn>, #<immed_3>
15 14 13 12 11 10 9 8 6 5 3 2 0
0001111 immed_3 Rn Rd
31302928272625242322212019 1615 12111098765432 0
111000100101 Rn Rd 000000000immed_3
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-99
7.1.60 SUB (2)
This form of SUB subtracts a large immediate value from the value of a register and stores the result back

in the same register. The condition code flags are updated, based on the result.
Syntax
SUB <Rd>, #<immed_8>
where:
<Rd> Is the register containing the first operand for the subtraction, and is also the
destination register for the operation.
<immed_8> Is an 8-bit immediate value (values 0 to 255) that is subtracted from <Rd>.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rd - immed_8
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = NOT BorrowFrom(Rd - immed_8)
V Flag = OverflowFrom(Rd - immed_8)
Equivalent ARM syntax and encoding
SUBS <Rd, <Rd>, #<immed_8>
15 14 13 12 11 10 8 7 0
00111 Rd immed_8
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 0
111000100101 Rd Rd 0000 immed_8
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Thumb Instructions
A7-100
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.61 SUB (3)
This form of SUB subtracts the value of one register from the value of a second register and stores the result

in a third register. The condition code flags are updated, based on the result.
Syntax
SUB <Rd>, <Rn>, <Rm>
where:
<Rd> Is the destination register for the operation.
<Rn> Is the register containing the first operand for the subtraction.
<Rm> Is the register whose value is subtracted from <Rn>.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rn - Rm
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = NOT BorrowFrom(Rn - Rm)
V Flag = OverflowFrom(Rn - Rm)
Equivalent ARM syntax and encoding
SUBS <Rd>, <Rn>, <Rm>
15 14 13 12 11 10 9 8 6 5 3 2 0
0001101 Rm Rn Rd
31302928272625242322212019 1615 1211109876543 0
111000000101 Rn Rd 00000000 Rm
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-101
7.1.62 SUB (4)
This form of SUB decrements the SP by four times a 7-bit immediate (that is, by a multiple of 4 in the range

0 to 508). The condition codes are not affected.
Syntax
SUB SP, #<immed_7> * 4
where:
SP Indicates the stack pointer. The result of the operation is also stored in the SP.
<immed_7> Is a 7-bit immediate value that is multiplied by 4 and then subtracted from the value
of the stack pointer.
Architecture version
All T variants
Exceptions
None
Operation
SP = SP - (immed_7 << 2)
Usage
For the Full Descending stack which the Thumb instruction set is designed to use, decrementing the SP is
used to allocate extra memory variables on the top of the stack.
Notes
Alternative syntax This instruction can also be written as SUB SP, SP, #<immed_7> * 4.
Equivalent ARM syntax and encoding
SUB SP, SP, #<immed_7> * 4
15 14 13 12 11 10 9 8 7 6 0
101100001 immed_7
313029282726252423222120191817161514131211109876 0
1110001001001101110111110 immed_7
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Thumb Instructions
A7-102
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.63 SWI

The SWI (Software Interrupt) instruction is used as an operating system service call. A SWI exception is
generated, which is handled by an operating system to provide the requested service. See Exceptions on
page A2-13.
Syntax
SWI <immed_8>
where:
<immed_8> Is an 8-bit immediate value that is put into bits[7:0] of the instruction. This value is
ignored by the processor, but can be used by an operating system’s SWI exception
handler to determine which operating system service is being requested.
Architecture version
All T variants
Exceptions
Software Interrupt
Operation
R14_svc = address of next instruction after the SWI instruction
SPSR_svc = CPSR
CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
CPSR[5] = 0 /* Execute in ARM state */
/* CPSR[6] is unchanged */
CPSR[7] = 1 /* Disable normal interrupts */
if high vectors configured then
PC = 0xFFFF0008
else
PC = 0x00000008
Equivalent ARM syntax and encoding
SWI <immed_8>
15 14 13 12 11 10 9 8 7 0
11011111 immed_8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 0
111011110000000000000000 immed_8

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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-103
7.1.64 TST
The TST (Test) instruction is used to determine whether a particular subset of bits in a register includes at
least one set bit. A very common use for TST is to test whether a single bit is set or clear. The condition
code flags are updated, based on the result.
Syntax
TST <Rn>, <Rm>
where:
<Rn> Is the register containing the first operand for the instruction.
<Rm> Is the register whose value is logically ANDed with the value of <Rn>.
Architecture version
All T variants
Exceptions
None
Operation
alu_out = Rn AND Rm
N Flag = alu_out[31]
Z Flag = if alu_out == 0 then 1 else 0
C Flag = unaffected
V Flag = unaffected
Equivalent ARM syntax and encoding
TST <Rn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0100001000 Rm Rn
31302928272625242322212019 1615 1211109876543 0
111000010001 Rn SBZ 00000000 Rm

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Thumb Instructions
A7-104
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.2 Thumb instructions and architecture versions
Table 7-1 shows which Thumb instructions are present in each current ARM architecture version that
supports Thumb.
Table 7-1 Thumb instructions by architecture
Instruction v4T, v4TxM v5T, v5TxM
ADC Ye s Ye s
ADD (all forms) Yes Yes
AND Yes Yes
ASR (both forms) Yes Yes
B (both forms) Yes Yes
BIC Yes Yes
BKPT No Yes
BL Yes Yes
BLX (both forms) No Yes
BX Yes Yes
CMN Yes Yes
CMP (all forms) Yes Yes
EOR Yes Yes
LDMIA Yes Yes
LDR (all forms) Yes Yes
LDRB (both forms) Yes Yes
LDRH (both forms) Yes Yes
LDRSB Ye s Yes
LDRSH Ye s Yes
LSL (both forms) Yes Yes

LSR (both forms) Yes Yes
MOV (all forms) Yes Yes
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-105
MUL Yes Yes
MVN Yes Yes
NEG Yes Yes
ORR Yes Yes
POP Yes Yes
PUSH Yes Yes
ROR Yes Yes
SBC Yes Yes
STMIA Yes Yes
STR (all forms) Yes Yes
STRB (both forms) Yes Yes
STRH (both forms) Yes Yes
SUB (all forms) Yes Yes
SWI Ye s Ye s
TST Ye s Ye s
Table 7-1 Thumb instructions by architecture
(Continued)
Instruction v4T, v4TxM v5T, v5TxM
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Thumb Instructions
A7-106
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E

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ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A8-1
Chapter A8
The 26-bit Architectures
This chapter describes the differences between the 32-bit and 26-bit architectures. It contains the following
sections:
• Overview of the 26-bit architectures on page A8-2
• Format of register 15 on page A8-4
• 26-bit PSR update instructions on page A8-6
• Address exceptions on page A8-8
• Backwards compatibility from 32-bit architectures on page A8-9.
Note
The information in this chapter is to help with backwards-compatibility issues in existing systems.
Programmers starting new projects are strongly encouraged to use only the 32-bit facilities.
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The 26-bit Architectures
A8-2
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
8.1 Overview of the 26-bit architectures
ARMv1, ARMv2, and ARMv2a are earlier versions of the ARM architecture which implement only a 26-bit
address space, and are known as 26-bit architectures.
ARM architecture version 3 and above implement a 32-bit address space and are known as 32-bit
architectures. For backwards compatibility:
• except for ARMv3G, all variants of ARM architecture version 3 implement the 26-bit address space
• all non-T variants of ARM architecture version 4 and above can optionally implement the 26-bit
address space.
This chapter describes the differences between the 26-bit and 32-bit architectures, and how the

backwards-compatibility features are used.
There are several differences between the 26-bit and the 32-bit architectures:
Program counter The 26-bit architectures implement only a 24-bit program counter in R15, which
allows 64MB of program space. The 32-bit architectures have a 30-bit program
counter in R15 which allows 4GB of program space on 32-bit architectures.
Processor modes Only four processor modes are supported on 26-bit architectures:
• User (0b00)
• FIQ (0b01)
• IRQ (0b10)
• Supervisor (0b11).
Register 15 In the 26-bit architectures, the following are also stored in register 15:
• four condition flags (N, Z, C and V)
• the interrupt disable flags (I and F)
• two processor mode bits (M1 and M0).
CPSR/SPSR The 26-bit architectures do not have a CPSR or any SPSRs.
Exceptions An exception (called an address exception) is raised if a memory access instruction
uses an address that is greater than 2
26
–1 bytes.
Branches In 26-bit architectures, there are no restrictions on branching backwards past
location 0x0000000 or forwards past location 0x3FFFFFF. Such branches wrap
around to the other end of the 26-bit address space, and so have a different target
address than they would have had in a 32-bit architecture.
As a result, the signed 24-bit word offset in the B and BL instructions allows any
instruction in the 26-bit address space to be branched to.
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The 26-bit Architectures
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A8-3

Together, these differences make up the fundamental distinction between 26-bit and 32-bit architectures:
26-bit architectures
All process status (namely the condition flags, interrupt status and processor mode) can be
preserved across subroutine calls and nested exceptions without adding any instructions to
the entry or exit sequence.
32-bit architectures
This process status functionality is given up to allow 32-bit instruction addresses to be used.
For exceptions, processor status is preserved in the SPSRs, and if nested exceptions using
the same SPSR can occur, extra instructions are used to preserve this status in memory. For
subroutine calls, processor status can be preserved across the subroutine call by using extra
instructions, but this is not normally done.
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The 26-bit Architectures
A8-4
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
8.2 Format of register 15
Bits[25:2] are collectively known as the Program Counter (PC). Because the PC occupies only 24 bits of
register 15, only 2
24
instructions (2
26
bytes) can be addressed, giving a maximum addressable program size
of 64MB.
Bits[31:26] and bits[1:0] are collectively known as the Program Status Register (PSR).
The N, Z, C, V, I, and F bits have the same meaning in both 26-bit and 32-bit architectures. M[1:0] also have
the same meaning in both architectures.
Abort, Undefined, and System mode are not supported in 26-bit architectures. Aborts and Undefined
Instruction exceptions have exactly the same actions in both modes, except that in 26-bit architectures,
Supervisor mode is entered instead of Abort or Undefined mode.

The precise effect of an exception on a 26-bit architecture can be derived from the rules in Exceptions on
page A2-13, as follows:
• The banked version of R14 has bits[25:2] set to the specified address, and bits[31:26, 1, 0] set to
copies of the corresponding bits in R15.
• The I, F, M1, and M0 bits are modified in the same way as CPSR[7], CPSR[6], CPSR[1], and
CPSR[0] respectively, on a 32-bit architecture.
The I, F and M[1:0] bits cannot be written directly when the processor is in User mode. In User mode they
are only changed by an exception occurring.
8.2.1 Reading register 15
In 26-bit architectures, the value of R15 is read in five different ways:
• Most importantly, if R15 has an
UNPREDICTABLE value in the 32-bit architecture, it also has an
UNPREDICTABLE value when used in the same way in the 26-bit architecture.
• If R15 is specified in bits[19:16] of an instruction (and its value is not
UNPREDICTABLE), only the PC
(bits[25:2]) is used. All other bits read as zero.
• If R15 is specified in bits[3:0] of an instruction (and its value is not
UNPREDICTABLE), all 32 bits are
used.
• If R15 is stored using STR or STM, the value of the PC (bits[25:2]) is
IMPLEMENTATION DEFINED, but
all 32 bits of the register are stored.
• All 32 bits are stored in the Link register (R14) after a Branch with Link instruction or an exception
entry.
31 30 29 28 27 26 25 210
N Z C V I F Program Counter M1M0
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The 26-bit Architectures
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.

A8-5
8.2.2 Writing register 15
In 26-bit architectures, the value of R15 is written in three different ways:
• The following instructions only write the PC part of R15, leaving the PSR part unchanged:
— Data-processing instructions without the S bit set
—LDR instructions
— LDM instructions, other than Load Multiple with Restore CPSR.
• The following instructions write both the PC and the PSR part of R15:
— Data-processing instructions with the S bit set
— Load Multiple with Restore CPSR.
• Variants of the CMP, CMN, TST, and TEQ instructions write just the PSR part of R15 and leave the
PC part unchanged. These instruction variants are described 26-bit PSR update instructions on
page A8-6.
These read/write rules mean that R15 is used in three basic ways:
• When it is the Rn specifier in data-processing instructions, or the base address for load and store
instructions, only the value of the program counter is used, to simplify PC-relative addressing and
position-independent code.
• When it is the Rm specifier in data-processing instructions, all 32 bits are used in order to allow all
process status to be restored after a subroutine call or exception by subroutine-return instructions
such as:
MOVS PC, LR and LDM , PC}^
These instructions are UNPREDICTABLE in User mode on 32-bit architectures, but are legal on 26-bit
architectures, as they are used to restore the condition code flags on procedure exit.
• All 32 bits are saved in the Link register, to preserve the PC and the PSR across subroutine calls and
exceptions.
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