ARM Architecture Reference Manual- P25

VFP Instructions

Notes
Vectors

When the LEN field of the FPSCR indicates scalar mode (vector length 1), FSQRTS
performs just one square root operation, and vec_len=1, Sd[0]=Sd, and Sm[0]=Sm.
When the LEN field indicates a vector mode (vector length > 1), FSQRTS might perform
more than one square root operation. Addressing Mode 3 - Single-precision vectors
(monadic) on page C5-14 describes how FSQRTS encodes the registers it uses and how
vec_len, Sd[i], and Sm[i] are determined.

Rounding

ARM DDI 0100E

This is a fully-rounded square root operation. The FPSCR determines the rounding mode.

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C4-93


VFP Instructions

4.1.51

FSTD
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 0 1 U 0 0 0

16 15

Rn

12 11 10 9 8

Dd

7

6

1 0 1 1

5

4 3

0

offset

The FSTD (Floating-point Store, Double-precision) instruction stores a double-precision register to

memory.

Syntax
FSTD{<cond>}

<Dd>, [<Rn>{, #+/-(<offset>*4)}]

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Dd>

Specifies the source register.

<Rn>

Specifies the register holding the base address for the transfer.

<offset>

Specifies an offset to be multiplied by 4, then added to the base address (if U == 1) or
subtracted from it (if U == 0) to form the actual address of the transfer. If offset is
omitted, it defaults to +0.

Architecture version
D variants only

Exceptions
Data Abort

Operation
if ConditionPassed(cond) then
if (U == 1)
address = Rn + offset * 4
else
address = Rn - offset * 4
if (big-endian)
Memory[address,4] = Dd[63:32]
Memory[address+4,4] = Dd[31:0]
else
Memory[address,4] = Dd[31:0]
Memory[address+4,4] = Dd[63:32]

C4-94

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ARM DDI 0100E


VFP Instructions

Notes
Addressing mode
This is a special case of Addressing Mode 5 - VFP load/store multiple on page C5-24.

Conversions

ARM DDI 0100E

An implementation using an internal format for double-precision values must convert that
format back to the external double-precision format. Otherwise, no conversion is required.

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C4-95


VFP Instructions

4.1.52

FSTMD
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 0 P U 0 W 0

16 15

Rn

12 11 10 9 8

Dd

7

6

1 0 1 1

5

4 3

0

offset

The FSTMD (Floating-point Store Multiple, Double-precision) instruction stores a sequence of consecutive
double-precision registers to memory.

Syntax
FSTM<addressing_mode>D{<cond>}

<Rn>{!}, <registers>

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<addressing_mode>
Specifies the addressing mode, which determines the values of start_address and
end_address used by the instruction. See Addressing Mode 5 - VFP load/store multiple
on page C5-24 for details.
<Rn>

Specifies the base register used by <addressing_mode>.

!

Sets the W bit of the instruction to 1, specifying that the base register <Rn> is to be updated
by the instruction. If it is omitted, the W bit of the instruction is set to 0 and the base register
<Rn> is left unchanged. Some combinations of <addressing_mode> and the presence
or absence of ! are not allowed. For details, see Addressing Mode 5 - VFP load/store
multiple on page C5-24.

<registers>
Specifies which registers are to be stored, as a list of consecutively numbered
double-precision registers, separated by commas and surrounded by brackets. It is encoded
in the instruction by setting Dd to the number of the first register in the list, and offset to
twice the number of registers in the list. At least one register must be specified in the list.
For example, if <registers> is {D2,D3,D4}, the Dd field of the instruction is 2 and
the offset field is 6.

Architecture version
D variants only

Exceptions
Data Abort

C4-96

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ARM DDI 0100E


VFP Instructions

Operation
if ConditionPassed(cond) then
address = start_address
for i = 0 to (offset-2)/2
/* d is the number of register Dd;
*/
/* D(n) is the double-precision register numbered n */
if (big-endian)
Memory[address,4] = D(d+i)[63:32]
Memory[address+4,4] = D(d+i)[31:0]
else
Memory[address,4] = D(d+i)[31:0]
Memory[address+4,4] = D(d+i)[63:32]
address = address + 8
assert end_address = address - 4

Notes
Encoding

If P=1 and W=0, the instruction is instead an FSTD instruction. Otherwise, if offset is odd,
the instruction is instead an FSTMX instruction.

Vectors

The FSTMD instruction is unaffected by the LEN and STRIDE fields of the FPSCR, and
does not wrap around at bank boundaries in the way that vector operands to data-processing
instructions do. Registers are stored in simple increasing order of register number.

Invalid register lists
If Dd and offset do not specify a valid register list, the instruction is UNPREDICTABLE.
This happens in two cases:
•
•
Conversions

ARM DDI 0100E

if offset == 0, that is, if an attempt is made to transfer no registers
if d + offset/2 > 16, that is, if an attempt is made to transfer another register
after D15.

If an implementation uses an internal format for double-precision values, it must convert
that format back to the external double-precision format. Otherwise, no conversion is
required.

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C4-97


VFP Instructions

4.1.53

FSTMS
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 0 P U D W 0

16 15

Rn

12 11 10 9 8

Fd

7

6

1 0 1 0

5

4 3

0

offset

The FSTMS (Floating-point Store Multiple, Single-precision) instruction stores a sequence of consecutive
single-precision registers to memory.

Syntax
FSTM<addressing_mode>S{<cond>}

<Rn>{!}, <registers>

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<addressing_mode>
Specifies the addressing mode, which determines the values of start_address and
end_address used by the instruction. See Addressing Mode 5 - VFP load/store multiple
on page C5-24.
<Rn>

Specifies the base register used by <addressing_mode>.

!

Sets the W bit of the instruction to 1, specifying that the base register <Rn> is to be updated
by the instruction. If it is omitted, the W bit of the instruction is set to 0 and the base register
<Rn> is left unchanged. Some combinations of <addressing_mode> and the presence
or absence of ! are not allowed. For details, see Addressing Mode 5 - VFP load/store
multiple on page C5-24.

<registers>
Specifies which registers are to be stored, as a list of consecutively numbered
single-precision registers, separated by commas and surrounded by brackets. If d is the
number of the first register in the list, the list is encoded in the instruction by setting Fd and
D to the top 4 bits and the bottom bit respectively of d, and offset to the number of
registers in the list. At least one register must be specified in the list.
For example, if <registers> is {S5,S6,S7}, the Fd field of the instruction is 0b0010,
the D bit will be 1 and the offset field is 3.

Architecture version
All

Exceptions
Data Abort

C4-98

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ARM DDI 0100E


VFP Instructions

Operation
if ConditionPassed(cond) then
address = start_address
for i = 0 to offset-1
/* d is as defined for <registers> above;
*/
/* S(n) is the single-precision register numbered n */
Memory[address,4] = S(d+i)
address = address + 4
assert end_address = address - 4

Notes
Encoding

If P=1 and W=0, the instruction is instead an FSTS instruction.

Vectors

The FSTMS instruction is unaffected by the LEN and STRIDE fields of the FPSCR, and
does not wrap around at bank boundaries in the way that vector operands to data-processing
instructions do. Registers are stored in simple increasing order of register number.

Invalid register lists

If Fd, Dd and offset do not specify a valid register list, the instruction is UNPREDICTABLE.
This happens in two cases:
•
•
Conversions

if offset == 0, that is, if an attempt is made to transfer no registers
if d + offset > 32, that is, if an attempt is made to transfer another register after
S31.

In the programmer’s model is that FSTMS does not perform any conversion on the value
transferred. The source registers can each contain either a single-precision floating-point
number or an integer. The latter is typically obtained as the result of one of the
floating-point-to-integer conversion instructions.
Implementations are free to hold the values in the source registers in an internal format,
provided that FSTMS converts it to external format and this conversion recovers the correct
data, regardless of whether the register contains a single-precision floating-point number or
an integer.

ARM DDI 0100E

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C4-99


VFP Instructions

4.1.54

FSTMX
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 0 P U 0 W 0

16 15

Rn

12 11 10 9 8

Dd

7

6

1 0 1 1

5

4 3

0

offset

The FSTMX (Floating-point Store Multiple, Unknown precision) instruction stores a sequence of
consecutive double-precision registers to memory, in an IMPLEMENTATION DEFINED format that allows the
registers to be reloaded correctly regardless of whether they contain integers, single-precision values or
double-precision values.

Syntax
FSTM<addressing_mode>X{<cond>}

<Rn>{!}, <registers>

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<addressing_mode>
Specifies the addressing mode, which determines the values of start_address and
end_address used by the instruction. See Addressing Mode 5 - VFP load/store multiple
on page C5-24 for details.
<Rn>

Specifies the base register used by <addressing_mode>.

!

Sets the W bit of the instruction to 1, specifying that the base register <Rn> is to be updated

by the instruction. If it is omitted, the W bit of the instruction is set to 0 and the base register
<Rn> is left unchanged. Some combinations of <addressing_mode> and the presence
or absence of ! are not allowed. For details, see Addressing Mode 5 - VFP load/store
multiple on page C5-24.

<registers>
Specifies which registers are to be stored, as a list of consecutively numbered
double-precision registers, separated by commas and surrounded by brackets. It is encoded
in the instruction by setting Dd to the number of the first register in the list, and offset to
twice the number of registers in the list plus 1. At least one register must be named in the list.
For example, if <registers> is {D2,D3,D4}, the Dd field of the instruction is 2 and
the offset field is 7.

Architecture version
All

Exceptions
Data Abort

C4-100

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ARM DDI 0100E


VFP Instructions

Operation
if ConditionPassed(cond) then
/* d is the number of register Dd;
*/
/* D(n) is the double-precision register numbered n */
Store registers D(d) to D(d+(offset-3)/2) to memory words
Memory[start_address,4] through to Memory[end_address-4,4]

Usage
FSTMX is used to save VFP register values to memory in circumstances where it is unknown what type of
data they contain. Typical cases of this are:
•
in procedure entry sequences when a callee-save procedure calling standard is being used
•
in process swap code.

Notes
Encoding

If P=1 and W=0, the instruction is instead an FSTD instruction. Otherwise, if offset is
even, the instruction is instead an FSTMD instruction.

Vectors

The FSTMX instruction is unaffected by the LEN and STRIDE fields of the FPSCR, and
does not wrap around at bank boundaries in the way that vector operands to data-processing
instructions do. Registers are stored in simple increasing order of register number.

Invalid register lists
If Dd and offset do not specify a valid register list, the instruction is UNPREDICTABLE.

This happens in two cases:
•

if offset == 0, that is, if an attempt is made to transfer no registers

•

if d + (offset-1)/2 > 16, that is, if an attempt is made to transfer another
register after D15.

Memory format
The memory format used is IMPLEMENTATION DEFINED. The only requirements on it are:
•

A matching FLDMX instruction must reload the registers correctly, regardless of
whether they originally contained integers, single-precision values or
double-precision values. For an FLDMX instruction and an FSTMX instruction to
count as matching, they must specify identical register lists and must generate the
same start_address and end_address when executed.

•

It must not use more than the allowed number of memory words, that is, 2N+1
memory words for storing N double-precision registers.

Non implementation-specific code must not do anything with the results of an FSTMX
except reload it with a matching FLDMX instruction.

ARM DDI 0100E

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C4-101


VFP Instructions

4.1.55

FSTS
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 0 1 U D 0 0

16 15

Rn

12 11 10 9 8

Fd

7

6

1 0 1 0

5

4 3

0

offset

The FSTS (Floating-point Store, Single-precision) instruction stores a single-precision register to memory.

Syntax
FSTS{<cond>}

<Sd>, [<Rn>{, #+/-(<offset>*4)}]

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the source register. Its number is encoded as Fd (top 4 bits) and D (bottom bit).

<Rn>

Specifies the register holding the base address for the transfer.

<offset>

Specifies an offset to be multiplied by 4, then added to the base address (if U == 1) or
subtracted from it (if U == 0) in order to form the actual address of the transfer. If this
offset is omitted, it defaults to +0.

Architecture version
All

Exceptions
Data Abort

Operation
if ConditionPassed(cond) then
if (U == 1)
address = Rn + offset * 4
else
address = Rn - offset * 4
Memory[address,4] = Sd

C4-102

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ARM DDI 0100E

VFP Instructions

Notes
Addressing mode
This is a special case of Addressing Mode 5 - VFP load/store multiple on page C5-24.
Conversions

In the programmer’s model, FSTS does not perform any conversion on the value
transferred. The source register Sd can contain either a single-precision floating-point
number or an integer. The latter is typically obtained as the result of one of the
floating-point-to-integer conversion instructions.
Implementations are free to hold the value in Sd in an internal format, provided that FSTS
converts it to an external format and this conversion recovers the correct data, whether or
not Sd contains a single-precision floating-point number or an integer.

ARM DDI 0100E

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C4-103


VFP Instructions

4.1.56

FSUBD
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 1 0 0 0 1 1

16 15

Dn

12 11 10 9 8

Dd

7

6

5

4 3

1 0 1 1 0 1 0 0

0

Dm

The FSUBD (Floating-point Subtract, Double-precision) instruction subtracts one double-precision register
from another double-precision register and writes the result to a third double-precision register. It can also
perform a vector version of this operation.

Syntax
FSUBD{<cond>}

<Dd>, <Dn>, <Dm>

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Dd>

Specifies the destination register.

<Dn>

Specifies the register that contains the first operand for the subtraction.

<Dm>

Specifies the register that contains the second operand for the subtraction.

Architecture version
D variants only

Exceptions
Floating-point exceptions: Invalid Operation, Overflow, Inexact

Operation
if ConditionPassed(cond) then
for i = 0 to vec_len-1
Dd[i] = Dn[i] - Dm[i]

C4-104

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ARM DDI 0100E


VFP Instructions

Notes
Vectors

When the LEN field of the FPSCR indicates scalar mode (vector length 1), FSUBD performs
just one subtraction, and vec_len=1, Dd[0]=Dd, Dn[0]=Dn, and Dm[0]=Dm.
When the LEN field indicates a vector mode (vector length > 1), FSUBD might perform
more than one subtraction. Addressing Mode 2 - Double-precision vectors (non-monadic)
on page C5-8 describes how FSUBD encodes the registers it uses and how vec_len,
Dd[i], Dn[i], and Dm[i] are determined.

Rounding

ARM DDI 0100E

This is a fully-rounded subtraction. The rounding mode is determined by the FPSCR.

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C4-105


VFP Instructions

4.1.57

FSUBS
31

28 27 26 25 24 23 22 21 20 19

cond

1 1 1 0 0 D 1 1

16 15

Fn

12 11 10 9 8

Fd

7

6

5

4 3

1 0 1 0 N 1 M 0

0

Fm

The FSUBS (Floating-point Subtract, Single-precision) instruction subtracts one single-precision register
from another single-precision register and writes the result to a third single-precision register. It can also
perform a vector version of this operation.

Syntax
FSUBS{<cond>}

<Sd>, <Sn>, <Sm>

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the destination register. Its number is encoded as Fd (top 4 bits) and D (bottom
bit).

<Sn>

Specifies the register that contains the first operand for the subtraction. The register number
is encoded as Fn (top 4 bits) and N (bottom bit).

<Sm>

Specifies the register that contains the second operand for the subtraction. The register
number is encoded as Fm (top 4 bits) and M (bottom bit).

Architecture version
All

Exceptions
Floating-point exceptions: Invalid Operation, Overflow, Inexact

Operation
if ConditionPassed(cond) then
for i = 0 to vec_len-1
Sd[i] = Sn[i] - Sm[i]

C4-106

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ARM DDI 0100E


VFP Instructions

Notes
Vectors

When the LEN field of the FPSCR indicates scalar mode (vector length 1), FSUBS performs
one subtraction, and vec_len=1, Sd[0]=Sd, Sn[0]=Sn, and Sm[0]=Sm.
When the LEN field indicates a vector mode (vector length > 1), FSUBS might perform
more than one subtraction. Addressing Mode 1 - Single-precision vectors (non-monadic) on
page C5-2 describes how FSUBS encodes the registers it uses and how vec_len, Sd[i],
Sn[i], and Sm[i] are determined.

Rounding

ARM DDI 0100E

The operation is a fully-rounded subtraction. Rounding mode is determined by the FPSCR.

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C4-107


VFP Instructions

4.1.58

FTOSID
31

28 27 26 25 24 23 22 21 20 19

cond

16 15

1 1 1 0 1 D 1 1 1 1 0 1

12 11 10 9 8

Fd

7

6

5

4 3

1 0 1 1 Z 1 0 0

0

Dm

The FTOSID (Floating-point Convert to Signed Integer from Double-precision) instruction converts a value
held in a double-precision register to a signed integer and writes the result to a single-precision register. The
integer value is normally then transferred to memory by a single-precision store instruction or to an ARM
register by an FMRS instruction.

Syntax
FTOSI{Z}D{<cond>}

<Sd>, <Dm>

where:
Z

Sets the Z bit in the instruction to 1 and means that the operation uses the round towards
zero rounding mode. If Z is not specified, the Z bit of the instruction is 0 and the operation
uses the rounding mode specified by the FPSCR.

<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the destination register. Its number is encoded as Fd (top 4 bits) and D (bottom
bit).

<Dm>

Specifies the source register.

Architecture version
D variants only

Exceptions
Floating-point exceptions: Invalid Operation, Inexact

Operation
if ConditionPassed(cond) then
Sd = ConvertDoubleToSignedInteger(Dm)

C4-108

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ARM DDI 0100E


VFP Instructions

Notes
Vectors

FTOSID always specifies a scalar operation, regardless of the LEN field of the FPSCR.

Out-of-range values
If the operand is −∞ (minus infinity) or the result after rounding would be less than −231, an
invalid operation exception is raised. If this exception is untrapped, the result is
0x80000000.
If the operand is +∞ (plus infinity) or the result after rounding would be greater than 231−1,
an invalid operation exception is raised. If the exception is untrapped, the result is
0x7FFFFFFF.
If the operand is a NaN, an invalid operation exception is raised. If this exception is
untrapped, the result is 0x00000000.

ARM DDI 0100E

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C4-109


VFP Instructions

4.1.59

FTOSIS
31

28 27 26 25 24 23 22 21 20 19

cond

16 15

1 1 1 0 1 D 1 1 1 1 0 1

12 11 10 9 8

Fd

7

6

5

4 3

1 0 1 0 Z 1 M 0

0

Fm

The FTOSIS (Floating-point Convert to Signed Integer from Single-precision) instruction converts a value
held in a single-precision register to a signed integer and writes the result to a second single-precision
register. The integer value is normally then transferred to memory by a single-precision store instruction or
to an ARM register by an FMRS instruction.

Syntax
FTOSI{Z}S{<cond>}

<Sd>, <Sm>

where:
Z

Sets the Z bit in the instruction to 1 and means that the operation uses the round towards
zero rounding mode. If Z is not specified, the Z bit of the instruction is 0 and the operation
uses the rounding mode specified by the FPSCR.

<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the destination register. Its number is encoded as Fd (top 4 bits) and D (bottom
bit).

<Sm>

Specifies the source register. Its number is encoded as Fm (top 4 bits) and M (bottom bit).

Architecture version
All

Exceptions

Floating-point exceptions: Invalid Operation, Inexact

Operation
if ConditionPassed(cond) then
Sd = ConvertSingleToSignedInteger(Sm)

C4-110

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ARM DDI 0100E


VFP Instructions

Notes
Vectors

FTOSIS always specifies a scalar operation, regardless of the LEN field of the FPSCR.

Out-of-range values
If the operand is −∞ (minus infinity) or the result after rounding would be less than −231, an
invalid operation exception is raised. If this exception is untrapped, the result is
0x80000000.
If the operand is +∞ (plus infinity) or the result after rounding would be greater than 231−1,
an invalid operation exception is raised. If this exception is untrapped, the result is
0x7FFFFFFF.
If the operand is a NaN, an invalid operation exception is raised. If this exception is

untrapped, the result is 0x00000000.

ARM DDI 0100E

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C4-111


VFP Instructions

4.1.60

FTOUID
31

28 27 26 25 24 23 22 21 20 19

cond

16 15

1 1 1 0 1 D 1 1 1 1 0 0

12 11 10 9 8

Fd

7

6

5

4 3

1 0 1 1 Z 1 0 0

0

Dm

The FTOUID (Floating-point Convert to Unsigned Integer from Double-precision) instruction converts a
value held in a double-precision register to an unsigned integer and writes the result to a single-precision
register. The integer value is normally then transferred to memory by a single-precision store instruction or
to an ARM register by an FMRS instruction.

Syntax
FTOUI{Z}D{<cond>}

<Sd>, <Dm>

where:
Z

Sets the Z bit in the instruction to 1 and means that the operation uses the round towards
zero rounding mode. If Z is not specified, the Z bit of the instruction is 0 and the operation
uses the rounding mode specified by the FPSCR.

<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the destination register. Its number is encoded as Fd (top 4 bits) and D (bottom
bit).

<Dm>

Specifies the source register.

Architecture version
D variants only

Exceptions
Floating-point exceptions: Invalid Operation, Inexact

Operation
if ConditionPassed(cond) then
Sd = ConvertDoubleToUnsignedInteger(Dm)

C4-112

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ARM DDI 0100E


VFP Instructions

Notes
Vectors

FTOUID always specifies a scalar operation, regardless of the LEN field of the FPSCR.

Out-of-range values
If the operand is −∞ (minus infinity) or the result after rounding would be less than 0, an
invalid operation exception is raised. If this exception is untrapped, the result is
0x00000000.
If the operand is +∞ (plus infinity) or the result after rounding would be greater than 232−1,
an invalid operation exception is raised. If this exception is untrapped, the result is
0xFFFFFFFF.
If the operand is a NaN, an invalid operation exception is raised. If this exception is
untrapped, the result is 0x00000000.

ARM DDI 0100E

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C4-113

VFP Instructions

4.1.61

FTOUIS
31

28 27 26 25 24 23 22 21 20 19

cond

16 15

1 1 1 0 1 D 1 1 1 1 0 0

12 11 10 9 8

Fd

7

6

5

4 3

1 0 1 0 Z 1 M 0

0

Fm

The FTOUIS (Floating-point Convert to Unsigned Integer from Single-precision) instruction converts a
value held in a single-precision register to an unsigned integer and writes the result to a second
single-precision register. The integer value is normally then transferred to memory by a single-precision
store instruction or to an ARM register by an FMRS instruction.

Syntax
FTOUI{Z}S{<cond>}

<Sd>, <Sm>

where:
Z

Sets the Z bit in the instruction to 1 and means that the operation uses the round towards
zero rounding mode. If Z is not specified, the Z bit of the instruction is 0 and the operation
uses the rounding mode specified by the FPSCR.

<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the destination register. Its number is encoded as Fd (top 4 bits) and D (bottom
bit).

<Sm>

Specifies the source register. Its number is encoded as Fm (top 4 bits) and M (bottom bit).

Architecture version
All

Exceptions
Floating-point exceptions: Invalid Operation, Inexact

Operation
if ConditionPassed(cond) then
Sd = ConvertSingleToUnsignedInteger(Sm)

C4-114

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ARM DDI 0100E


VFP Instructions

Notes
Vectors

FTOUIS always specifies a scalar operation, regardless of the LEN field of the FPSCR.

Out-of-range values
If the operand is −∞ (minus infinity) or the result after rounding would be less than 0, an
invalid operation exception is raised. If this exception is untrapped, the result is
0x00000000.
If the operand is +∞ (plus infinity) or the result after rounding would be greater than 232−1,
an invalid operation exception is raised. If this exception is untrapped, the result is
0xFFFFFFFF.
If the operand is a NaN, an invalid operation exception is raised. If this exception is
untrapped, the result is 0x00000000.

ARM DDI 0100E

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C4-115


VFP Instructions

4.1.62

FUITOD
31

28 27 26 25 24 23 22 21 20 19

cond

16 15

1 1 1 0 1 0 1 1 1 0 0 0

12 11 10 9 8

Dd

7

6

5

4 3

1 0 1 1 0 1 M 0

0

Fm

The FUITOD (Floating-point Convert Unsigned Integer to Double-precision) instruction converts an
unsigned integer value held in a single-precision register to double precision and writes the result to a
double-precision register. The integer value will normally have been transferred from memory by a
single-precision Load instruction or from an ARM register by an FMSR instruction.

Syntax
FUITOD{<cond>}

<Dd>, <Sm>

where:
<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Dd>

Specifies the destination register.

<Sm>

Specifies the source register. The register number is encoded as Fm (top 4 bits) and M
(bottom bit).

Architecture version
D variants only

Exceptions
None

Operation
if ConditionPassed(cond) then
Dd = ConvertUnsignedIntegerToDouble(Sm)

Notes
Vectors
Zero

C4-116

FUITOD always specifies a scalar operation, regardless of the LEN field of the FPSCR.
If Sm contains an integer zero, the result is a double-precision +0.0, not a double-precision
-0.0.

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ARM DDI 0100E


VFP Instructions

4.1.63

FUITOS
31

28 27 26 25 24 23 22 21 20 19

cond

16 15

1 1 1 0 1 D 1 1 1 0 0 0

12 11 10 9

Fd

8

7

6 5

4

1 0 1 0 0 1 M 0

3

0

Fm

The FUITOS (Floating-point Convert Unsigned Integer to Single-precision) instruction converts an
unsigned integer value held in a single-precision register to single precision and writes the result to a second
single-precision register. The integer value will normally have been transferred from memory by a
single-precision Load instruction or from an ARM register by an FMSR instruction.

Syntax
FUITOS{<cond>}

<Sd>, <Sm>

where:

<cond>

Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Sd>

Specifies the destination register. The register number is encoded as Fd (top 4 bits) and D
(bottom bit).

<Sm>

Specifies the source register. The register number is encoded as Fm (top 4 bits) and M
(bottom bit).

Architecture version
All

Exceptions
Floating-point exception: Inexact

Operation
if ConditionPassed(cond) then
Sd = ConvertUnsignedIntegerToSingle(Sm)

Notes
Vectors

FUITOS always specifies a scalar operation, regardless of the LEN field of the FPSCR.

Zero

If Sm contains an integer zero, the result is a single-precision +0.0, not a single-precision
-0.0.

Rounding

Rounding is needed for some large operand values. The rounding mode is determined by
the FPSCR.

ARM DDI 0100E

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C4-117