Tài liệu Getting Started with PIC® MCU Mid-Range docx

© 2005 Microchip Technology Incorporated. All Rights Reserved.
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 1
11002 GS2
Getting Started with
PIC
®
MCU Mid-Range
Architecture, Instruction Set and
Assembly Language Programming
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 2
Class Objective
When you finish this class you will:
− Understand the basics of the inner
workings of a PIC16
− Understand most instructions
− Understand memory organization
− Understand how to write simple
programs
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 3
Agenda
O Architecture Basics
O Instruction Set Overview
O Memory Organization and
Addressing Modes
O Special Features
O Hands-on Exercises
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 4
Architecture
O The high performance of the PIC
®
microcontroller can be attributed to the

following architectural features:
− Harvard Architecture
− Instruction Pipelining
− Large Register File
− Single Cycle Instructions
− Single Word Instructions
− Long Word Instructions
− Reduced Instruction Set
− Orthogonal Instruction Set
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 5
Harvard Architecture
O Von Neumann
Architecture:
− Fetches instructions and
data from a single memory
space
− Limits operating bandwidth
O Harvard Architecture:
− Uses two separate memory
spaces for program
instructions and data
− Improved operating
bandwidth
− Allows for different bus
widths
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 6
Instruction Pipelining
O Instruction fetch is overlapped with execution of previously
fetched instruction
call SUB1

addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch Flush

Fetch
T7
Time to execute normal instruction
Time to execute call
instruction includes
pipeline flush
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 7
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch
T0
Instruction Cycles

movlw 0x05 -
Pre-Fetched Instruction
Executing Instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 8
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch Execute
T0 T1
Instruction Cycles
Fetch
movwf REG1 movlw 0x05
Pre-Fetched Instruction

Executing Instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 9
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch Execute
T0 T1 T2
Instruction Cycles
Fetch Execute
Fetch
call SUB1 movwf REG1
Pre-Fetched Instruction
Executing Instruction

Time to execute normal instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 10
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch Execute
T0 T1 T2 T3
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
addwf REG2 call SUB1
Pre-Fetched Instruction

Executing Instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 11
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch Execute
T0
Flush
T1 T2 T3 T4
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch

Fetch
movf PORTB,w call SUB1
Pre-Fetched Instruction
Executing Instruction
Time to execute call
instruction includes
pipeline flush
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 12
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example Program
Fetch Execute
T0

Flush
T1 T2 T3 T4 T5
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch
return movf PORTB,w
Pre-Fetched Instruction
Executing Instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 13
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1
2
3
4
51
52
53

54
Example Program
Fetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch
movf PORTC,w return
Pre-Fetched Instruction
Executing Instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 14
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05MAIN
movwf REG1
1

2
3
4
51
52
53
54
Example Program
Fetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch Flush
Fetch
T7
addwf REG2 return
Pre-Fetched Instruction
Executing Instruction
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 15
Long Word Instruction
8-bit Program Memory
14-bit Program Memory
1

1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k

k
1
1
1
1
0
0
0
0
0
0
0
0
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
8-bit Instruction on typical 8-bit MCU

Example: Freescale ‘Load Accumulator A’:
• 2 Program Memory Locations
• 2 Instruction Cycles to Execute
14-bit Instruction on PIC16 8-bit MCU
Example: ‘Move Literal to Working Register’
• 1 Program Memory Location
• 1 Instruction Cycle to Execute
O Limits
Bandwidth
O Increases
Memory Size
Requirements
O Separate busses allow different widths
O 2k x 14 is roughly equivalent to 4k x 8
ldaa #k
movlw k
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 16
Register File Concept
Data Bus
Data Bus
d
Opcode
Opcode
d
d
Address
Address
Decoded Instruction
from Program
Memory:

Arithmetic/Logic
Function to be Performed
Result
Destination
Address of Second
Source Operand
O Register File Concept:
All of data memory is
part of the register
file, so any location in
data memory may be
operated on directly
O All peripherals are
mapped into data
memory as a series of
registers
O Orthogonal
Instruction Set: ALL
instructions can
operate on ANY data
memory location
O The Long Word
Instruction format
allows a directly
addressable register
file
wf
wf
ALU
W

W
Data Memory
(Register File)
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 17
Instruction Set Overview
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 18
Instruction Set Overview
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 19
Instruction Set Overview
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 20
PIC16 Instruction Set
Byte Oriented Operations
Byte Oriented Operations
Bit Oriented Operations
Bit Oriented Operations
addwf f,d
addwf f,d
andwf f,d
andwf f,d
clrf f

clrf f
clrw -
clrw -
comf f,d
comf f,d
decf f,d
decf f,d
decfsz f,d
decfsz f,d
incf f,d
incf f,d
incfsz f,d
incfsz f,d
iorwf f,d
iorwf f,d
movf f,d
movf f,d
movwf f
movwf f
nop -
nop -
rlf f,d
rlf f,d
rrf f,d
rrf f,d
subwf f,d
subwf f,d
swapf f,d
swapf f,d
xorwf f,d

xorwf f,d
Add W and f
Add W and f
AND W with f
AND W with f
Clear f
Clear f
Clear W
Clear W
Complement f
Complement f
Decrement f
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if 0
Increment f
Increment f
Increment f, Skip if 0
Increment f, Skip if 0
Inclusive OR W with f
Inclusive OR W with f
Move f
Move f
Move W to f
Move W to f
No Operation
No Operation
Rotate Left f through Carry
Rotate Left f through Carry
Rotate Right f through Carry

Rotate Right f through Carry
Subtract W from f
Subtract W from f
Swap nibbles in f
Swap nibbles in f
Exclusive OR W with f
Exclusive OR W with f
bcf f,b
bcf f,b
bsf f,b
bsf f,b
btfsc f,b
btfsc f,b
btfss f,b
btfss f,b
Bit Clear f
Bit Clear f
Bit Set f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Test f, Skip if Set
Literal and Control Operations
Literal and Control Operations
addlw k
addlw k
andlw k
andlw k
call k

call k
clrwdt -
clrwdt -
goto k
goto k
iorlw k
iorlw k
movlw k
movlw k
retfie -
retfie -
retlw k
retlw k
return -
return -
sleep -
sleep -
sublw k
sublw k
xorlw k
xorlw k
Add literal and W
Add literal and W
AND literal with W
AND literal with W
Call subroutine
Call subroutine
Clear Watchdog Timer
Clear Watchdog Timer
Go to address

Go to address
Inclusive OR literal with W
Inclusive OR literal with W
Move literal to W
Move literal to W
Return from interrupt
Return from interrupt
Return with literal in W
Return with literal in W
Return from Subroutine
Return from Subroutine
Go into standby mode
Go into standby mode
Subtract W from literal
Subtract W from literal
Exclusive OR literal with W
Exclusive OR literal with W
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 21
PIC16 Visual Interpreter
ADDLW 0x0
A
Execute
Register File Address
d
FF
FF
FF
W Register
FF
FF

FF
FF
FF
FF
FF
FF
FF
18
18
18
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
00h
01h

02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
wf
wf
ALU
1
1
1
0
0
0
0
0
ZDCC
STATUS
Data
Bus
Reset
Hex
Dec
Bin
Literal Data from

Instruction Word
,
,
0
1
2
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 22
Data Memory Organization
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
PIC16F876/877 Register File Map
368 Bytes of General Purpose RAM Plus Special Function Registers
000h
01Fh
020h
07Fh
080h
09Fh
0A0h

0FFh
100h
110h
17Fh
180h
190h
1FFh
0EFh 16Fh 1EFh
10Fh 18Fh
128 Bytes
SFR SFR SFR SFR
GPR
96 Bytes
GPR
80 Bytes
GPR
96 Bytes
GPR
96 Bytes
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 23
Data Memory Organization
INDF
INDF
TMR0
TMR0
PCL
PCL
STATUS
STATUS
FSR

FSR
PORTA
PORTA
PORTB
PORTB
PORTC
PORTC
PORTD
PORTD
PORTE
PORTE
PCLATH
PCLATH
INTCON
INTCON
INDF
INDF
OPTION_REG
OPTION_REG
PCL
PCL
STATUS
STATUS
FSR
FSR
TRISA
TRISA
TRISB
TRISB
TRISC

TRISC
TRISD
TRISD
TRISE
TRISE
PCLATH
PCLATH
INTCON
INTCON
INDF
INDF
TMR0
TMR0
PCL
PCL
STATUS
STATUS
FSR
FSR
PORTB
PORTB
PCLATH
PCLATH
INTCON
INTCON
INDF
INDF
OPTION_REG
OPTION_REG
PCL

PCL
STATUS
STATUS
FSR
FSR
TRISB
TRISB
PCLATH
PCLATH
INTCON
INTCON
PIR1
PIR1
PIE1
PIE1
EEDATA
EEDATA
EECON1
EECON1
PIR2
PIR2
PIE2
PIE2
EEADR
EEADR
EECON2
EECON2
Bank 0 Bank 1 Bank 2 Bank 3
000
001

002
003
004
005
006
007
008
009
00A
00B
00C
00D
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
100
101
102
103

104
105
106
107
108
109
10A
10B
10C
10D
180
181
182
183
184
185
186
187
188
189
18A
18B
18C
18D
Device Specific Registers
© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 24
STATUS Register
IRP
IRP
RP1

RP1
RP0
RP0
TO
TO
PD
PD
Z
Z
DC
DC
C
C
bit 7 bit 0
IRP: Register Bank Select (used for Indirect addressing)
0 = Bank 0, 1 1 = Bank 2, 3
RP1:RP0: Register Bank Select Bits (used for direct addressing)
00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3
TO: Time-out bit
0 = A WDT time-out occurred
PD: Power-down bit
0 = SLEEP instruction executed
Z: Zero bit
1 = Result of arithmetic operation is zero
DC: Digit cary / borrow bit
1 = Carry out of 4
th
low order bit occurred / No borrow occurred
C: Carry / borrow bit
1 = Carry out of MSb occurred / No borrow occurred

© 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 25
PIC16 Addressing Modes
O Data Memory Access:
− Direct addwf <data_address>, <d>
− Indirect addwf INDF, <d>
− Immediate (Literal) movlw <constant>
O Program Memory Access:
− Absolute goto <program_address>
− Relative addwf PCL,f