Design an 2 stage amplifier

VIETNAM NATIONAL UNIVERSITY - HO CHI MINH
UNIVERSITY OF SCIENCE
FACULITY OF ELECTRONICS AND TELECOMMUNICATION
GRADUATE COURSE IN MICROELECTRONICS

Design an 2 stage amplifier
Le Thanh Thien An


Agenda

1. Outline
2. Result review
3. Hand design result
4. Simulation summary result
5. Layout review


Outline



Base on topology as below image and specification information, design an amplifier.
Topology

Specification

Specification

 
Item

Condition

Specification

Unit

MIN

TYP

MAX

Supply Voltage

V

4.5

5

5.5

Temperature

°C

-40

25

150

Input voltage range

V

1

1.5

2.5

Current (Icc)

uA

-

-

800

Slew rate (SR)

MV/s

5

-

-

Open Gain

dB

60

-

-

Unity Gain Frequency

MHz

2

-

-

Phase Margin

deg

50

-

-

mV

-10

-

10

mV

-

-

-

mV

-

-

-

um^2

-

-

3600

Input offset voltage
(3s + systematic)
Saturation region
|Vds - Vdsat|, min
Strong inversion region
|Vgs-Vth|,min
Area (total W*L)

3


Result review

Below result is from hand-calculation.
Amplifier has met all specifications
Cout = 10 pF

Specification

 

hand-calculation

simulation

simulation (Post_layout)

Item

Condition

Specification

Judge
Unit

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

Supply Voltage

V

4.5

5

5.5

4.5

5

5.5

4.5

5

5.5

4.5

5

5.5

Temperature

°C

-40

25

150

-40

25

150

-40

25

150

-40

25

150

Input voltage range

V

1

1.5

2.5

1

1.5

2.5

1

1.5

2.5

1

1.5

2.5

Current (Icc)

uA

-

-

800

248.67

355.25

532.87

245

379

602

244.6

378.6

600.6

Slew rate (SR)

MV/s

5

-

-

7.36

10.51

15.77

5.12

8.43

15.9

5.04

8.32

15.63

Open Gain

dB

60

-

-

96.22

100.03

105.87

74.57

84.12

88.38

74.59

84.12

88.39

Unity Gain Frequency

MHz

2

-

-

6.02

7.2

8.82

2.98

6.22

14.7

2.978

6.21

14.71

Phase Margin

deg

50

-

-

-

72.8

-

51.29

67.29

72.12

51.27

67.29

72.11

mV

-10

-

10

-

9.89

-

-9.85

-0.05

9.67

-9.87

-0.05

9.81

Input offset voltage
(3s + systematic)

Saturation region
|Vds - Vdsat|, min

Strong inversion region
|Vgs-Vth|,min

-

-

OK
OK

OK
OK
OK

OK

mV

-

-

-

100

-

-

290

-

-

289

-

OK

mV

-

-

-

150

-

-

125

-

-

125

-

-

um^2

-

-

3600

-

2269

-

-

2276

-

-

3293

-

OK
Area (total W*L)

4

OK

Hand design result (1/2)

Items

unit

Mpin0/Mpin1

Mnl0/Mnl1

Mno

Mpr

Mpt1

L

(um)

2

3

3

1

1

1

W (total W)

(um)

27.33

5.9

212.24

7.47

7.47

134.39

finger/multi

 

2/2

2/2

2/72

2/2

2/2

2/36

J

(uA/um)

0.33

1.51

1.51

2.38

2.38

2.38

Vdsat

(V)

0.24

0.37

0.37

0.4

0.4

0.4

Vds - Vdsat

(V)

1.17

0.66

1.5

0.56

0.56

0.56

Area

(um^2)

109.33

35.37

636.71

7.47

7.47

134.34

Cc(pF)

Iref(A)

1.69

17.76

1300

(um2)

6.40E-05

(A/(V^2))

2.41E-05

(A/(V^2))

9.92

(mv)

Cc (pF)

R0(kohm)

Area of Capacitor Cc
(0.0013pF/um2)

unCox =

 

upCox =

 

Input offset voltage
3σ

5
Simulation results

Mpt2


Hand design result (2/2)


Step 1: Hand design and simulation

Below image shows the schematic with parameters of components

6


Simulation result summary
Consideration (1) ICC

Contribution Analysis from DC simulation

Current (ICC)
[uA]

7

Res [kohm]

Vth_MPR

Vdsat_MPR

I_MPR

I_MPT1

I_MPT2

Typ

379

2.28E+02

7.45E-01

3.53E-01

1.71E+01

1.80E+01

3.44E+02

Worst

602

1.70E+02

5.23E-01

5.04E-01

2.63E+01

2.90E+01

5.47E+02

Typ

temp = 25 deg VCCA=5V Vcm=1.5 mos_hv=TT Moscap=TT Res=TT

Worst

temp = 150 deg VCCA = 5.5V Vcm=1 mos_hv=FF Moscap=Max Res= FF



Because of channel length effect, current ratio between stage 1 and 2 does not same with hand design.







VCCA max, Vcm min make Vds of MPT1 become bigger
Mos_hv = FF: Vth of mosfet is smaller
Temp. higher => Vth decrease
R value is smaller, => current is higher
Res = FF: fast conductance => current higher


Consideration (2) slew rate

Contribution anaysis from DC simulation

Slew rate
[Mv/s]

Typ

Cc

Res

I_MPR

I_MPT1

I_MPT2

[pF]

[kohm]

[uA]

[uA]

[uA]

Typ

8.43

1.57

2.28E+02

17.1

18.4

350

Worst

5.04

1.99

2.48E+02

11.7

12.3

237

: temp=2 5deg VCCA=5V Vcm=1.5V mos hv=TT MosCap=TT Res=TT

Worst : Temp=-4 0 VCCA=4.5 mos _hv=FS Moscap=MAX Res=SS

8



Cc is biggest contributor for PVT variation of slew rate






VCCA min => current decrease
Temp is lower, so R value increase => current decrease
Res = SS: lower conduction => current decrease
Moscap = max => Cc increase => SR decrease


Consideration (2) Slew rate (2/2)
Contribution anaysis from DC simulation
Slew rate
[Mv/s]

Typ

Res

I_MPR

I_MPT1

I_MPT2

[kohm]

[uA]

[uA]

[uA]

Typ

8.43

1.57

2.28E+02

17.1

18.4

350

Worst

5.04

1.99

2.48E+02

11.7

12.3

237

: temp=2 5deg VCCA=5V Vcm=1.5V mos hv=TT MosCap=TT Res=TT

Worst : Temp=-4 0 VCCA=4.5 mos _hv=FS Moscap=MAX Res=SS

9

Cc
[pF]


Consideration (3) Open gain

Contribution Analysis from DC simulation

Open Gain

gm

[dB]

_MPIN1

gm

[uA/V]

Typ
Worst
Typ

ro

_MN0

ro1

_MPIN1

[uA/V]

[Mohm]

[Mohm]

ro

[kohm]

[Mohm]

ro

ro

_MN0

_MPT2

[kohm]

[kohm]

I_MPT2

I_MPT2

[uA]

[uA]

84.12

79.5

1810

2.16

5.9

3.41

51.87

123

89.7

18

344

74.57

85.6

1820

1.18

3.06

1.93

59.76

521

67.5

29

547

: temp=2 5deg VCCA=5V Vcm=1.5V mos_hv=TT Moscap=TT Res=TT

Worst : temp=1 50 VCCA=5.5 Vcm=1 mos_hv=FF Moscap=MAX Res=FF

10

ro2

_MNL1






VCM decrease so Vds of MPT1, MPT2 increase, ro decrease



To improve open gain, need to decrease current to get ro higher

Vth of Pmos and Nmos decrease: increase current, ro decrease
Res = FF: fast conducton, increase current
Temp. increase, vth decrease: increase current


Consideration (4) Unity Gain Frequency

Contribution Analysis from DC simulation
Unity Gain

Typ
Worst
Typ:

Frequency

Cc

[MHz]

[pF]

gm
_MPIN 1
[uA/V]

[uA]

gm

fu

fp2

_MN 0

(calc)

(calc)

[uA/V]

[MHz]

[MHz]

6.22

1.87

79.5

18

1810

6.77

24.27

2.98

2.27

45.7

12.1

1070

3.2

13.88

temp=2 5deg VCCA=5V Vcm=1.5 mos_hv=TT Moscap=TT Res=TT

Worst: temp=1 50 VCCA=4.5 Vcm=2.5 mos_hv=ss Moscap=MAX Res=SS

11

I_MPT1




fu in my hand design is 7.2M => cause: Cc value is change





Moscap = max => fu is creased

Gm1 decrease by current decrease

Res = SS => decrease current => gm1 decrease
Vds of MPT1, MPT2 is decreased

Consideration (5) Phase Margin (1/2)

Contribution Analysis from DC simulation
fu

fz

Phase Margin

(calc)

(calc)

(calc)

Cc

gm_MPIN1

gm_MN0

I_MPT1

[deg]

[MHz]

[MHz]

[MHz]

[pF]

[uA/V]

[uA/V]

[uA]

I_MPT2
[uA]

Typ

67.29

6.77

24.27

154.05

1.87

79.5

1810

18

344

Worst

51.29

19.39

38.95

431.14

0.993

121

2690

27.6

524

Typ

Worst

12

fp2

temp=25deg VCCA=5V Vcm=1 mos_hv=TT moscap=TT Res=TT

tem=-40 VCCA=5.5 Vcm=1 mos_hv=SF moscap=Min Res=FF



Simulation result does not match with hand design. It’s decreased by fz.








Res=FF => increase current
Moscap=min : Cc decrease => PM decrease
Mos_hv=SF: Vth of NMOS increase => current I2 decrease
Vth of Pmos decrease => current I1 increase
=> PM decrease
VCCA= 5.5 and Vcm =1 => Vds of MPT1 increase , so current increase

The error factor: Cc, gm_PIN1, gm_MN0


Consideration (5) Phase Margin (2/2)

Contribution Analysis from DC simulation
fu

13

fp2

fz

Phase Margin

(calc)

(calc)

(calc)

Cc

gm_MPIN1

gm_MN0

I_MPT1

[deg]

[MHz]

[MHz]

[MHz]

[pF]

[uA/V]

[uA/V]

[uA]

I_MPT2
[uA]

Typ

67.29

6.77

24.27

154.05

1.87

79.5

1810

18

344

Worst

51.29

19.39

38.95

431.14

0.993

121

2690

27.6

524

Typ

temp=25deg VCCA=5V Vcm=1 mos_hv=TT moscap=TT Res=TT

Worst

tem=-40 VCCA=5.5 Vcm=1 mos_hv=SF moscap=Min Res=FF

Consideration (6) Offset Voltage:
Random
Contribution Analysis from DC simulation
Random offset

σVth_diff

σVth_load

gm_MPIN1

gm_MNL1

(Ratio)

voltage [mv]

[mv]

[mv]

[uA/V]

[uA/V]

gm_MNL1/gm_MPIN1 [uA/V]

1.83

2.81

79.5

48.5

0.61

Typ

Typ

9.69

Temp=25deg VCCA=5V Vcm=1.5V mos_hv=TT moscap=TT Res=TT



Main contributor for random offset voltage is load pair



To reduce offset voltage:

-

14

Increase gate length of load pair
Decrease current
Increase delta OV of Nmod (load) a little

Consideration (7) Offset voltage:
Systematic
Contribution Analysis from DC simulation
Systematic
offset voltage

Delta Vgs*

[mv]

Av1

[mv]

gm_MPIN1

[V/V]

ro1

[uA/V]

[Mohm]

ro

ro

MPIN1

MNL1

[Mohm]

[Mohm]

Typ

0.05

8.63

171

79.5

2.16

5.9

3.41

Worst

0.15

17.19

109.9

72.4

1.52

3.39

2.75

Typ

temp=25deg VCCA=5V Vcm=1.5V mos_hv=TT Moscap=TT Res=TT

Worst

temp=150deg VCCA=5.5V Vcm=1 mos_hv=SS Moscap=MAX RES=TT

Delta Vgs* = Vgs_MN0 - Vgs_MNL0




Mismatch characteristic of load pair and output mosfet (Vgs between them) cause of systematic offset voltage
To reduce systematic offset voltage:

-

15

Reduce mismatch current between MPT1 and MPT2
Av1 (gain of stage 1) is enough large (Vof = Delta_Vo1/AV1)


Layout
Circuit schematic for layout

16


Floor-plan
45.8 um



Diff. , load pair are placed
common centroid



Antenna diodies are placed
close to gate with mosfets



Symmetrical placement for
current source mosfets

R & Dummy R
MPT2

Output
MPR

DM

MPT1

DM

Mos
71,8 um

DM

MPIN1

MPIN0

DM

Cc
DM

MPIN0

MPIN1

DM

Antenna
diodes
DM : Dummy

17

DM
DM

MNL0

MNL1

MNL1

MNL0

DM
DM


Important nets

1. VPT1: Tail signal is short and route straight due to center line of differential pair.
2. OUT: short and width correspond with current ratio.

18


Important nets

19

3.

VNL0-VNL1: routing common centroid , using some dummy metal

4.

OUT: increase wiring width for long nets.


THANK FOR YOUR ATTENTION