Silicon Devices and Process Integration pot

Silicon Devices and Process Integration
Deep Submicron and Nano-Scale Technologies
Badih El-Kareh
Silicon Devices
and Process Integration
Deep Submicron and Nano-Scale
Technologies
ABC
Badih El-Kareh
Independent Consultant
Cedar Park, TX
USA

ISBN: 978-0-387-36798-9 e-ISBN: 978-0-387-69010-0
DOI: 10.1007/978-0-387-69010-0
Library of Congress Control Number: 2008936300
c
 Springer Science+Business Media, LLC 2009
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Preface
State-of-the-art silicon devices and integrated process technologies are covered in

this book. The eight chapters represent a comprehensive discussion of modern
silicon devices, their characteristics, and the relationship between their electrical
properties and processing conditions. The material is compiled from industrial and
academic lecture-notes and reflects years of experience in the development of sili-
con devices.
The book is prepared specifically for engineers and scientists in semiconduc-
tor research, development and manufacturing. It is also suitable for a one-semester
course in electrical engineering and materials science at the upper undergraduate or
lower graduate level.
The chapters are arranged logically, beginning with a review of silicon properties
that lays the groundwork for the discussion of device properties, including mobility-
enhancement by straining silicon.
Junctions and contacts are inherent to practically all semiconductor devices.
Chapter 2 covers junctions under forward and reverse characteristics, including
high-level injection and high-field effects. Understanding the properties of contacts
has become increasingly important as the contact size is reduced to deep submicron
and nanoscale dimensions. The last part of Chap. 2 discusses ohmic and rectifying
contacts.
Chapter 3 begins with bipolar fundamentals and moves to an advanced treat-
ment of bipolar enhancements with silicon–germanium (SiGe). This chapter is par-
ticularly important to analog and mixed-signal applications where complementary
metal-oxide semiconductor (CMOS) and bipolar transistors are integrated in a BiC-
MOS process. It also benefits engineers in understanding important bipolar effects
in CMOS-only applications, such as subthreshold current and parasitic latch-up.
The metal-oxide silicon (MOS) capacitor is a key part of a metal-oxide semicon-
ductor field-effect transistor (MOSFET) and a powerful process and device charac-
terization tool. The physics and characterization of MOS structures are detailed in
Chap. 4, beginning with an ideal stack of a conductor, an insulator and silicon, and
gradually moving to real structures and quantum effects.
v

vi Preface
Chapter 5 deals with the insulated-gate field-effect transistor. It begins with a
description of the modes of transistor operation and the different transistor types.
Transistor current–voltage characteristics are detailed, followed by a discussion of
scaling the structure to smaller dimensions, scaling limitations, short-channel, re-
verse short-channel, narrow-channel, and reverse narrow-channel effects. Mobility
enhancement techniques are described, including strained silicon and optimization
of crystal orientation. The discussion extends to ultra-thin gate-oxide, high-K di-
electrics, advanced gate-stacks, and three-dimensional structures.
Analog devices and passive components are introduced in Chap. 6. As an exten-
sion of bipolar transistors detailed in Chap. 3, the properties of junction field-effect
transistors are described, followed by optimization of MOSFETs for analog appli-
cations. The design and properties of integrated precision resistors, capacitors, and
varactors are then detailed. The chapter concludes with the important topics of com-
ponent matching and noise.
Chapter 7 covers advanced enabling processes and process integration. It be-
gins with integrated CMOS and BiCMOS processes to illustrate typical sequences
of processing steps. Crystal growth and wafer parameters, including properties
of silicon-on-insulator (SOI), relevant to modern integrated processes are dis-
cussed. Front-end of the line unit processes include short-duration thermal pro-
cesses, atomic-lay deposition (ALD), ionized physical-vapor deposition (IPVD),
optical proximity correction (OPC), double exposure and patterning, immersion
lithography, and new silicides. Back-end of the line processes include copper in-
terconnects and low-K dielectrics.
The last chapter reviews selected CMOS and BiCMOS digital and memory ap-
plications. The inverter is used to analyze the important parasitic latch-up effect
and methods to suppress it. The second part covers memory cells, including dy-
namic random-access memory (DRAM), static random-access memory (SRAM),
and nonvolatile memory (NVM).
It would not have been possible for me to complete this book in its present

form without the continuous invaluable help with corrections and suggestions for
improvement and encouragement from Dr. Wendell Noble, independent consul-
tant, retired IBM semiconductor physicist, Professor Carlton Osburn of the North
Carolina State University, and Dr. Albert Puttlitz, IEEE-Components, Packaging
and Manufacturing Technology Society, VP of Education. I also thank my former
colleagues at IBM, Russell Houghton and Ashwin Ghatalia, for their reviews and
inputs. My special thanks to the personnel of the University of Texas library for
their kind support in my research.
August 18, 2008 Badih El-Kareh
Contents
List of Symbols xiii
1 Silicon Properties 1
1.1 Introduction . . . . 1
1.2 Valence-Bond and Two-Carrier Concept . . 1
1.2.1 Doping 3
1.3 Energy Bands in Silicon . . . . . 6
1.3.1 Energy Band Model . . 6
1.3.2 Metals, Semiconductors and Insulators . . . . 10
1.3.3 Band Model for Impurities in Silicon . . . . . . 11
1.3.4 Energy Band Theory . 12
1.3.5 EffectiveMass 16
1.4 Thermal Equilibrium Statistics . . . 17
1.4.1 The Boltzmann Distribution Function . . . . . 18
1.4.2 Fermi-DiracDistributionandDensityofStates 18
1.4.3 Density of States and Carrier Distribution in Silicon . . . . . . . 20
1.4.4 Doped Silicon 23
1.5 CarrierTransport 28
1.5.1 CarrierTransportbyDrift:LowField 29
1.5.2 Matthiesson’sRule 36
1.5.3 CarrierTransportbyDrift:HighField 37

1.5.4 CarrierTransportbyDiffusion 42
1.6 Nonequilibrium Conditions . . 44
1.6.1 CarrierLifetime 45
1.6.2 Diffusion Length . . . . 49
1.7 Problems 50
References . . . 52
2 Junctions and Contacts 55
2.1 Introduction . . . . 55
2.2 PNJunction 55
2.2.1 Junction Profiles and Shapes . . . . . . 57
vii
viii Contents
2.2.2 Step-JunctionApproximation 57
2.2.3 PN Junction at Thermal Equilibrium . . . . . . 64
2.2.4 PNJunctioninForwardBias 77
2.2.5 PNJunctioninReverseBias 93
2.3 Contacts 111
2.3.1 Rectifying Contacts, Schottky Barrier Diode . . . 111
2.3.2 Current–VoltageCharacteristics 118
2.3.3 OhmicContacts 123
2.4 Problems 129
References . . . 131
3 The Bipolar Transistor 135
3.1 Introduction . . . . 135
3.2 Transistor Action, a Qualitative Description . . . . . . 136
3.2.1 Nomenclature and Regions of Operation . . . 136
3.2.2 IdealizedStructure 138
3.2.3 Ebers-Moll Equations 141
3.2.4 Collector Saturation Voltage, V
CEsat

142
3.3 Planar Transistor, Low-Level Injection 143
3.3.1 Low-LevelInjectionParameters 144
3.3.2 Collector-BaseReverseCharacteristics 151
3.3.3 Emitter-Base Reverse Characteristics. . . . . . 156
3.3.4 Polysilicon Emitter and Interface Oxide . . . 158
3.3.5 Transistor Resistances 165
3.4 High-LevelInjectionEffects 172
3.4.1 Base Conductivity Modulation . . . . 172
3.4.2 Base-PushEffect(KirkEffect) 173
3.5 Frequency Response of Current Gain . . . . . 175
3.5.1 Emitter Delay,
τ
E
176
3.5.2 Base Transit Time,
τ
B
177
3.5.3 Collector Delay,
τ
C
179
3.6 TheTransistorasaSwitch 182
3.6.1 Delay Time, t
d
183
3.6.2 Rise Time, t
r
185

3.6.3 Storage Time, t
s
186
3.6.4 Fall Time, t
f
187
3.7 Silicon-Germanium Transistor . . . . 188
3.7.1 SiGe Film Deposition and Properties . . . . . . 188
3.7.2 Bandgap Lowering . . . 191
3.7.3 DensityofStates 192
3.7.4 Mobility 192
3.7.5 TransistorParameters 196
3.7.6 TransistorOptimization 200
3.8 Problems 204
References . . . 207
Contents ix
4 The MOS Structure 213
4.1 Introduction . . . . 213
4.2 Physics of an Ideal MOS Structure 214
4.2.1 Description of Semiconductor Surface Conditions . . . . . . . . . 215
4.2.2 SurfaceChargeandElectricField 220
4.2.3 Approximations 222
4.2.4 Excess Surface Carrier Concentrations . . . . 224
4.2.5 MOS Capacitance . . . . 225
4.3 Calculation of Capacitance. . . 228
4.3.1 Calculation of Low-Frequency Capacitance 228
4.3.2 Description of the Low-Frequency CV-Plot 229
4.3.3 Calculation of High-Frequency Capacitance . . . . 237
4.4 Measurement of MOS Capacitance 239
4.4.1 Low-Frequency, or Quasi-Static CV Measurement . . . . . . . . 239

4.4.2 High-Frequency CV Measurement . 240
4.5 Non-UniformImpurityProfile 241
4.5.1 ProfileApproximations 242
4.5.2 SurfaceConditions 242
4.6 Non-Ideal MOS Structure 244
4.6.1 Workfunction Difference . . 244
4.6.2 DielectricCharge 247
4.7 CharacterizationandParameterExtraction 253
4.7.1 Extraction of Equivalent Oxide Thickness, t
eq
253
4.7.2 Workfunction Difference . . 254
4.7.3 Extraction of Dopant Concentration . . . . . . . 255
4.7.4 LifetimeMeasurements 257
4.7.5 Extraction of Interface-State Distribution . . 259
4.7.6 Extraction of Mobile Ion Concentration . . . 263
4.8 Carrier Transport Through the Dielectric . . 264
4.8.1 Tunneling Through the Oxide . . . . . 265
4.8.2 Avalanche Injection . . 266
4.9 Problems 268
References . . . 270
5 Insulated-Gate Field-Effect Transistor 273
5.1 Introduction . . . . 273
5.2 Qualitative Description of MOSFET Operation 273
5.3 Gate-ControlledPNJunction,orGatedDiode 277
5.3.1 Junction at Equilibrium . . . 277
5.3.2 Reverse Biased Junction: Depleting Gate Voltage . . . . . . . . . 279
5.3.3 Reverse Biased Junction: Accumulating Gate Voltage . . . . . . 281
5.4 MOSFETCharacteristics 286
5.4.1 Long and Wide Channel . . 286

5.4.2 ScalingtoSmallDimensions 304
x Contents
5.4.3 Short-Channel Effects, SCE 312
5.4.4 Reverse Short-Channel Effects, RSCE 319
5.4.5 Narrow Channel Effects, NCE 322
5.4.6 Reverse Narrow-Channel Effects, RNCE 326
5.4.7 Small-SizeEffects 329
5.5 Mobility Enhancement . . . . . . 330
5.5.1 Mean-Free Time Between Collisions,
τ
331
5.5.2 EffectiveMass 334
5.6 UltrathinOxideandHigh-KDielectrics 340
5.6.1 High-K Dielectric Requirements . . 341
5.6.2 High-KMaterials 343
5.7 GateStack 345
5.7.1 PolysiliconWorkfunction 346
5.7.2 MetalGates 347
5.8 Three-Dimensional Structures, FinFETS 352
5.9 Problems 353
References . . . 356
6 Analog Devices and Passive Components 369
6.1 Introduction . . . . 369
6.2 AnalogDevices 370
6.2.1 JunctionField-EffectTransistor,JFET 370
6.2.2 Analog/RFMOSFETs 381
6.2.3 Integrated Passive Components . . . 385
6.3 Matching 409
6.3.1 MOSFET Mismatch 410
6.3.2 BipolarTransistorMismatch 416

6.3.3 ResistorMismatch 417
6.3.4 Capacitor Mismatch . . 419
6.4 Noise 422
6.4.1 ClassificationofNoise 423
6.5 Problems 429
References . . . 430
7 Enabling Processes and Integration 439
7.1 Introduction . . . . 439
7.2 A Conventional CMOS Logic Process Flow . . . . . . 439
7.3 A BiCMOS Process Flow . . . . 446
7.4 Advanced Enabling Processes 451
7.4.1 Crystal Growth and Wafer Preparation . . . . 451
7.4.2 Short-Duration Thermal Processes 460
7.4.3 Thin-Film Deposition. 466
7.4.4 IntegrationofUltra-ShallowJunctions 479
7.4.5 Gate Stack Module . . . 485
Contents xi
7.5 Advanced Interconnects . . . . . 489
7.5.1 Copper Interconnects . 491
7.5.2 Low-KDielectrics 498
7.6 Problems 501
References . . . 503
8 Applications 523
8.1 Introduction . . . . 523
8.2 LogicUnits 523
8.2.1 TheInverter 523
8.2.2 The CMOS Inverter 528
8.2.3 The BiCMOS Inverter 533
8.2.4 CMOS NAND and NOR Gates 534
8.2.5 BiCMOS Two-Input NAND 535

8.2.6 TheTransmissionGate 536
8.3 Memories 537
8.3.1 Dynamic Random-Access Memories, DRAM 537
8.3.2 Static Random Access Memories, SRAM 546
8.3.3 Nonvolatile Memory, NVM 551
8.3.4 BiCMOS forAnalog/RFApplications 566
8.4 Problems 567
References . . . 567
Appendix A: Universal Physical Constants 575
Appendix B: International System of Units, SI 577
Appendix C: The Greek Alphabet 579
Appendix D: Properties of Silicon and Germanium (300K, Intrinsic
Semiconductor Unless Otherwise Stated) 581
Appendix E: Conversion Factors 583
Index 585
List of Symbols
a acceleration (cm/s
2
)
a JFET metallurgical channel width (cm)
a lattice constant (cm)
a voltage ramp-rate (V/s)
A geometry-dependent factor
A area (cm
2
)
A
∗
effective Richardson constant (A/cm
2

·K
2
)
A
E
emitter area (cm
2
)
A
C
cross-sectional area (cm
2
)
A
ΔR
process-related resistor mismatch factor (cm)
A
ΔVT
process-related threshold voltage-mismatch factor (cm)
A
G
gate area (cm
2
)
A
S
surface area (cm
2
)
b mobility ratio (

μ
n
/
μ
p
)
BL bit-line
BV breakdown voltage (V)
BV
CBO
collector-base breakdown voltage, emitter open (V)
BV
CBS
collector-base breakdown voltage, emitter-base shorted (V)
BV
CEO
collector-emitter breakdown voltage, base open (V)
BV
DGO
drain-gate breakdown voltage, source open (V)
BV
DGS
drain-gate breakdown voltage, source-gate shorted (V)
BV
EBO
emitter-base breakdown voltage, collector open (V)
BV
EBS
emitter-base breakdown voltage, collector-base shorted (V)
C capacitance per unit area (F/cm

2
)
c velocity of light (2.998×10
10
cm/s)
C
BL
bit-line capacitance (C)
C
D
diffusion capacitance per unit area (F/cm
2
)
C
decap
decoupling capacitance (F)
C
deep
deep deletion capacitance per unit area, CV plot (F/cm
2
)
C
FG-CG
capacitance between floating and control gate (F)
xiii
xiv List of Symbols
C
GCh
gate to channel capacitance per unit area (F/cm
2

)
C
GD
gate to drain capacitance (F)
C
GS
gate to source capacitance (F)
C
HF
high-frequency capacitance per unit area, CV plot (F/cm
2
)
C
i
intrinsic capacitance, varactor (F)
C
ILD
inter-level dielectric capacitance (F)
C
inv
silicon inversion capacitance per unit area, CV plot (F/cm
2
)
C
j
junction capacitance (F)
C
jE
emitter-base junction capacitance (F)
C

jC
collector-base junction capacitance (F)
C
L
atomic concentration in liquid state (cm
−3
)
C
L
load capacitance (F)
C
LF
low-frequency capacitance per unit area, CV plot (F/cm
2
)
C
max
maximum capacitance per unit area, CV plot (F/cm
2
)
C
min
minimum capacitance per unit area, CV plot (F/cm
2
)
C
ox
oxide capacitance per unit area, CV plot (F/cm
2
)

C
par
parasitic capacitance (F)
C
PMD
pre-metal dielectric capacitance (F)
C
poly
polysilicon, e.g., depletion capacitance per unit area, (F/cm
2
)
C
S
atomic concentration in solid state (cm
−3
)
C
S
storage node capacitance (F)
C
Si
silicon capacitance per unit area, CV plot (F/cm
2
)
C
Sidep
silicon depletion capacitance per unit area, CV plot (F/cm
2
)
C

SiFB
silicon capacitance at flatband per unit area, CV plot (F/cm
2
)
C
Simin
silicon minimum capacitance per unit area, CV plot (F/cm
2
)
C
STI
shallow-trench capacitance (F)
d distance (cm)
D diffusion constant (cm
2
/s)
˜
D effective diffusion constant (cm
2
/s)
D
n
electron diffusion constant (cm
2
/s)
D
p
hole diffusion constant (cm
2
/s)

E energy (eV)
E electric field (V/cm)
e tensile strain (Pa)
E
C
critical field (V/cm)
E
C
bottom of conduction band energy level (eV)
E
CNL
charge neutrality level (eV)
E
D
donor energy level (eV)
E
F
Fermi level (eV)
E
Fn
electron quasi-Fermi level (eV)
E
Fp
hole quasi-Fermi level (eV)
E
g
energy gap (eV)
E
grad
field induced by grading Ge profile (V/cm)

Ei intrinsic silicon energy level (eV)
List of Symbols xv
E
i
ionization energy (eV)
E
i(A)
acceptor ionization energy (eV)
E
i(D)
donor ionization energy (eV)
E
n
nitride field Q
n
≈ 0(V/cm)
E
ox
oxide field (V/cm)
E
OO
characteristic tunneling energy (eV)
E
P
phonon energy (eV)
E
peak
peak electric field (V/cm)
E
s

surface field (V/cm)
E
Si
field in silicon (V/cm)
E
T
trap energy level (eV)
E
V
top of valence band energy level (eV)
E
x
field in silicon normal to surface (V/cm)
E
y
surface field parallel to silicon surface (V/cm)
F force (N)
F dimensionless electric field (F-function)
f frequency (Hz)
f(E) Fermi-function
f
T
gain-bandwidth product, cut-off frequency (Hz)
f
max
maximum frequency of operation (Hz)
G constant
G bulk generation rate (cm
−3
·s

−1
)
g
D
channel (drain) conductance (S)
g
D-lin
linear channel (drain) conductance (S)
g
D-sat
saturated channel (drain) conductance (S)
g
m
transconductance (S)
g
m-lin
linear transconductance (S)
g
m-sat
saturated transconductance (S)
GR generation-recombination
G
0
lumped JFET parameter
I current (A)
I
B
base current (A)
I
B

body current (A)
I
BC
base-collector current (A)
I
BE
base-emitter current (A)
I
C
collector current (A)
I
CBO
collector-base current, emitter open (A)
I
CEO
collector-emitter current, base open (A)
I
Csat
collector saturation current (A)
I
D
drain current (A)
I
Diff
diffusion current (A)
I
Dsat
saturated drain current (A)
I
D0

drain current per channel-square at threshold (A)
I
E
emitter current (A)
I
EBO
emitter-base current, collector open (A)
xvi List of Symbols
I
Esat
emitter saturation current (A)
I
F
forward-bias current (A)
I
G
gate current (A)
I
gen
generation current (A)
I
gen-bulk
bulk generation current (A)
I
gen-surf
surface generation current (A)
I
H
holding current, latch-up (A)
I

leak
total leakage current (A)
I
n
electron current (A)
i
n
noise current (A)
I
NW
current in n-well (A)
I
off
MOSFET off-current (A)
I
p
hole current (A)
I
PT
punch-through current (A)
I
PT0
current at onset of punch-through (A)
I
PW
current in p-well (A)
I
R
reverse-bias current at V
G

= V
T
(A)
I
r
surface recombination current (A)
I
S
source current (A)
I
S
saturation current (A)
I
s
surface current (A)
I
sB
base saturation current (A)
I
sC
collector saturation current (A)
I
0
drain current at V
G
= V
T
(A)
j current density (A/cm
2

)
j
direct
direct tunneling current density (A/cm
2
)
j
F
forward current density (A/cm
2
)
j
FN
Fowler-Nordheim tunneling current density (A/cm
2
)
j
G
gate current density (A/cm
2
)
j
n
electron current density (A/cm
2
)
j
n(dif)
diffusion electron current density (A/cm
2

)
j
p
hole current density (A/cm
2
)
j
p(dif)
diffusion hole current density (A/cm
2
)
j
R
reverse current density (A/cm
2
)
j
s
saturation current density (A/cm
2
)
j
T
total current density (A/cm
2
)
K dielectric constant =
ε
/
ε

0
k Boltzmann constant ≈ 8.618×10
−5
eV/K
k wave number (cm
−1
)
k
l
dimensionless resolution factor
k
seg
segregation coefficient
kT thermal energy (=0.0258eV at 300 K)
kT/q thermal voltage (=0.0258V at 300 K)
L length (cm)
List of Symbols xvii
L inductance (H)
L
D
Debye length (cm)
L
D
drawn length (cm)
L
E
emitter length (cm)
L
E
electrical length, e.g., resistor (cm)

L
e
extrinsic Debye length (cm)
L
eff
effective channel length (cm)
l
eff
effective mean-free path (cm)
L
I
impact-ionization mean-free path (cm)
L
i
intrinsic Debye length (cm)
L
met
metallurgical channel length (cm)
L
n
electron diffusion length (cm)
L
nB
electron diffusion length in base (cm)
L
p
hole diffusion length (cm)
L
pE
hole diffusion length in emitter (cm)

L
poly
polysilicon line-width, channel length (cm)
L
r
optical phonon mean-free path (cm)
L
T
contact transfer length (cm)
M multiplication factor
m
D
density of states effective mass (kg)
m
0
electron mass (≈ 9.1 ×10
−31
kg)
m
∗
n
electron effective mass (kg)
m
ox
oxide electron effective mass (kg)
m
∗
p
hole effective mass (kg)
N number of electrons per unit area (cm

−2
)
n electron concentration (cm
−3
)
¯n thermal equilibrium electron concentration (cm
−3
)
n number of squares
n ideality factor
n index of refraction
n number of circuits
NA numerical aperture
N
A
acceptor concentration (cm
−3
)
N
−
A
ionized acceptor concentration (cm
−3
)
N
A0
acceptor concentration at x = 0 (cm
−3
)
N

A
(x) acceptor concentration as function of depth (cm
−3
)
N
B
background dopant concentration (cm
−3
)
N
B
concentration of lightly-doped region (cm
−3
)
n
b
electron concentration in bulk (cm
−3
)
N
C
effective density of states at conduction band edge (cm
−3
)
N
D
donor concentration (cm
−3
)
N

+
D
ionized donor concentration (cm
−3
)
N
D
(x) donor concentration as function of depth (cm
−3
)
N
D0
donor concentration at x = 0 (cm
−3
)
N
f
number of fixed oxide charges per unit area (=Q
f
/q cm
−2
)
xviii List of Symbols
N
I
number of mobile ions per unit area (cm
−2
)
n
i

intrinsic carrier concentration (cm
−3
)
n
i0
intrinsic carrier concentration without energy-gap lowering (cm
−3
)
N
inv
number of inversion electrons per unit area (cm
−2
)
N
it
number interface traps per unit area (cm
−2
)
NM noise margin
NM
H
high noise margin
NM
L
low noise margin
n
n
majority electron concentration in n-region (cm
−3
)

¯n
n
thermal equilibrium electron concentration in n-region (cm
−3
)
n
n0
electron concentration in n-region at x = 0 (cm
−3
)
n
p
minority electron concentration in p-region (cm
−3
)
¯n
p
thermal equilibrium electron concentration in p-region (cm
−3
)
n
p0
electron concentration in p-region at x = 0 (cm
−3
)
n
s
surface electron concentration (cm
−3
)

N
s
number of secondary carrier pairs
n
sL
surface electron concentration at drain (cm
−3
)
n
so
surface electron concentration at source (cm
−3
)
N
t
density of generation-recombination centers (cm
−3
)
N
teff
effective density of generation-recombination centers (cm
−3
)
N
V
effective density of states at valence band edge (cm
−3
)
N
0

fixed diffusion-source concentration (cm
−3
)
n
0
electron concentration at x = 0 (cm
−3
)
O
i
concentration of interstitial oxygen (cm
−3
)
P parameter
P perimeter (cm)
P power (W)
P probability
p hole concentration (cm
−3
)
p momentum (N·s)
¯p thermal equilibrium hole concentration (cm
−3
)
p
b
bulk hole concentration (cm
−3
)
P

j
junction perimeter (cm)
p
n
concentration of minority holes in n-region (cm
−3
)
¯p
n
thermal equilibrium hole concentration in n-region (cm
−3
)
p
n0
hole concentration in n-region at x = 0 (cm
−3
)
¯p
n0
equilibrium minority hole concentration at x = 0 (cm
−3
)
p
p
concentration of majority holes in p-region (cm
−3
)
¯p
p
thermal equilibrium hole concentration in p-region (cm

−3
)
¯p
p0
equilibrium majority hole concentration at x = 0 (cm
−3
)
p
p0
hole concentration in p-region at x = 0 (cm
−3
)
p
s
surface hole concentration (cm
−3
)
P
standby
standby power (W)
Q charge per unit area (C/cm
2
)
Q quality factor
List of Symbols xix
q electron charge (≈1.6×10
−19
C)
Q
B

minority-carrier charge in base (C)
Q
b
bulk depletion charge per unit area (C/cm
2
)
Q
bmax
maximum bulk depletion charge per unit area (C/cm
2
)
Q
b-deep
bulk charge in deep depletion per unit area (C/cm
2
)
Q
eff
effective dielectric charge per unit area (C/cm
2
)
Q
f
oxide fixed charge per unit area (C/cm
2
)
Q
it
silicon-oxide interface trap charge per unit area (C/cm
2

)
Q
itm
gate-insulator interface trap charge per unit area (C/cm
2
)
Q
m
charge induced at gate-oxide interface per unit area (C/cm
2
)
Q
m
mobile charge per unit area (C/cm
2
)
Q
max
maximum quality factor
Q
n
surface electron charge per unit area (C/cm
2
)
Q
ot
oxide trap charge per unit area (C/cm
2
)
Q

p
surface hole charge per unit area (C/cm
2
)
Q
S
stored charge per unit area (C/cm
2
)
Q
s
surface charge per unit area (C/cm
2
)
R resistance (Ω)
r radius of curvature (cm)
r correlation coefficient
r fraction
r
A
Auger recombination rate (cm
6
/s)
R
B
base resistance (Ω)
R
Bext
extrinsic base resistance (Ω)
R

Bint
intrinsic base resistance (Ω)
R
B0
base resistance without applied bias (Ω)
R
C
collector resistance (Ω)
R
C
contact resistance (Ω)
R
Ch
channel resistance (Ω)
R
D
drain resistance (Ω)
R
E
emitter resistance (Ω)
r
E
emitter dynamic resistance (=kT/qI
C
, Ω)
R
ext
extrinsic resistance (Ω)
R
ext-S

source extrinsic resistance (Ω)
R
ext-D
drain extrinsic resistance (Ω)
R
G
gate resistance (Ω)
R
L
load resistance (Ω)
R
LDD
resistance of lightly-doped drain region (Ω)
R
N
noise resistance (Ω)
R
NBL
n-buried layer resistance (Ω)
R
p
parallel resistance (Ω)
R
p
projected range (cm)
R
PBL
p-buried layer resistance (Ω)
R
pinch

intrinsic-base (pinched) resistance (Ω)
xx List of Symbols
R
S
source resistance (Ω)
R
S
sheet resistance (Ω/Square)
R
SD
source-drain resistance (Ω)
R
Sp
spreading resistance (Ω)
R
S0
sheet resistance at T = T
0
(Ω/Square)
R
wire
wiring resistance (Ω)
r
0
output wiring resistance (Ω)
S subthreshold swing (V/decade)
s, s
0
surface recombination velocity (cm/s)
s

i
current noise power spectral density (A/
√
Hz)
s
v
voltage noise power spectral density (V/
√
Hz)
t time (s)
t thickness (cm)
T temperature (K)
T
0
reference temperature (K)
t
eq
equivalent oxide thickness (cm)
t
metal
metal thickness (cm)
T
N
noise temperature (K)
t
n
nitride thickness (cm)
t
ox
oxide thickness (cm)

t
ox-phys
physical oxide thickness (cm)
t
poly
polysilicon thickness (cm)
t
Si
path-length in silicon (cm)
t
silicide
silicide thickness (cm)
t
STI
shallow-trench isolation thickness (cm)
U generation-recombination rate (cm
−3
· s
−1
)
U
s
surface generation rate (cm
−3
· s
−1
)
u dimensionless Fermi potential (=q
φ
/kT)

u
b
dimensionless bulk Fermi potential (=q
φ
b
/kT)
u
s
dimensionless surface Fermi potential (=q
φ
s
/kT)
u(x) dimensionless Fermi potential versus depth x [=q
φ
(x)/kT]
v velocity (cm/s)
v dimensionless potential (=q
ψ
/kT)
V
A
Early voltage (V)
V
a
applied voltage (V)
V
B
, V
BS
body to source voltage (V)

V
b
barrier height (V)
V
b
built-in voltage (V)
V
BC
collector-base voltage (V)
V
BE
base-emitter voltage (V)
V
CBO
collector-base voltage, emitter open (V)
V
CBS
collector-base voltage, emitter shorted to base (V)
V
CC
power supply voltage, bipolar transistor (V)
V
CE
collector-emitter voltage (V)
V
CEO
collector-emitter voltage, base open (V)
List of Symbols xxi
V
CEsat

collector saturation voltage (V)
V
Ch
channel to source voltage, FET (V)
V
D
, V
DS
drain to source voltage
v
d
drift velocity (cm/s)
V
DA
measured dielectric absorption (V)
V
DD
power supply voltage, MOSFET (V)
V
Dsat
saturation drain voltage, MOSFET (V)
v
dy
drift velocity along surface, in y-direction (cm/s)
V
EBS
emitter-base voltage, collector shorted to base (V)
V
F
forward voltage (V)

V
FB
flatband voltage (V)
V
G
,V
GS
gate to source voltage (V)
V
H
holding voltage, latch-up (V)
V
IH
high input voltage (V)
V
IHmax
maximum high input voltage (V)
V
IHmin
minimum high input voltage (V)
V
IL
low input voltage (V)
V
ILmax
maximum low input voltage (V)
V
ILmin
minimum low input voltage (V)
V

j
junction voltage (V)
V
jG
junction to gate voltage, gated diode (V)
v
n
electron velocity (cm/s)
V
OH
high output voltage
V
OHmax
maximum high output voltage
V
OHmin
minimum high input voltage
V
ox
voltage across oxide (V)
V
P
pinch-off voltage (V)
v
p
hole velocity (cm/s)
V
PT
punch-through voltage (V)
V

R
reverse voltage (V)
V
RD
read voltage (V)
V
SS
typically ground potential, MOSFET (0 V)
v
s
dimensionless surface potential (=qψ
s
/kT)
v
sat
saturation velocity (cm/s)
V
T
threshold voltage (V)
V
T-drain
threshold voltage at drain (V)
v
th
thermal velocity (≈10
7
cm/s at 300 K)
V
T-source
threshold voltage at source (V)

V
T0
threshold voltage for zero floating-gate charge (V)
v(x) dimensionless potential versus depth [=qψ(x)/kT]
v
0
initial velocity (cm/s)
W width (cm)
W
b
neutral base width (cm)
W
Contact
contact width (cm)
W
D
drawn width (cm)
xxii List of Symbols
W
E
emitter width (cm)
W
E
electrical width (cm)
W
eff
effective width (cm)
WL word-line
W
Metal

metal width (cm)
W
n
width of neutral n-region (cm)
W
p
width of neutral p-region (cm)
W
Total
sum of all on-chip MOSFET width (cm)
W
Via
via width (cm)
x depth normal to silicon surface (cm)
x
Ch
channel depth below the surface, thickness (cm)
x
d
depletion width (cm)
x
dD
depletion width at MOSFET drain (cm)
x
d-deep
depletion depth in deep depletion (cm)
x
d-field
depletion width under field oxide (cm)
x

d-inv
steady-state depletion depth in inversion (cm)
x
d-lat
lateral junction depletion width at surface (cm)
x
dmax
maximum depletion depth below surface (cm)
x
dn
depletion width in n-side of pn junction (cm)
x
dp
depletion width in p-side of pn junction (cm)
x
dS
depletion width at MOSFET source (cm)
x
ds
,x
dsurf
junction depletion width at surface intercept (cm)
x
i
depth below surface where n = p = n
i
(cm)
x
J
junction depth (cm)

x
jC
collector-base junction depth (cm)
x
JE
emitter-base junction depth (cm)
x
jlat
, x
jl
lateral extent of junction at surface (cm)
x
m
depth of potential peak, image-force barrier lowering (cm)
y direction from source to drain
α
grounded base current gain (=I
C
/I
E
)
α
temperature coefficient of resistance (K
−1
)
α
F
forward grounded base current gain (=I
C
/I

E
)
α
i
impact ionization rate (cm
−1
)
α
R
reverse grounded base current gain (=I
C
/I
E
)
α
T
base transport factor
α
T
pre-tunneling factor
β
grounded emitter current gain (= I
C
/I
B
)
β
=
μ
eff

·C
ox
·W/L (MOSFET)
β
F
forward grounded emitter current gain (=I
C
/I
B
)
β
R
reverse grounded emitter current gain (=I
C
/I
B
)
β
R
ratio of NMOS
β
to PMOS
β
γ
injection efficiency
γ
n
electron injection efficiency, NPN
γ
n

= I
n
/(I
n
+ I
p
)
γ
p
hole injection efficiency, PNP
γ
p
= I
p
/(I
n
+ I
p
)
δ
thickness of interface barrier gap (cm)
List of Symbols xxiii
δ
L
length of pinch-off region (cm)
Δ width of gap layer (cm)
Δ voltage drop across interface oxide (V)
ΔE
C
change (offset) in minimum conduction band edge (eV)

ΔE
g
change in energy bandgap (eV)
ΔE
V
change (offset) in maximum valence band edge (eV)
ΔI
B
increment in base current (A)
ΔI
C
increment in collector current (A)
ΔI
E
increment in emitter current (A)
ΔL change in channel length (cm)
Δn change in electron concentration (cm
−3
)
Δn
p0
change in minority-electron concentration at x = 0 (cm
−3
)
Δp change in hole concentration (cm
−3
)
Δp
n0
change in minority-hole concentration at x = 0 (cm

−3
)
ΔV
BE
increment in emitter-base forward voltage (V)
ΔV
G
increment in gate voltage (V)
ΔV
R
increment in reverse voltage (V)
ΔV
T
change in threshold voltage (V)
ΔW change in channel width (cm)
Δ
φ
barrier lowering (eV)
ε
0
permittivity of free space (≈8.86 ×10
−14
F/cm)
ε
gap
dielectric constant of interface gap
ε
ox
oxide dielectric constant (≈3.9)
ε

n
nitride dielectric constant (≈7.0)
ε
Si
silicon dielectric constant (≈11.7)
η
multiplier of inversion-layer concentration to calculate field
θ
aperture
θ
mobility degradation factor (V
−1
)
κ
same as K = ε/ε
0
λ
wavelength (cm)
λ
channel length modulation factor (= −1/V
A
, V
−1
)
λ
mean-free path (cm)
λ
De Broglie wavelength (cm)
λ
i

average interstitial point-defect diffusion length (cm)
λ
0
wavelength in vacuum (cm)
μ
mobility (cm
2
/V·s)
μ
eff
effective mobility (cm
2
/V·s)
μ
h
high mobility, normal to crystallographic axis (cm
2
/V·s)
μ
I
ionized-impurity scattering limited mobility (cm
2
/V·s)
μ
l
lattice-scattering limited mobility (cm
2
/V·s)
μ
l

low mobility, along crystallographic axis (cm
2
/V·s)
μ
ln
electron lattice mobility (cm
2
/V·s)
μ
lp
hole lattice mobility (cm
2
/V·s)
μ
n
electron mobility (cm
2
/V·s)
˜
μ
n
effective electron mobility (cm
2
/V·s)
xxiv List of Symbols
μ
p
hole mobility (cm
2
/V·s)

˜
μ
p
effective hole mobility (cm
2
/V·s)
μ
0
surface mobility at V
G
= V
T
(cm
2
/V·s)
ρ
resistivity (Ω-cm)
ρ
volume charge concentration (C/cm
3
)
ρ
C
specific contact resistance (Ω-cm
2
)
ρ
0
resistivity at T = T
0

(Ω-cm)
σ
conductivity (Ω
−1
cm
−1
or S/cm)
σ
charge sheet (C/cm
2
)
σ
surface recombination velocity in buried plane (cm/s)
σ
capture cross-section (cm
2
)
σ
VT
variance in threshold voltage (V)
σ
Δ
P
variance in parameter P
τ
lifetime (s)
τ
mean-time between collisions (s)
τ
time constant (s)

τ
B
base transit time (s)
τ
C
collector transit time (s)
τ
E
emitter transit time (s)
τ
n
electron transit time, lifetime (s)
τ
nB
electron transit time, lifetime in base (s)
τ
p
hole transit time, lifetime (s)
τ
pE
hole transit time, lifetime in emitter (s)
τ
SRH
Shockley-Read-Hall recombination lifetime (s)
τ
0
assumed same lifetime for electrons and holes (s)
φ
potential (V)
φ

dose (cm
−2
)
φ
I
pulsed-shaped implant dose (cm
−2
)
φ
B
barrier height (V)
φ
b
bulk Fermi potential (V)
φ
bn
bulk electron Fermi potential (V)
φ
bp
bulk hole Fermi potential (V)
φ
Fn
electron quasi Fermi potential (V)
φ
Fp
hole quasi Fermi potential (V)
φ
m
metal (gate) workfunction (V)
φ

ms
workfunction difference between metal (gate) and Si (V)
φ
m-app
apparent metal (gate) workfunction (V)
φ
n
electron Fermi potential (V)
φ
p
hole Fermi potential (V)
φ
s
surface Fermi potential (V)
φ
Si
silicon workfunction (V)
φ
0
surface neutrality level (V)
χ
electron affinity (V)
χ
stress (Pa)
χ
Si
silicon electron affinity (V)
List of Symbols xxv
χ
ox

silicon-dioxide electron affinity (V)
ψ
band-bending, potential (V)
ψ
s
surface potential (V)
ψ
s-field
surface potential under field oxide (V)
ω
angular frequency (s
−1
)
Chapter 1
Silicon Properties
1.1 Introduction
A review of silicon properties is important to understanding silicon components,
in particular modern components such as strained-silicon MOSFETs and hetero-
junction bipolar transistors. Several books cover this subject in detail. The objective
of this chapter is to highlight those features that are most important to silicon device
operation and characteristics.
1.2 Valence-Bond and Two-Carrier Concept
The valence-bond model is frequently used to qualitatively describe the properties of
semiconductors [1]. In this model, the covalent bond between two adjacent atoms
formed by two valence electrons, one from each atom contributing to the bond,
is visualized as localized bars along which electrons shuttle back and forth with
opposite spins (Fig. 1.1).
When a pure silicon crystal is near 0 K, all valence electrons remain locally bound
to their covalent bonds since they do not have sufficient energy to break loose. In
this case, no quasi-free electrons are generated and the crystal behaves like a perfect

insulator. As the temperature is increased, the amplitude of vibration of lattice atoms
increases around their equilibrium positions. A fraction of the vibrational energy
is transferred to valence electrons. Some electrons can acquire sufficient energy to
break loose from their bonds and move quasi freely in the crystal. Hence, the number
of quasi free electrons and holes (missing bond electrons) in the crystal increases as
the temperature is increased.
The energy required to break a silicon bond is an ionization energy (∼1.1eV)
which differs from the ionization energy of an isolated silicon atom (∼8eV) because
B. El-Kareh, Silicon Devices and Process Integration:Deep Submicron 1
and Nano-Scale Technologies,
c
 Springer Science+Business Media, LLC 2009