tinder, r. f. (2000). engineering digital design (2nd ed.)

Engineering
Digital
Design
Second
Edition,
Revised
This page intentionally left blank
Engineering
Digital
Design
Second
Edition,
Revised
by
RICHARD
F.
TINDER
School
of
Electrical Engineering
and
Computer Science
Washington
State
University
Pullman,
Washington
ACADEMIC
PRESS
A

Harcourt
Science
and
Technology
Company
SAN
DIEGO/SAN FRANCISCO/NEW YORK/BOSTON/LONDON/SYDNEY/TOKYO
J.

Copyright ©2000, Elsevier
Science
(USA).
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For the
sake
of
persons
of
different
types,
scientific
truth should
be
presented
in
different
forms,
and
should

be
regarded
as
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scientific,
whether
it
appears
in the
robust form
and
the
vivid
coloring
of
a
physical illustration,
or in the
tenuity
and
paleness
of
a
symbolic
expression.
James
Clerk Maxwell
Address
to the
Mathematics

and
Physical
Section,
British
Association
of
Sciences,
1870
This page intentionally left blank
Contents
Preface
xix
1.
Introductory
Remarks
and
Glossary
1
1.1
What
Is So
Special about Digital Systems?
1
1.2
The
Year
2000
and
Beyond?
3

1.3
A
Word
of
Warning
5
1.4
Glossary
of
Terms, Expressions,
and
Abbreviations
5
2.
Number
Systems,
Binary
Arithmetic,
and
Codes
31
2.1
Introduction
31
2.2
Positional
and
Polynomial
Representations
32

2.3
Unsigned Binary Number System
33
2.4
Unsigned Binary Coded
Decimal,
Hexadecimal,
and
Octal
34
2.4.1
The BCD
Representation
34
2.4.2
The
Hexadecimal
and
Octal Systems
36
2.5
Conversion between Number Systems
37
2.5.1 Conversion
of
Integers
38
2.5.2 Conversion
of
Fractions

40
2.6
Signed Binary Numbers
43
2.6.1
Signed-Magnitude Representation
44
2.6.2 Radix Complement Representation
45
2.6.3 Diminished Radix Complement Representation
48
2.7
Excess
(Offset)
Representations
49
2.8
Floating-Point
Number Systems
49
2.9
Binary Arithmetic
52
2.9.1
Direct Addition
and
Subtraction
of
Binary
Numbers

52
2.9.2 Two's Complement Subtraction
53
2.9.3 One's Complement Subtraction
54
2.9.4 Binary Multiplication
55
2.9.5 Binary Division
58
2.9.6
BCD
Addition
and
Subtraction
62
2.9.7 Floating-Point Arithmetic
64
2.9.8 Perspective
on
Arithmetic Codes
67
2.10 Other
Codes
68
2.10.1
The
Decimal Codes
68
2.10.2
Error Detection

Codes
69
2.10.3 Unit Distance Codes
70
2.10.4
Character Codes
70
Further
Reading
72
Problems
72
ix
CONTENTS
3.
Background
for
Digital
Design
79
3.1
Introduction
79
3.2
Binary State Terminology
and
Mixed
Logic
Notation
79

3.2.1 Binary State Terminology
79
3.3
Introduction
to
CMOS Terminology
and
Symbology
82
3.4
Logic
Level Conversion:
The
Inverter
83
3.5
Transmission Gates
and
Tri-State Drivers
84
3.6 AND and OR
Operators
and
Their Mixed-Logic Circuit Symbology
87
3.6.1
Logic Circuit Symbology
for AND and OR 87
3.6.2 NAND Gate Realization
of

Logic
AND and OR 88
3.6.3
NOR
Gate Realization
of
Logic
AND and OR 89
3.6.4 NAND
and NOR
Gate Realization
of
Logic Level Conversion
90
3.6.5
The AND and OR
Gates
and
Their Realization
of
Logic
AND
and OR 92
3.6.6 Summary
of
Logic Circuit Symbols
for the AND and OR
Functions
and
Logic

Level Conversion
94
3.7
Logic Level Incompatibility: Complementation
95
3.8
Reading
and
Construction
of
Mixed-Logic Circuits
97
3.9 XOR and EQV
Operators
and
Their Mixed-Logic Circuit Symbology
98
3.9.1
The XOR and
EQV
Functions
of the XOR
Gate
100
3.9.2
The XOR and EQV
Functions
of the EQV
Gate
100

3.9.3 Multiple Gate Realizations
of the XOR and EQV
Functions
101
3.9.4
The
Effect
of
Active
Low
Inputs
to the XOR and EQV
Circuit Symbols
102
3.9.5 Summary
of
Conjugate
Logic Circuit Symbols
for
XOR
and
EQV
Gates
103
3.9.6 Controlled Logic Level Conversion
103
3.9.7 Construction
and
Waveform Analysis
of

Logic
Circuits Containing
XOR-Type Functions
104
3.10
Laws
of
B
oolean Algebra
105
3.10.1
NOT, AND,
and OR
Laws
106
3.10.2
The
Concept
of
Duality
107
3.10.3
Associative, Commutative, Distributive, Absorptive,
and
Consensus Laws
108
3.10.4
DeMorgan's Laws
110
3.11

Laws
of
XOR
Algebra
111
3.11.1
Two
Useful
Corollaries
114
3.11.2
Summary
of
Useful
Identities
115
3.12
Worked Examples
116
Further Reading
120
Problems
121
4.
Logic
Function
Representation
and
Minimization
131

4.1
Introduction
131
4.2 SOP and POS
Forms
131
4.2.1
The SOP
Representation
131
4.2.2
The POS
Representation
134
4.3
Introduction
to
Logic Function Graphics
137
4.3.1 First-Order
K-maps
138
4.3.2
Second-Order
K-maps
138
4.3.3 Third-Order K-maps
140
4.3.4 Fourth-Order K-maps
143

CONTENTS
xi
4.4
Karnaugh
Map
Function Minimization
144
4.4.1 Examples
of
Function Minimization
146
4.4.2 Prime Implicants
148
4.4.3 Incompletely
Specified
Functions: Don't Cares
150
4.5
Multiple
Output
Optimization
152
4.6
Entered Variable
K-map
Minimization
158
4.6.1 Incompletely
Specified
Functions

162
4.7
Function Reduction
of
Five
or
More Variables
165
4.8
Minimization Algorithms
and
Application
169
4.8.1
The
Quine-McCluskey
Algorithm
169
4.8.2 Cube Representation
and
Function Reduction
173
4.8.3 Qualitative Description
of the
Espresso Algorithm
173
4.9
Factorization, Resubstitution,
and
Decomposition

Methods
174
4.9.1 Factorization
175
4.9.2 Resubstitution Method
176
4.9.3 Decomposition
by
Using Shannon's Expansion Theorem
177
4.10 Design Area
vs
Performance
180
4.11
Perspective
on
Logic Minimization
and
Optimization
181
4.12
Worked
EV
K-map Examples
181
Further Reading
188
Problems
189

5.
Function
Minimization
by
Using K-map
XOR
Patterns
and
Reed-Muller
Transformation
Forms
197
5.1
Introduction
197
5.2
XOR-Type Patterns
and
Extraction
of
Gate-Minimum Cover
from
EV
K-maps
198
5.2.1 Extraction Procedure
and
Examples
200
5.3

Algebraic
Verification
of
Optimal
XOR
Function Extraction
from
K-maps
204
5.4
K-map Plotting
and
Entered Variable
XOR
Patterns
205
5.5
The
SOP-to-EXSOP
Reed-Muller
Transformation
207
5.6 The
POS-to-EQPOS
Reed-Muller
Transformation
208
5.7
Examples
of

Minimum Function Extraction
209
5.8
Heuristics
for
CRMT Minimization
217
5.9
Incompletely Specified Functions
218
5.10
Multiple Output Functions with Don't Cares
222
5.11
K-map
Subfunction
Partitioning
for
Combined CRMT
and
Two-Level
Minimization
225
5.12
Perspective
on the
CRMT
and
CRMT/Two-Level
Minimization Methods

229
Further Reading
229
Problems
230
6.
Nonarithmetic Combinational
Logic
Devices
237
6.1
Introduction
and
Background
237
6.1.1
The
Building Blocks
237
6.1.2
Classification
of
Chips
238
6.1.3 Performance Characteristics
and
Other Practical Matters
238
6.1.4 Part Numbering Systems
241

6.1.5
Design Procedure
241
xii
CONTENTS
6.2
Multiplexers
242
6.2.1 Multiplexer Design
242
6.2.2 Combinational Logic Design
with
MUXs
245
6.3
Decoders/Demultiplexers
248
6.3.1 Decoder Design
248
6.3.2 Combinational Logic Design with Decoders
251
6.4
Encoders
254
6.5
Code Converters
257
6.5.1
Procedure
for

Code Converter Design
257
6.5.2 Examples
of
Code Converter Design
257
6.6
Magnitude Comparators
265
6.7
Parity Generators
and
Error Checking Systems
273
6.8
Combinational Shifters
275
6.9
Steering Logic
and
Tri-State
Gate Applications
278
6.10
Introduction
to
VHDL
Description
of
Combinational Primitives

279
Further Reading
287
Problems
288
7.
Programmable
Logic
Devices
295
7.1
Introduction
295
7.2
Read-Only Memories
295
7.2.1 PROM Applications
299
7.3
Programmable Logic Arrays
301
7.3.1
PLA
Applications
302
7.4
Programmable Array Logic Devices
307
7.5
Mixed-Logic Inputs

to and
Outputs
from
ROMs, PLAs,
and PAL
Devices
310
7.6
Multiple
PLD
Schemes
for
Augmenting
Input
and
Output Capability
312
7.7
Introduction
to
FPGAs
and
Other
General-Purpose
Devices
317
7.7.1
AND-OR-Invert
and
OR-AND-Invert

Building Blocks
317
7.7.2
Actel
Field Programmable Gate Arrays
319
7.7.3
Xilinx
FPGAs
321
7.7.4 Other Classes
of
General-Purpose PLDs
328
7.8 CAD
Help
in
Programming
PLD
Devices
328
Further
Reading
330
Problems
331
8.
Arithmetic
Devices
and

Arithmetic
Logic
Units
(ALUs)
335
8.1
Introduction
335
8.2
Binary Adders
335
8.2.1
The
Half Adder
336
8.2.2
The
Full Adder
337
8.2.3 Ripple-Carry Adders
338
8.3
Binary
Subtracters
340
8.3.1 Adder/Subtractors
342
8.3.2 Sign-Bit Error Detection
343
8.4 The

Carry Look-Ahead Adder
345
8.5
Multiple-Number Addition
and the
Carry-Save Adder
349
8.6
Multipliers
350
8.7
Parallel Dividers
353
CONTENTS
xiii
8.8
Arithmetic
and
Logic Units
357
8.8.1
Dedicated
ALU
Design Featuring
R-C and CLA
Capability
358
8.8.2
The MUX
Approach

to ALU
Design
363
8.9
Dual-Rail Systems
and
ALUs with Completion Signals
369
8.9.1 Carry
Look-Ahead
Configuration
378
8.10
VHDL Description
of
Arithmetic Devices
380
Further Reading
383
Problems
385
9.
Propagation Delay
and
Timing
Defects
in
Combinational
Logic
391

9.1
Introduction
391
9.2
Static Hazards
in
Two-Level Combinational Logic Circuits
392
9.3
Detection
and
Elimination Hazards
in
Multilevel XOR-Type Functions
399
9.3.1
XOP and EOS
Functions
400
9.3.2 Methods
for the
Detection
and
Elimination
of
Static Hazards
in
Complex
Multilevel
XOR-type Functions

403
9.3.3 General Procedure
for the
Detection
and
Elimination
of
Static Hazards
in
Complex Multilevel XOR-Type Functions
408
9.3.4 Detection
of
Dynamic Hazards
in
Complex Multilevel XOR-Type
Functions
409
9.4
Function Hazards
412
9.5
Stuck-at Faults
and the
Effect
of
Hazard Cover
on
Fault Testability
412

Further Reading
413
Problems
415
10.
Introduction
to
Synchronous
State
Machine
Design
and
Analysis
419
10.1
Introduction
419
10.1.1
A
Sequence
of
Logic States
420
10.2 Models
for
Sequential Machines
421
10.3
The
Fully Documented State Diagram:

The Sum
Rule
424
10.4
The
Basic Memory Cells
428
10.4.1
The
Set-Dominant Basic Cell
428
10.4.2
The
Reset-Dominant Basic Cell
431
10.4.3
Combined Form
of the
Excitation
Table
433
10.4.4
Mixed-Rail Outputs
of the
Basic Cells
434
10.4.5 Mixed-Rail Output Response
of the
Basic Cells
435

10.5 Introduction
to
Flip-Flops
436
10.5.1
Triggering Mechanisms
437
10.5.2
Types
of
Flip-Flops
438
10.5.3 Hierarchical Flow Chart
and
Model
for
Flip-Flop
Design
438
10.6
Procedure
for FSM
(Flip-Flop)
Design
and the
Mapping Algorithm
440
10.7
The D
Flip-Flops: General

440
10.7.1
TheD-Latch
441
10.7.2
The RET D
Flip-Flop
444
10.7.3
The
Master-Slave
D
Flip-Flop
448
10.8
Flip-Flop
Conversion:
The T, JK
Flip-Flops
and
Miscellaneous
Flip-Flops
450
10.8.1
The T
Flip-Flops
and
Their Design
from
D

Flip-Flops
451
10.8.2
The JK
Flip-Flops
and
Their Design
from
D
Flip-Flops
453
10.8.3 Design
of T and D
Flip-Flops
from
JK
Flip-Flops
455
xiv
CONTENTS
10.8.4
Review
of
Excitation Tables
457
10.8.5
Design
of
Special-Purpose
Flip-Flops

and
Latches
459
10.9 Latches
and
Flip-Flops
with
Serious Timing Problems:
A
Warning
461
10.10 Asynchronous Preset
and
Clear Overrides
463
10.11
Setup
and
Hold-Time Requirements
of
Flip-Flops
465
10.12 Design
of
Simple Synchronous State Machines
with
Edge-Triggered Flip-
Flops:
Map
Conversion

466
10.12.1
Design
of a
Three-Bit Binary
Up/Down
Counter:
D-to-T
K-map
Conversion
466
10.12.2 Design
of a
Sequence Recognizer: D-to-JK K-map Conversion
471
10.13 Analysis
of
Simple State Machines
476
10.14
VHDL Description
of
Simple State Machines
480
10.14.1
The
VHDL
Behavorial
Description
of the RET D

Flip-flop
480
10.14.2
The
VHDL Behavioral Description
of a
Simple
FSM
481
Further Reading
482
Problems
483
11.
Synchronous
FSM
Design
Considerations
and
Applications
491
11.1
Introduction
491
11.2
Detection
and
Elimination
of
Output Race Glitches

491
11.2.1
ORG
Analysis Procedure Involving
Two
Race Paths
496
11.2.2
Elimination
of
ORGs
496
11.3
Detection
and
Elimination
of
Static Hazards
in the
Output
Logic
499
11.3.1
Externally Initiated Static Hazards
in the
Output Logic
500
11.3.2
Internally Initiated Static Hazards
in the

Output
of
Mealy
and
Moore FSMs
502
11.3.3
Perspective
on
Static Hazards
in the
Output Logic
of
FSMs
509
11.4 Asynchronous Inputs: Rules
and
Caveats
510
11.4.1
Rules Associated
with
Asynchronous Inputs
510
11.4.2
Synchronizing
the
Input
511
11.4.3

Stretching
and
Synchronizing
the
Input
512
11.4.4 Metastability
and the
Synchronizer
514
11.5 Clock Skew
517
11.6
Clock Sources
and
Clock Signal Specifications
520
11.6.1 Clock-Generating Circuitry
520
11.6.2 Clock Signal Specifications
521
11.6.3
Buffering
and
Gating
the
Clock
522
11.7
Initialization

and
Reset
of the
FSM: Sanity Circuits
522
11.7.1 Sanity Circuits
523
11.8
Switch Debouncing Circuits
526
11.8.1
The
Single-Pole/Single-Throw Switch
526
11.8.2
The
Single-Pole/Double-Throw
Switch
528
11.8.3
The
Rotary
Selector
Switch
529
11.9
Applications
to the
Design
of

More Complex State Machines
530
11.9.1 Design Procedure
530
11.9.2
Design Example:
The
One-
to
Three-Pulse
Generator
532
11.10
Algorithmic State Machine Charts
and
State Tables
536
11.10.1
ASM
Charts
537
11.10.2
State Tables
and
State Assignment Rules
539
11.11
Array Algebraic Approach
to
Logic Design

542
CONTENTS
XV
11.12
State Minimization
547
Further
Reading
549
Problems
551
12.
Module
and
Bit-Slice
Devices
561
12.1 Introduction
561
12.2
Registers
561
12.2.1
The
Storage (Holding) Register
562
12.2.2
The
Right
Shift

Register with Synchronous
Parallel
Load
562
12.2.3 Universal
Shift
Registers
with
Synchronous Parallel Load
565
12.2.4
Universal
Shift
Registers with Asynchronous Parallel Load
568
12.2.5 Branching Action
of a
4-Bit
USR 570
12.3 Synchronous Binary Counters
572
12.3.1
Simple
Divide-by-TV
Binary Counters
573
12.3.2 Cascadable
BCD
Up-Counters
575

12.3.3
Cascadable
Up/Down
Binary Counters
with
Asynchronous
Parallel Load
579
12.3.4 Binary
Up/Down
Counters with Synchronous Parallel Load
and
True
Hold Capability
581
12.3.5
One-B
it
Modular Design
of
Parallel Loadable
Up/Down
Counters with
True Hold
584
12.3.6
Perspective
on
Parallel Loading
of

Counters
and
Registers:
Asynchronous
vs
Synchronous
588
12.3.7
Branching Action
of a
4-Bit Parallel Loadable
Up/Down
Counter
589
12.4 Shift-Register Counters
590
12.4.1 Ring Counters
590
12.4.2 Twisted Ring Counters
593
12.4.3
Linear
Feedback
Shift
Register Counters
594
12.5 Asynchronous (Ripple) Counters
600
Further Reading
605

Problems
606
13.
Alternative
Synchronous
FSM
Architectures
and
Systems-Level
Design
613
13.1
Introduction
613
13.1.1
Choice
of
Components
to be
Considered
613
13.2 Architecture Centered around Nonregistered PLDs
614
13.2.1
Design
of the
One-
to
Three-Pulse
Generator

by
Using
a PLA
615
13.2.2
Design
of the
One-
to
Three-Pulse Generator
by
Using
a PAL
617
13.2.3
Design
of the
One-
to
Three-Pulse
Generator
by
Using
a ROM
618
13.2.4
Design
of a
More Complex
FSM by

Using
a ROM as the PLD 622
13.3
State Machine Designs Centered around
a
Shift
Register
626
13.4
State Machine Designs Centered around
a
Parallel Loadable
Up/Down
Counter
632
13.5
The
One-Hot Design Method
636
13.5.1
Use of
ASMs
in
One-Hot Designs
640
13.5.2 Application
of the
One-Hot Method
to a
Serial

2's
Complementer
643
13.5.3
One-Hot Design
of a
Parallel-to-Serial
Adder/Subtractor Controller
645
13.5.4
Perspective
on the Use of the
One-Hot Method:
Logic
Noise
and Use
of
Registered PLDs
647
xvi
CONTENTS
13.6 System-Level Design: Controller, Data Path,
and
Functional Partition
649
13.6.1
Design
of a
Parallel-to-Serial
Adder/Subtractor Control System

651
13.6.2 Design
of a
Stepping Motor Control System
655
13.6.3 Perspective
on
System-Level Design
in
This Text
666
13.7 Dealing with
Unusually
Large Controller
and
System-Level Designs
666
Further Reading
668
Problems
670
14.
Asynchronous
State
Machine
Design
and
Analysis:
Basic
Concepts

683
14.1
Introduction
683
14.1.1 Features
of
Asynchronous FSMs
684
14.1.2
Need
for
Asynchronous
FSMs
685
14.2
The
Lumped Path Delay Models
for
Asynchronous FSMs
685
14.3 Functional Relationships
and the
Stability Criteria
687
14.4
The
Excitation Table
for the LPD
Model
688

14.5 State Diagrams, K-maps,
and
State Tables
for
Asynchronous FSMs
689
14.5.1
The
Fully Documented State Diagram
689
14.5.2 Next-State
and
Output
K-maps
690
14.5.3
State Tables
691
14.6 Design
of the
Basic Cells
by
Using
the LPD
Model
692
14.6.1
The
Set-Dominant Basic Cell
692

14.6.2
The
Reset-Dominant Basic Cell
694
14.7
Design
of the
Rendezvous Modules
by
Using
the
Nested
Cell
Model
695
14.8 Design
of the RET D
Flip-Flop
by
Using
the LPD
Model
698
14.9 Design
of the RET JK
Flip-Flop
by
Flip-Flop
Conversion
700

14.10
Detection
and
Elimination
of
Timing Defects
in
Asynchronous
FSMs
701
14.10.1 Endless Cycles
702
14.10.2 Races
and
Critical Races
703
14.10.3
Static Hazards
in the NS and
Output
Functions
705
14.10.4
Essential Hazards
in
Asynchronous FSMs
711
14.10.5
Perspective
on

Static Hazards
and
E-hazards
in
Asynchronous
FSMs
718
14.11
Initialization
and
Reset
of
Asynchronous FSMs
719
14.12
Single-Transition-Time
Machines
and the
Array
Algebraic
Approach
720
14.13
Hazard-Free Design
of
Fundamental Mode State Machines
by
Using
the
Nested

Cell Approach
730
14.14
One-Hot Design
of
Asynchronous State Machines
734
14.15
Perspective
on
State Code Assignments
of
Fundamental Mode FSMs
738
14.16
Design
of
Fundamental Mode FSMs
by
Using PLDs
740
14.17
Analysis
of
Fundamental Mode State Machines
741
Further
Reading
758
Problems

759
15. The
Pulse
Mode
Approach
to
Asynchronous
FSM
Design
773
15.1 Introduction
773
15.2 Pulse Mode Models
and
System Requirements
773
15.2.1
Choice
of
Memory Elements
774
15.3
Other Characteristics
of
Pulse Mode FSMs
777
15.4 Design Examples
779
15.5 Analysis
of

Pulse Mode
FSMs
788
CONTENTS
xvn
15.6 Perspective
on the
Pulse Mode Approach
to FSM
Design
795
Further Reading
796
Problems
797
16.
Externally
Asynchronous/Internally Clocked
(Pausable)
Systems
and
Programmable
Asynchronous
Sequencers
805
16.1 Introduction
805
16.2 Externally
Asynchronous/Internally
Clocked Systems

and
Applications
806
16.2.1 Static Logic DFLOP Design
807
16.2.2 Domino Logic DFLOP Design
812
16.2.3
Introduction
to
CMOS Dynamic Domino Logic
814
16.2.4
EAIC
System Design
816
16.2.5
System
Simulations
and
Real-Time
Tests
817
16.2.6 Variations
on the
Theme
820
16.2.7
How
EAIC FSMs

Differ
from
Conventional Synchronous FSMs
821
16.2.8 Perspective
on
EAIC Systems
as an
Alternative Approach
to FSM
Design
822
16.3 Asynchronous Programmable Sequencers
823
16.3.1
Microprogrammable
Asynchronous Controller Modules
and
System Architecture
823
16.3.2 Architecture
and
Operation
of the MAC
Module
824
16.3.3 Design
of the MAC
Module
827

16.3.4
MAC
Module Design
of a
Simple
FSM 830
16.3.5
Cascading
the MAC
Module
832
16.3.6
Programming
the MAC
Module
833
16.3.7 Metastability
and the MAC
Module:
The
Final Issue
834
16.3.8
Perspective
on MAC
Module
FSM
Design
834
16.4

One-Hot
Programmable Asynchronous Sequencers
835
16.4.1
Architecture
for
One-Hot Asynchronous Programmable
Sequencers
835
16.4.2 Design
of a
Four-State Asynchronous One-Hot Sequencer
837
16.4.3 Design
and
Operation
of a
Simple
FSM by
Using
a
Four-State
One-Hot Sequencer
838
16.4.4
Perspective
on
Programmable Sequencer Design
and
Application

839
16.5
Epilogue
to
Chapter
16 842
Further Reading
842
Problems
844
A
Other
Transistor
Logic
Families
849
A.
1
Introduction
to the
Standard NMOS Logic Family
849
A.2
Introduction
to the TTL
Logic Family
850
A.3
Performance Characteristics
of

Important
1C
Logic
Families
852
Further Reading
852
B
Computer-Aided
Engineering
Tools
855
B.I
Productivity Tools Bundled
with
this Text
855
B.2
Other
Productivity Tools
855
Further Reading
857
xviii
CONTENTS
C
IEEE
Standard
Symbols
859

C.I
Gates
859
C.2
Combinational Logic Devices
859
C.3
Flip-Flops,
Registers,
and
Counters
860
Further Reading
862
Index
863
Preface
TEXT
OVERVIEW
This text emphasizes
the
successful engineering design
of
digital devices
and
machines
from
first
principles.
A

special
effort
has
been made
not to
"throw"
logic circuits
at the
reader
so
that
questions remain
as to how the
circuits came about
or
whether
or not
they will
function
correctly.
An
understanding
of the
intricacies
of
digital circuit design, particularly
in the
area
of
sequential machines,

is
given
the
highest priority
— the
emphasis
is on
error-free
operation. From
an
engineering point
of
view,
the
design
of a
digital device
or
machine
is
of
little
or no
value unless
it
performs
the
intended operation(s) correctly
and
reliably.

Both
the
basics
and
background
fundamentals
are
presented
in
this text.
But it
goes well
beyond
the
basics
to
provide
significant
intermediate-to-advanced
coverage
of
digital design
material, some
of
which
is
covered
by no
other text.
In

fact,
this text attempts
to
provide
course
coverage
at
both
the first and
second
levels
—
an
ambitious undertaking.
The aim
is
to
provide
the
reader with
the
tools necessary
for the
successful design
of
relatively
complex digital systems
from
first
principles.

In
doing
so, a firm
foundation
is
laid
for the
use of CAD
methods that
are
necessary
to the
design
of
large systems.
In a
related sense,
VHDL behavioral
and
architectural descriptions
of
various machines, combinational
and
sequential,
are
provided
at
various points
in the
text

for
those instructors
and
students
who
wish
to
have
or
require
a
hardware description language
in the
study
of
digital design.
The
text
is
divided into
16
relatively small chapters
to
provide maximum versatility
in its
use.
These
chapters range
from
introductory remarks

to
advanced topics
in
asynchronous
systems.
In
these chapters
an
attempt
is
made
to
replace verbosity
by
illustration. Students
generally
do not
like
to
read lengthy verbal developments
and
explanations when simple
illustrations
suffice.
Well more than
600 figures and
tables help
to
replace lengthy expla-
nations.

More than 1000 examples, exercises,
and
problems (worked
and
unworked, single
and
multiple part)
are
provided
to
enhance
the
learning process. They range
in
complex-
ity
from
simple algebraic manipulations
to
multipart system-level designs, each carefully
chosen with
a
specific purpose
in
mind. Annotated references appear
at the end of
each
chapter,
and an
appendix

at the end of the
text provides
the
details
of
subjects thought
to
be
peripheral
to the
main thrust
of the
text. Chapter
1
breaks with tradition
in
providing
a
complete glossary
of
terms, expressions,
and
abbreviations that serves
as a
conspicuous
and
useful
source
of
information.

SUBJECT
AREAS
OF
PARTICULAR
STRENGTH
IN
THIS
TEXT
Like
others,
this
text
has its
subject areas
of
strengths
—
those
that
are
uniquely
presented
in
sufficient
detail
as to
stand
out as
significant
didactic

and
edifying contributions.
This
text
xix
XX
PREFACE
breaks
with
tradition
in
providing unique coverage
in
several important areas.
In
addition
to
the
traditional
coverage,
the
following
20
subject areas
are of
particular strength
in
this text:
1.
Thorough coverage

of
number systems, arithmetic methods
and
algorithms,
and
codes
2.
Mixed logic notation
and
symbology used throughout
the
text
3.
Emphasis
on
CMOS logic circuits
4.
Unique treatment
of
conventional Boolean algebra
and XOR
algebra
as
these subjects
relate
to
logic design
5.
Entered variable mapping methods
as

applied throughout
the
text
to
combinational
and
sequential logic design
6.
Applications
of
Reed-Muller
transformation
forms
to
function
minimization
7.
Nonarithmetic
combinational logic devices such
as
comparators, shifters,
and
FPGAs
8.
Arithmetic devices such
as
carry-save adders, multipliers,
and
dividers
9.

Three
uniquely different
ALU
designs, including
an
introduction
to
dual-rail systems
and
ALUs with completion signal
and
carry look-ahead capability
10.
Detection
and
elimination methods
for
static hazards
in
two-level
and
multilevel (e.g.,
XOR-type) circuits including
the use of
binary
decision
diagrams (BDDs)
11.
Design
and

analysis
of flip-flops
provided
in a
simple, well organized fashion
12.
Detection
and
elimination
of
timing defects
in
synchronous sequential circuits
13.
Input synchronization
and
debouncing,
and FSM
initialization
and
reset methods
14.
Use of
unique modular methods
in the
design
of
shift
registers
and

counters
15.
Complete coverage
of
ripple counters, ring counters
and
linear feedback
shift
register
(LFSR
and
ALFSR) counters
16.
Application
of the
array
algebraic
and
one-hot
approaches
to
synchronous
FSM
design
17.
Detection
and
elimination
of
timing

defects
in
asynchronous
fundamental
mode FSMs
18.
Design
and
analysis
of
asynchronous FSMs including
the
nested cell approach, single
transition
time (STT) machines
by
using array algebra,
and the
one-hot code method
19.
High speed externally asynchronous/internally clocked systems, including
an
intro-
duction
to
dynamic domino
logic
applications
20.
Programmable asynchronous sequencers

READERSHIP
AND
COURSE PREREQUISITES
No
prior background
in
digital design
is
required
to
enter
a first
course
of
study
by
using
this
text.
It is
written
to
accommodate both
the first- and
second-level user. What
is
required
is
that
the

reader
have
sufficient
maturity
to
grasp
some
of the
more abstract
concepts
that
are
unavoidable
in any
digital design course
of
study.
It has
been
the
author's experience
that
digital design makes
an
excellent introduction
to
electrical
and
computer engineering
because

of the
absolute
and
precise
nature
of the
subjects
—
there
are no
approximation
signs. This text
is
designed
to
make
first
reading
by a
user
a
rewarding experience. However,
there
is
sufficient
advanced material
to
satisfy
the
needs

of the
second level students
and
professionals
in the field. A first-level
understanding
of the
subject matter
is
necessary
before
entering
a
second-level course using this text.
PREFACE
xxi
SUGGESTED TEXT USAGE
Perhaps
the
best advice that
can be
given
to
instructors
on the use of
this text
is to
study
the
table

of
contents
carefully
and
then decide what
subject
matter
is
essential
to the
course
under consideration. Once this
is
done
the
subject
area
and
order
of
presentation will usually
become obvious.
The
following
two
course outlines
are
offered
here
as a

starting point
for
instructors
in
making
decisions
on
course subject usage:
The
Semester System
[1]
First-Level
Course—Combinational
Logic Design
Block
I
Introduction (Chapter
1)
Number
systems, binary arithmetic
and
codes (Sections
2.1
through
2.5 or
choice)
Binary
state terminology, CMOS logic circuits,
and
mixed-logic symbology

(Sections
3.1
through 3.7)
Reading
and
construction
of
logic circuits (Section 3.8)
XOR
and EQV
operators
and
mixed-logic symbology (Section 3.9)
Laws
of
Boolean
and XOR
algebra (Sections
3.10
through
3.12)
Review
EXAM
#1
Block
II
Introduction; logic
function
representation (Sections
4.1

and
4.2)
Karnaugh
map
(K-map)
function
representation
and
minimization, don't cares,
and
multioutput optimization (Sections
4.3
through 4.5)
Entered variable mapping methods
and
function reduction
of five or
more
variables
(Sections
4.6,
4.7 and
4.12)
Introduction
to
minimization algorithms (Section 4.8)
Factorization
and
resubstitution methods (Subsections
4.9.1

and
4.9.2)
Function
minimization
by
using
XOR
K-map patterns (Sections
5.1
through 5.4)
Review
EXAM
#2
Block
III
Introduction
to
combinational logic design (Section
6.1)
Multiplexers,
decoders, priority encoders,
and
code converters (Sections
6.2
through
6.5; Section 2.10)
Magnitude
comparators, parity generators
and
shifters

(Sections
6.6
through 6.8)
Programmable logic devices
—
ROMs, PLAs
and
PALs (Sections
7.1
through 7.6)
xxn
PREFACE
Adders,
subtracters,
multipliers,
and
dividers (Section
2.6 and
Subsections 2.9.1
through
2.9.5
or
choice; Sections
8.1
through
8.7 or
choice)
Arithmetic
and
logic

units
—
ALUs (Section 8.8)
— may be
omitted
if
time-limited
Static hazards
in
combinational logic devices (Sections
9.1 and
9.2)
Review
EXAM
#3
and/or
FINAL
[2]
Second-Level
Course—State
Machine Design
and
Analysis
Block
IV
Introduction; models,
the
state diagram,
and
heuristic development

of the
basic
memory cells (Sections 10.1 through 10.4)
Design
and
analysis
of flip-flops, flip-flop
conversion; timing problems; asyn-
chronous overrides; setup
and
hold time requirements (Sections 10.5 through
10.11)
Design
of
simple synchronous
finite
state machines; K-map conversion; analysis
of
synchronous FSMs (Sections 10.12
and
10.13)
Review
EXAM
#1
Block
V
Introduction;
detection
and
elimination

of
timing defects
in
synchronous state
machines (Sections
11.1
through
11.3)
Synchronizing
and
stretching
of
asynchronous
inputs;
metastability; clock skew
and
clock sources (Sections
11.4
through
11.6)
Initialization
and
reset
of
FSMs,
and
debouncing circuits (Sections
11.7
and
11.8)

Applications
to the
design
and
analysis
of
more complex synchronous
FSMs;
ASM
charts
and
state assignment rules; array algebraic approach
to FSM
design; state
minimization (Sections
11.9
through
11.12)
Review
EXAM
#2
Block
VI
Introduction; design
of
shift
registers
and
synchronous counters; synchronous
vs

asynchronous parallel loading (Sections
12.1
through 12.3)
Shift
register counters
and
ripple counters; special purpose counters (Sections
12.4
through
12.5)
Alternative architecture
— use of
MUXs, decoders, PLDs, counters
and
shift
reg-
isters;
the
one-hot
design
method
(Sections
13.1
through 13.5)
The
controller, data path,
functional
partition,
and
system-level design (Sections

13.6
and
13.7)
Introduction
to
asynchronous sequential
machines
—
fundamental
mode FSMs
(Sections 14.1 through 14.9)
PREFACE
xxiii
Pulse mode approach
to
asynchronous
FSM
design (Sections
15.1
through 15.6)
Selected topics
in
Chapter
16
Review
EXAM
#3
and/or
FINAL
The

choice
of
course content
is
subject
to so
many variables that
no one
course outline will
suffice
even within
a
single institution where several instructors
may
teach
a
given course.
It
is for
this reason that
the
text
is
divided
up
into
16
relatively small
chapters.
This

offers
the
instructor somewhat more
flexibility in the
choice
of
subject
matter.
For
example,
if it is
desirable
to
offer
a
single (combined) semester course
in
digital design,
it
might
be
desirable
to
offer
both combinational
and
sequential (synchronous FSM) logic design. Such
a
course
might include

the
following subject areas taken
from
Blocks
I
through
VI in
sample course
outlines
[1] and
[2]:
[3]
Single
(Combined)
Semester
Course
in
Digital
Design
Binary state terminology,
and
mixed-logic
symbology
(Sections
3.1
through 3.7)
Reading
and
construction
of

logic
circuits
(Section
3.8)
XOR
and EQV
operators
and
mixed-logic symbology (Section 3.9)
Laws
of
Boolean
and XOR
algebra (Sections 3.10 through 3.12)
Review
EXAM
#1
Logic
function
representation (Sections
4.1
and
4.2)
K-map
function
representation
and
minimization, don't cares
and
multioutput

optimization (Sections
4.3
through 4.5)
Entered variable mapping methods
and
function reduction
of five or
more variables
(Sections 4.6,
4.7 and
4.12)
Multiplexers, decoders, priority encoders,
and
code converters (Sections
6.2
through 6.5)
Comparators, parity generators,
and
shifters
or
choice (Sections
6.6
through 6.8)
Adders, subtractors,
and
multipliers
(Sections
8.1
through 8.3;
Section

8.6)
Static hazards
in
combinational logic devices (Sections
9.1
and
9.2)
Review
EXAM
#2
Heuristic development
of the
basic memory cells (Sections
10.1
through 10.4)
Design
and
analysis
of flip-flops, flip-flop
conversion (Sections 10.5 through 10.8)
Asynchronous overrides; setup
and
hold time requirements; design
and
analysis
of
simple synchronous state machines (Sections 10.10 through 10.13)
Detection
and
elimination

of
timing defects
in
synchronous state
machines
(Sections
11.1
through
11.3)
Synchronizing
of
asynchronous inputs (Section
11.4)
Initialization
and
reset
of
FSMs; debouncing circuits (Sections
11.7
and
11.8)
Shift
registers
and
counters (Sections 12.1 through 12.3)
xxiv
PREFACE
Alternative
architecture
—

use of
MUXs, decoders, PLDs;
the
one-hot method
(Sections 13.1 through 13.3, Section 13.5)
The
controller, data path,
and
functional
partition
and
system-level design
(Sections 13.6
and
13.7)
Review
EXAM
#3
and/or
FINAL
Though
the
subject coverage
for
EXAM
#3 in
course sample outline
[3]
seems large
in

proportion
to
those required
for
EXAM
#2, a
close inspection will indicate that
the
number
of
sections
are the
same.
The
sections required
for
EXAM
#1
number about half that
of the
other two.
The
Quarter System
Not
all
courses
at
colleges
and
universities

are
operated
on a
semester basis. Some
are
operated
on the
quarter system.
This
requires that
the
course subject areas
be
divided
up
in
some
logical
and
effective
manner, which
may
require that both combinational
and
sequential
machines
be
covered within
a
given quarter

course.
As a
guide
to
subject
area
planning
on the
quarter system when using this text,
the
following quarter system
may be
considered
(refer
to
sample course outlines
[1] and
[2]):
First
Quarter
Block
I
EXAM#1
Block
II
EXAM
#2
Second
Quarter
Block

III
EXAM
#1
Block
IV
EXAM
#2
Third
Quarter
Block
V
EXAM
#1
Block
VI
EXAM
#2
Fourth
Quarter
(if
applicable)
Chapters
14 and
15
EXAM
#1
Chapter
16
PROJECT
and/or

EXAM
#2