A computer system consists of hardware, system programs, and application programs figs 4

4
MEMORY MANAGEMENT
4.1 BASIC MEMORY MANAGEMENT
4.2 SWAPPING
4.3 VIRTUAL MEMORY
4.4 PAGE REPLACEMENT ALGORITHMS
4.5 MODELING PAGE REPLACEMENT ALGORITHMS
4.6 DESIGN ISSUES FOR PAGING SYSTEMS
4.7 IMPLEMENTATION ISSUES
4.8 SEGMENTATION
4.9 RESEARCH ON MEMORY MANAGEMENT
4.10 SUMMARY
(a) (b) (c)
0xFFF …
000
User
program
User
program
User
program
Operating
system in
RAM
Operating
system in
RAM
Operating
system in
ROM
Device

drivers in ROM
Fig. 4-1. Three simple ways of organizing memory with an operat-
ing system and one user process. Other possibilities also exist.
(a)
Multiple
input queues
Partition 4
Partition 3
Partition 2
Partition 1
Operating
system
Partition 4
Partition 3
Partition 2
Partition 1
Operating
system
700K
400K
100K
0
(b)
Single
input queue
200K
800K
Fig. 4-2. (a) Fixed memory partitions with separate input queues
for each partition. (b) Fixed memory partitions with a single input
queue.

50% I/O wait
80% I/O wait
20% I/O wait
100
80
60
40
20
123456789100
Degree of multiprogramming
CPU utilization (in percent)
Fig. 4-3. CPU utilization as a function of the number of processes
in memory.
Job
Arrival
time
CPU
minutes
needed
1
2
3
4
10:00
10:10
10:15
10:20
4
3
2

2
CPU idle
CPU busy
CPU/process
.80
.20
.20
.64
.36
.18
.51
.49
.16
.41
.59
.15
1
2
3
4
0
100 15 20 22 27.6 28.2 31.7
2.0 .9
.9
.8
.8
.8
.3
.3
.3

.3
.9
.9
.9
.1
.1 .7
Job 2 starts
1234
# Processes
(a)
(c)
(b)
Time (relative to job 1's arrival)
Job 1 finishes
Fig. 4-4. (a) Arrival and work requirements of four jobs. (b) CPU
utilization for 1 to 4 jobs with 80 percent I/O wait. (c) Sequence
of events as jobs arrive and finish. The numbers above the hor-
izontal lines show how much CPU time, in minutes, each job gets
in each interval.
(a)
Operating
system
A
(b)
Operating
system
A
B
(c)
Operating

system
A
B
C
(d)
Time
Operating
system
B
C
(e)
D
Operating
system
B
C
(f)
D
Operating
system
C
(g)
D
Operating
system
A
C
Fig. 4-5. Memory allocation changes as processes come into
memory and leave it. The shaded regions are unused memory.
(a) (b)

Operating
system
Room for growth
Room for growth
B-Stack
A-Stack
B-Data
A-Data
B-Program
A-Program
Operating
system
Room for growth
B
A
Actually in use
Room for growth
Actually in use
Fig. 4-6. (a) Allocating space for a growing data segment.
(b) Allocating space for a growing stack and a growing data seg-
ment.
(a)
(b) (c)
ABCDE
81624
Hole Starts
at 18
Length
2
Process

P05 H53 P86 P144
H182 P206 P263 H293 X
1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 0 0 0
Fig. 4-7. (a) A part of memory with five processes and three holes.
The tick marks show the memory allocation units. The shaded
regions (0 in the bitmap) are free. (b) The corresponding bitmap.
(c) The same information as a list.
becomes
becomes
becomes
becomes
(a) A X B
(b) A X
(c) X B
(d) X
Before X terminates
AB
A
B
After X terminates
Fig. 4-8. Four neighbor combinations for the terminating process,
X.
CPU
package
CPU
The CPU sends virtual
addresses to the MMU

The MMU sends physical
addresses to the memory
Memory
management
unit
Memory
Disk
controller
Bus
Fig. 4-9. The position and function of the MMU. Here the MMU
is shown as being a part of the CPU chip because it commonly is
nowadays. However, logically it could be a separate chip and was
in years gone by.
Virtual
address
space
Physical
memory
address
60K-64K
56K-60K
52K-56K
48K-52K
44K-48K
40K-44K
36K-40K
32K-36K
28K-32K
24K-28K
20K-24K

16K-20K
12K-16K
8K-12K
4K-8K
0K-4K
28K-32K
24K-28K
20K-24K
16K-20K
12K-16K
8K-12K
4K-8K
0K-4K
Virtual page
Page frame
X
X
X
X
7
X
5
X
X
X
3
4
0
6
1

2
Fig. 4-10. The relation between virtual addresses and physical
memory addresses is given by the page table.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
000
000
000
000
111
000
101
000
000
000
011

100
000
110
001
010
0
0
0
0
1
0
1
0
0
0
1
1
1
1
1
1
Present/
absent bit
Page
table
12-bit offset
copied directly
from input
to output
Virtual page = 2 is used

as an index into the
page table
Incoming
virtual
address
(8196)
Outgoing
physical
address
(24580)
110
1 1 0 0 0 0 0 0 0 0 0 0 1 0 0
00 1 0 0 0 0 0 0 0 0 0 0 1 0 0
Fig. 4-11. The internal operation of the MMU with 16 4-KB
pages.
(a)
(b)
Top-level
page table
Second-level
page tables
To
pages
Page
table for
the top
4M of
memory
6
5

4
3
2
1
0
1023
6
5
4
3
2
1
0
1023
Bits 10 10 12
PT1 PT2 Offset
Fig. 4-12. (a) A 32-bit address with two page table fields.
(b) Two-level page tables.
Caching
disabled Modified Present/absent
Page frame number
Referenced Protection
Fig. 4-13. A typical page table entry.
Valid Virtual page Modified Protection Page frame
1 140 1 RW 31
120 0RX 38
1 130 1 RW 29
1 129 1 RW 62
119 0RX 50
121 0RX 45

1 860 1 RW 14
1 861 1 RW 75
Fig. 4-14. A TLB to speed up paging.
Traditional page
table with an entry
for each of the 2
52
pages
256-MB physical
memory has 2
16
4-KB page frames
Hash table
2
16
-1
2
52
-1
2
16
-1
00
Indexed
by virtual
page
0
Indexed
by hash on
virtual page

Virtual
page
Page
frame
Fig. 4-15. Comparison of a traditional page table with an inverted
page table.
(a)
Page loaded first
Most recently
loaded page
0
A
3
B
7
C
8
D
12
E
14
F
15
G
18
H
(b)
A is treated like a
newly loaded page
3

B
7
C
8
D
12
E
14
F
15
G
18
H
20
A
Fig. 4-16. Operation of second chance. (a) Pages sorted in FIFO
order. (b) Page list if a page fault occurs at time 20 and A has its R
bit set. The numbers above the pages are their loading times.
When a page fault occurs,
the page the hand is
pointing to is inspected.
The action taken depends
on the R bit:
R = 0: Evict the page
R = 1: Clear R and advance hand
A
B
C
D
E

F
G
H
I
J
K
L
Fig. 4-17. The clock page replacement algorithm.
(a)
0
0
0
0
0
1
1
0
0
0
2
1
0
0
0
3
1
0
0
0
0

1
2
3
Page
(b)
0
0
1
0
0
1
0
0
0
0
2
1
1
0
0
3
1
1
0
0
Page
(c)
0
0
1

1
0
1
0
0
1
0
2
0
0
0
0
3
1
1
1
0
Page
(d)
0
0
1
1
1
1
0
0
1
1
2

0
0
0
1
3
0
0
0
0
Page
(e)
0
0
1
1
1
1
0
0
1
1
2
0
0
0
0
3
0
0
1

0
(f)
0
1
1
1
0
0
0
0
0
1
0
0
0
1
1
0
(g)
0
0
0
0
1
0
0
0
1
1
0

0
1
1
1
0
(h)
0
0
0
1
1
0
0
1
1
1
0
1
0
0
0
0
(i)
0
0
1
1
1
0
1

1
0
0
0
0
0
0
1
0
(j)
0
0
1
1
1
0
1
1
0
0
0
1
0
0
0
0
Page
Fig. 4-18. LRU using a matrix when pages are referenced in the
order 0, 1, 2, 3, 2, 1, 0, 3, 2, 3.
Page

0
1
2
3
4
5
R bits for
pages 0-5,
clock tick 0
10000000
00000000
10000000
00000000
10000000
10000000
1
0 1 0 1 1
(a)
R bits for
pages 0-5,
clock tick 1
11000000
10000000
01000000
00000000
11000000
01000000
1
1 0 0 1 0
(b)

R bits for
pages 0-5,
clock tick 2
11100000
11000000
00100000
10000000
01100000
10100000
1
1 0 1 0 1
(c)
R bits for
pages 0-5,
clock tick 3
11110000
01100000
00100000
01000000
10110000
01010000
1
0 0 0 1 0
(d)
R bits for
pages 0-5,
clock tick 4
01111000
10110000
10001000

00100000
01011000
00101000
0
1 1 0 0 0
(e)
Fig. 4-19. The aging algorithm simulates LRU in software.
Shown are six pages for five clock ticks. The five clock ticks are
represented by (a) to (e).
w(k,t)
k
Fig. 4-20. The working set is the set of pages used by the k most
recent memory references. The function w(k, t) is the size of the
working set at time t.
Information about
one page
2084
2204 Current virtual time
2003
1980
1213
2014
2020
2032
1620
Page table
1
1
1
0

1
1
1
0
Time of last use
Page referenced
during this tick
Page not referenced
during this tick
R (Referenced) bit
Scan all pages examining R bit:
if (R == 1)
set time of last use to current virtual time
if (R == 0 and age > τ)
remove this page
if (R == 0 and age ≤ τ)
remember the smallest time
Fig. 4-21. The working set algorithm.
2204 Current virtual time
1213 0
2084 1
2032 1
1620 0
2020 1
2003 1
1980 1
2014 1
Time of
last use
R bit

(a) (b)
(c) (d)
New page
1213 0
2084 1
2032 1
1620 0
2020 1
2003 1
1980 1
2014 0
1213 0
2084 1
2032 1
1620 0
2020 1
2003 1
1980 1
2014 0
2204 1
2084 1
2032 1
1620 0
2020 1
2003 1
1980 1
2014 0
Fig. 4-22. Operation of the WSClock algorithm. (a) and (b) give
an example of what happens when R = 1. (c) and (d) give an
example of R =0.

Algorithm Comment
Optimal Not implementable, but useful as a benchmark
NRU (Not Recently Used) Very crude
FIFO (First-In, First-Out) Might throw out important pages
Second chance Big improvement over FIFO
Clock Realistic
LRU (Least Recently Used) Excellent, but difficult to implement exactly
NFU (Not Frequently Used) Fairly crude approximation to LRU
Aging Efficient algorithm that approximates LRU well
Working set Somewhat expensive to implement
WSClock Good efficient algorithm
Fig. 4-23. Page replacement algorithms discussed in the text.
0 1 2 3 0 1 4 4 4 2 3 3
012301401234
PPP
PPPP PPPPPP
P P P P P P 9 Page faults
0 1 2 3 0 1 1 1 4 2 2
0 1 2 3 0 0 0 1 4 4
(a)
Youngest page
Oldest page
All pages frames initially empty
0 1 2 3 3 3 4 0 1 2 3 4
012301401234
0 1 2 2 2 3 4 0 1 2 3
0 1 1 1 2 3 4 0 1 2
10 Page faults
0 0 0 1 2 3 4 0 1
(b)

Youngest page
Oldest page
Fig. 4-24. Belady’s anomaly. (a) FIFO with three page frames.
(b) FIFO with four page frames. The P’s show which page refer-
ences cause page faults.