ECAD and VLSI lab manual

ECAD & VLSI LAB
MANUAL FOR
B.TECH –ECE IV-1 SEMESTER
BY
SATHISH DADI M.TECH

DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING


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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV Year B.Tech. ECE - I Sem L T/P/D C 0 -/3/- 2
E-CAD AND VLSI LAB

List of Experiments

Design and implementation of the following CMOS digital/analog circuits using Cadence /
Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level
design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis,
Simulation and verification, Scaling of CMOS Inverter for different technologies, study of
secondary effects ( temperature, power supply and process corners), Circuit optimization with
respect to area, performance and/or power, Layout, Extraction of parasitics and back
annotation, modifications in circuit parameters and layout consumption, DC/transient analysis,

Verification of layouts (DRC, LVS)
E-CAD programs:
Programming can be done using any complier. Down load the programs on FPGA/CPLD boards
and performance testing may be done using pattern generator (32 channels) and logic analyzer
apart from verification by simulation with any of the front end tools.

1. HDL code to realize all the logic gates
2. Design of 2-to-4 decoder
3. Design of 8-to-3 encoder (without and with parity)
4. Design of 8-to-1 multiplexer
5. Design of 4 bit binary to gray converter
6. Design of Multiplexer/ Demultiplexer, comparator
7. Design of Full adder using 3 modeling styles
8. Design of flip flops: SR, D, JK, T
9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or
any sequence counter
10. Finite State Machine Design

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VLSI programs:
1. Introduction to layout design rules
2. Layout, physical verification, placement & route for complex design, static
timing analysis, IR drop analysis and crosstalk analysis of the following:
 Basic logic gates
CMOS inverter
CMOS NOR/ NAND gates

CMOS XOR and MUX gates
CMOS 1-bit full adder
Static / Dynamic logic circuit (register cell)
Latch
Pass transistor
3. Layout of any combinational circuit (complex CMOS logic gate)- Learning
about data paths
4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit
5. SPICE simulation of basic analog circuits: Inverter / Differential amplifier
6. Analog Circuit simulation (AC analysis) – CS & CD amplifier
7. System level design using PLL

Note: Any SIX of the above experiments from each part are to be conducted (Total 12)





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EXPERIMENT -1
Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL

Aim:
1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural
modeling style in Verilog using a Test bench.
2. Synthesize each one of them on two different EDA tools.
Apparatus required:

Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii) Model Sim simulation tool or Xilinx ISE Simulator tool
iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool
iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
fromSimulation to Implementation to download onto FPGA).
v) JTAG cable
vi) Adator 5v/4A

Boolean equations:
And Gate:Y = (A.B)
Or Gate: Y = (A + B)
Nand Gate: Y = (A.B)’
Nor Gate: Y = (A+B)’
Xor Gate: Y = A.B’ + A’.B
Xnor Gate: Y = A.B + A’.B’


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Block diagram:

Verilog program for AND gate:
// And Gate (In Dataflow, behavioral Modeling):
Module andg(a,b,c);
input a,b;
output c;
assign c = a & b;
endmodule

//behavioural modeling

Module andg1(a,b,c);
input a,b;
always(a,b)
begin
if (a==1’b0 or b == 1’b0)
c = 1’b0;
else if (a==1’b0 or b == 1’b1)
c = 1’b0;
else if (a==1’b1 or b == 1’b0)
c = 1’b0;
else if (a==1’b1 or b == 1’b1)
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c = 1’b1;
endendmodule

Verilog program for OR gate:

//Or gate(Dataflow, behavioral modeling):
Module org (a,b,c);
input a,b;
output c;
assign c = a | b;
endmodule

Verilog program for nand gate:

// Nand Gate (In Dataflow modeling):
Module nandg (a,b,c);
input a,b;
output c;
assign c = ~(a & b);
endmodule

Verilog program for NOR gate:
// Nor Gate (In Dataflow modeling):
Module norg (a,b,c);
input a,b;
output c;
assign c = ~(a | b);
endmodule




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Verilog program for XOR gate:
Xor gate(In Dataflow modeling):
Module xorg (a,b,c);
input a,b;
output c;
assign c = a ^ b;
endmodule
(or)
Module xorg2 (a,b,c);

input a,b;
output c;
assign c = (~a & b) | (a & ~b);
endmodule

Verilog program for XNOR gate:
//Xnor Gate (In Dataflow modeling):
Module xnorg (a,b,c);
input a,b;
output c;
assign c = ~(a ^ b);
endmodule







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VHDL PROGRAM FOR ALL LOGIC GATES:
library ieee;
use ieee.std_logic_1164.all;
entity digital_gates is port( x: in std_logic;
y: in std_logic;
sel:in std_logic_vector(1 downto 0);
F: out std_logic);
end digital_gates;

architecture behav1 of digital_gates is
begin
process(x, y, sel)
begin
if (sel = "00") then
F <= x and y;
elsif (sel = "01") then
F <= x or y;
elsif (sel = "10") then
F <= x nand y;
elsif (sel = "11") then
F <= x nor y;
else
F <= '0';
end if;
end process;
end behav1;


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Test Bench: programmable digital gates
library ieee;
use ieee.std_logic_1164.all;
entity tb_digital_gates is
end tb_digital_gates;
architecture behav1 of tb_digital_gates is
component digital_gates is
port( x: in std_logic;

y: in std_logic;
sel:in std_logic_vector(1 downto 0);
F: out std_logic
);
end component;
signal x,y,F:std_logic;
signal sel:std_logic_vector(1 downto 0);
begin
U1: digital_gates port map(x,y, sel,F);
process
begin
x <= '0';
wait for 10 ns;
x <= '1';
wait for 20 ns;
end process;
process
begin
y <= '0';
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wait for 20 ns;
y <= '1';
wait for 30 ns;
end process;
process
begin
sel <= "00","01" after 20 ns,"10" after 40 ns,"11" after 80 ns;
wait for 120 ns;

end process;
end behav1;














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EXPERIMENT -2
Design of decoder usingVerilog HDL

Aim:
1. Perform Zero Delay Simulation of decodere in Verilog using a Test bench.
2. Synthesize each one of them on two different EDA tools.
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii) Model Sim simulation tool or Xilinx ISE Simulator tool
iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool

iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
fromSimulation to Implementation to download onto FPGA).
v) JTAG cable
vi) Adator 5v/4A
Block diagram:

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Verilog program:
module decoder(a, y);
input [1:0] a;
output [3:0] y;
reg [3:0] y;
always @ (a)
case(a)
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2’b00: y<= 4’b1110;
2’b01: y<= 4’b1101;
2’b10: y<= 4’b1011;
2’b11: y<= 4’b0111;
end case;
endmodule
********************************************
//decoder using case statement
module dec2to4(W, Y, En);

input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(*)
case ({en,W})
3’b100: Y = 4’b1000;
3’b101: Y = 4’b0100;
3’b110: Y = 4’b0010;
3’b111: Y = 4’b0001;
default: Y = 4’b0000;
endcase
endmodule
****************************************************
module decoder_2to4(Y3, Y2, Y1, Y0, A, B, en);
output Y3, Y2, Y1, Y0;
input A, B;
input en;
reg Y3, Y2, Y1, Y0;
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always @(A or B or en)
begin
if (en == 1'b1)
case ( {A,B} )
2'b00: {Y3,Y2,Y1,Y0} = 4'b1110;
2'b01: {Y3,Y2,Y1,Y0} = 4'b1101;
2'b10: {Y3,Y2,Y1,Y0} = 4'b1011;
2'b11: {Y3,Y2,Y1,Y0} = 4'b0111;

default: {Y3,Y2,Y1,Y0} = 4'bxxxx;
endcase
if (en == 0)
{Y3,Y2,Y1,Y0} = 4'b1111;
end
endmodule
//***************test bench********************
module Test_decoder_2to4;
wire Y3, Y2, Y1, Y0;
reg A, B;
reg en;
// Instantiate the Decoder (named DUT {device under test})
decoder_2to4 DUT(Y3, Y2, Y1, Y0, A, B, en);
initial begin
$timeformat(-9, 1, " ns", 6); #1;
A = 1'b0; // time = 0
B = 1'b0;
en = 1'b0;
#9;
en = 1'b1; // time = 10
#10;
A = 1'b0;
B = 1'b1; // time = 20
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#10;
A = 1'b1;
B = 1'b0; // time = 30
#10;

A = 1'b1;
B = 1'b1; // time = 40
#5;
en = 1'b0; // time = 45
#5;
end
always @(A or B or en)
#1 $display("t=%t",$time," en=%b",en," A=%b",A," B=%b",B,"
Y=%b%b%b%b",Y3,Y2,Y1,Y0);
endmodule
******************************************
module decode24(q, a);
output[3:0] q;
input[1:0] a;
assign q = (4’b0001) << a;
endmodule
**********************************
module dec2to4(W, Y, En);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(*)
case ({en,W})
3’b100: Y = 4’b1000;
3’b101: Y = 4’b0100;
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3’b110: Y = 4’b0010;

3’b111: Y = 4’b0001;
default: Y = 4’b0000;
endcase
endmodule
3 TO 8 DECODER
module decoder(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C);
output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;
input A,B,C;
wire s0,s1,s2;

not (s0,A);
not (s1,B);
not (s2,C);
and (Q0,s0,s1,s2);
and (Q1,A,s1,s2);
and (Q2,s0,B,s2);
and (Q3,A,B,s2);
and (Q4,s0,s1,C);
and (Q5,A,s1,C);
and (Q6,s0,B,C);
and (Q7,A,B,C);
endmodule
//*****TESTBENCH*******//
module stimulus;
// Set up variables
reg A, B, C;
// Instantiate the decoder.
decoder FF(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C);
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// Setup the monitoring for the signal values
initial
begin
$monitor($time,"C=%b, =%b,A=%b ,Q=%b%b%b%b%b%b%b%b\n",
C,B,A,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7);
end
// Stimulate inputs
Initial begin
C=1'b0; B =1'b0; A = 1'b0;
#10 C =1'b0; B = 1'b0; A= 1'b1;
#10 C =1'b0; B = 1'b1; A= 1'b0;
#10 C =1'b0; B = 1'b1; A= 1'b1;
#10 C =1'b1; B = 1'b0; A= 1'b0;
#10 C =1'b1; B = 1'b0; A= 1'b1;
#10 C =1'b1; B = 1'b1; A= 1'b0;
#10 C =1'b1; B = 1'b1; A= 1'b1;
end
endmodule
**********************************************************
module decoder_3to8(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, A, B, C, en);
output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
input A, B, C;
input en;

assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111_1110 :
( {en,A,B,C} == 4'b1001) ? 8'b1111_1101 :
( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 :
( {en,A,B,C} == 4'b1011) ? 8'b1111_0111 :
( {en,A,B,C} == 4'b1100) ? 8'b1110_1111 :

( {en,A,B,C} == 4'b1101) ? 8'b1101_1111 :
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( {en,A,B,C} == 4'b1110) ? 8'b1011_1111 :
( {en,A,B,C} == 4'b1111) ? 8'b0111_1111 :
8'b1111_1111;
Endmodule
//TESTBENCH
module Test_decoder_3to8;
wire Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
reg A, B, C;
reg en;
// Instantiate the Decoder (named DUT {device under test})
decoder_3to8 DUT(Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0, A, B, C, en);
initial begin
$timeformat(-9, 1, " ns", 6); #1;
A = 1'b0; // time = 0
B = 1'b0;
C = 1'b0;
en = 1'b0;
#9;
en = 1'b1; // time = 10
#10;
A = 1'b0;
B = 1'b1;
C = 1'b0; // time = 20
#10;
A = 1'b1;
B = 1'b0;

C = 1'b0; // time = 30
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#10;
A = 1'b1;
B = 1'b1;
C = 1'b0; // time = 40
#5;
en = 1'b0; // time = 45
#5;
end
always @(A or B or C or en)
$display("t=%t en=%b ABC=%b%b%b Y=%b%b%b%b%b%b%b%b",
$time,en,A,B,C,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0);
Endmodule
********************************************************
module decoder (in,out);
input [2:0] in;
output [7:0] out;
wire [7:0] out;

assign out = (in == 3'b000 ) ? 8'b0000_0001 :
(in == 3'b001 ) ? 8'b0000_0010 :
(in == 3'b010 ) ? 8'b0000_0100 :
(in == 3'b011 ) ? 8'b0000_1000 :
(in == 3'b100 ) ? 8'b0001_0000 :
(in == 3'b101 ) ? 8'b0010_0000 :
(in == 3'b110 ) ? 8'b0100_0000 :
(in == 3'b111 ) ? 8'b1000_0000 : 8'h00;

endmodule

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********************************************************
module decoder_always (in,out);
input [2:0] in;
output [7:0] out;
reg [7:0] out;
always @ (in)
begin
out = 0;
case (in)
3'b001 : out = 8'b0000_0001;
3'b010 : out = 8'b0000_0010;
3'b011 : out = 8'b0000_0100;
3'b100 : out = 8'b0000_1000;
3'b101 : out = 8'b0001_0000;
3'b110 : out = 8'b0100_0000;
3'b111 : out = 8'b1000_0000;
endcase
end
endmodule
//USING FOR LOOP
module Decode3To8For(yOut, aIn, enable);
output [7:0]yOut;
input [2:0]aIn;
input enable;
reg [7:0] yOut;

integer k;
always@(aIn or enable)
begin
if(enable == 1)
begin
for(k=0;k<8;k=k+1)
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begin
if(aIn == k)
yOut[k] = 0;
else
yOut[k] = 1;
end
end
end
endmodule
BCD decoder

This circuit has four binary inputs and ten binary outputs. The ith output is asserted if the
binary inputs are the binary number i, where 0 ≤ i ≤ 9. The inputs will never be a number greater
than 9 (or if they are, we don’t care what the output is).

module (X, Y);
input [3:0] X;
output [0:9] Y;
reg [0:9] Y;
always @(*) begin
Y = 0;

case (X)
0: Y[0] = 1;
1: Y[1] = 1;
2: Y[2] = 1;
3: Y[3] = 1;
4: Y[4] = 1;
5: Y[5] = 1;
6: Y[6] = 1;
7: Y[7] = 1;
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8: Y[8] = 1;
9: Y[9] = 1;
default: Y = ’bx;
endcase
end
endmodule

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EXPERIMENT -3
Design of 8-to-3 encoder (without and with parity) usingVerilog HDL

Aim:
1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and
structural modeling style in Verilog using a Test bench.
2. Synthesize each one of them on two different EDA tools.
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST
iii) Synthesis tool or LeonardoSpectrum Synthesis Tool
iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
fromSimulation to Implementation to download onto FPGA).
v) JTAG cable
vi) Adator 5v/4A
THEORY:
An encoder is a digital circuit which performs the inverse of decoder.An encoder has 2^N input
lines and N output lines.In encoder the output lines genrate the binary code corresponding to
input value.The decimal to bcd encoder usually has 10 input lines and 4 ouput lines.The
decoder decimal data as an input for decoder an encoded bcd ouput is available at 4 output
lines.

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Y2 = w7 + w6 + w5 + w4
Y1 = w7 + w6 + w3 + w2
Y0 = w7 + w5 + w3 + w1

Verilog program for 8x3 encoder:
module encoder (din, dout);
input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
always @(din)
begin
if (din ==8'b00000001) dout=3'b000;
else if (din==8'b00000010) dout=3'b001;
else if (din==8'b00000100) dout=3'b010;
else if (din==8'b00001000) dout=3'b011;
else if (din==8'b00010000) dout=3'b100;
else if (din ==8'b00100000) dout=3'b101;
else if (din==8'b01000000) dout=3'b110;
else if (din==8'b10000000) dout=3'b111;
else dout=3'bX;
end
endmodule

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Priority Encoders
 A priority encoder has n inputs and ⎡log2n⎤ outputs.
The output signals are a binary number such that its valueis the highest index value of all the
inputs that are 1.
� Example: 4-to-2 priority encoder:
y1 = w3’•w2 + w3
y2 = w3’•w2’•w1 + w3
z = w0 + w1 + w2 + w3
Priority encoder is a special type of encoder in which multiple bits at the input can be asserted.
The response at the output is however defined by the priority rule, defined previously. Priority
encoders have vast application in different client-server systems. In client-server systems
decision is made to grant a service based on the priority of any specific client.
Here is a verilog code for an 8:3 priority encoder. It grants the highest priority to the "most left
sided bit in the input word". For example in data word "00010101" the highest priority is carried
by the most left sided one, appearing at the fourth (counting from left side). So all the other bits
that come next to it will be discarded or in other words will not be taken into account. Verilog
implementation has been done using "casex" statement.
an 8-bit priority encoder. This circuit basically converts a one-hot encoding into a binary
representation. If input n is active, all lower inputs (n-1 0) are ignored. Please read the
description of the 4:2 encoder for an explanation.
x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0

1 X X X X X X X 1 1 1
0 1 X X X X X X 1 1 0
0 0 1 X X X X X 1 0 1
0 0 0 1 X X X X 1 0 0
0 0 0 0 1 X X X 0 1 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 0 0 X 0 0 0

module priority_encoder (code, valid_data, data);
output [2:0] code;
output valid data;
input [7:0] data;
reg [2:0] code;

assign valid_data= |data; // Use of "reduction or" operator
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