advanced techniques in logic synthesis, optimizations and applications

Advanced Techniques in Logic Synthesis,
Optimizations and Applications
Sunil P. Khatri · Kanupriya Gulati
Editors
Advanced Techniques
in Logic Synthesis,
Optimizations
and Applications
123
Editors
Sunil P. Khatri
Department of ECE
333F WERC, MS 3259
Texas A&M University
College Station, TX 77843-3259,
USA

Kanupriya Gulati
Intel Corporation
2501 NW 229th Ave
Hillsboro, OR 97124,
USA

ISBN 978-1-4419-7517-1 e-ISBN 978-1-4419-7518-8
DOI 10.1007/978-1-4419-7518-8
Springer New York Dordrecht Heidelberg London
c

Springer Science+Business Media, LLC 2011
All rights reserved. This work may not be translated or copied in whole or in part without the written
permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York,

NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in
connection with any form of information storage and retrieval, electronic adaptation, computer
software, or by similar or dissimilar methodology now known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks, and similar terms, even if
they are not identified as such, is not to be taken as an expression of opinion as to whether or not
they are subject to proprietary rights.
Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)
Preface
The last few decades have seen a stupendous growth in the speed and complex-
ity of VLSI integrated circuits. This growth has been enabled by a powerful set
of electronic design automation (EDA) tools. The earliest EDA tools were two-
level logic minimization and PLA folding tools. Subsequently, EDA tools were
developed to address other aspects of t he VLSI design flow (in addition to logic
optimization) such as technology mapping, layout optimization, formal verification.
However, research in logic synthesis and optimization continued to progress rapidly.
Some of the research in logic synthesis tools saw broader application, to areas far
removed from traditional EDA, and routinely continue to do so. While observing
the recent developments and publications in logic synthesis and optimization, we
felt that there was a need for a single resource which presents some recent signifi-
cant developments in this area. This is how the idea of this edited monograph came
about. We decided to cover some key papers in logic synthesis, optimization, and
its applications, in an effort to provide an advanced practitioner a single reference
source that covers the important papers in these areas over the last few years.
This monograph is organized into five sections, dealing with logic decomposi-
tion, Boolean satisfiability, Boolean matching, logic optimization, and applications
of logic techniques to special design scenarios. Each of the chapters in any section
is an expanded, archival version of the original paper by the chapter authors, with
additional examples, results, and/or implementation details.
We dedicate this book to the area of logic synthesis and hope that it can stimulate

new and exciting ideas which expand the contribution of logic synthesis to areas far
beyond its traditional stronghold of VLSI integrated circuit design.
College Station, Texas Sunil P. Khatri
Hillsboro, Oregon Kanupriya Gulati
v
Contents
1 Introduction 1
Sunil P. Khatri and Kanupriya Gulati
1.1 Logic Decomposition 2
1.2 Boolean Satisfiability 3
1.3 Boolean Matching 4
1.4 Logic Optimization 4
1.5 Applications to Specialized Design Scenarios 5
References 6
Part I Logic Decomposition
2 Logic Synthesis by Signal-Driven Decomposition 9
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, and Tiziano Villa
2.1 Introduction 9
2.2 Decomposition Methods 11
2.3 P-Circuits 17
2.3.1 Synthesis Algorithms 19
2.4 Multivariable Decomposition 21
2.5 Experimental Results 24
2.6 Conclusion 28
References 28
3 Sequential Logic Synthesis Using Symbolic Bi-decomposition 31
Victor N. Kravets and Alan Mishchenko
3.1 Introduction and Motivation 31
3.2 Preliminary Constructs 33
3.2.1 “Less-Than-or-Equal” Relation 33

3.2.2 Parameterized Abstraction 34
3.3 Bi-decomposition of Incompletely Specified Functions 35
3.3.1 OR Decomposition 35
3.3.2 XOR Decomposition 36
vii
viii Contents
3.4 Parameterized Decomposition 37
3.4.1 OR Parameterization 37
3.4.2 XOR Parameterization 38
3.5 Implementation Details of Sequential Synthesis 39
3.5.1 Extraction of Incompletely Specified Logic 39
3.5.2 Exploring Decomposition Choices 40
3.5.3 Synthesis Algorithm 41
3.6 Experimental Evaluation 42
3.7 Conclusions and Future Work 44
References 45
4 Boolean Factoring and Decomposition of Logic Networks 47
Robert Brayton, Alan Mishchenko, and Satrajit Chatterjee
4.1 Introduction 47
4.2 Background 48
4.3 General Non-disjoint Decompositions 50
4.4 Rewriting K -LUT networks 53
4.4.1 Global View 53
4.4.2 Cut Computation 54
4.4.3 Cuts with a DSD Structure 56
4.4.4 Cut Weight 56
4.4.5 Decomposition and Network Update 57
4.4.6 Finding the Maximum Support-Reducing
Decomposition 58
4.4.7 Additional Details 60

4.4.7.1 Using Timing Information to Filter Candidate
Bound Sets 60
4.4.7.2 Restricting Bound Sets for Balanced
Decompositions 60
4.4.7.3 Opportunistic MUX-Decomposition 60
4.5 Comparison with Boolean Matching 61
4.6 Experimental Results 62
4.7 Conclusions and Future Work 64
References 65
5 Ashenhurst Decomposition Using SAT
and Interpolation 67
Hsuan-Po Lin, Jie-Hong Roland Jiang, and Ruei-Rung Lee
5.1 Introduction 67
5.2 Previous Work 69
5.3 Preliminaries 69
5.3.1 Functional Decomposition 70
5.3.2 Functional Dependency 71
5.3.3 Propositional Satisfiability and Interpolation 71
5.3.3.1 Refutation Proof and Craig Interpolation 71
Contents ix
5.3.3.2 Circuit-to-CNF Conversion 72
5.4 Main Algorithms 72
5.4.1 Single-Output Ashenhurst Decomposition 72
5.4.1.1 Decomposition with Known Variable Partition .72
5.4.1.2 Decomposition with Unknown Variable
Partition 75
5.4.2 Multiple-Output Ashenhurst Decomposition 79
5.4.3 Beyond Ashenhurst Decomposition 80
5.5 Experimental Results 80
5.6 Chapter Summary 84

References 84
6 Bi-decomposition Using SAT and Interpolation 87
Ruei-Rung Lee, Jie-Hong Roland Jiang, and Wei-Lun Hung
6.1 Introduction 87
6.2 Previous Work 88
6.3 Preliminaries 89
6.3.1 Bi-Decomposition 89
6.3.2 Propositional Satisfiability 90
6.3.2.1 Refutation Proof and Craig Interpolation 90
6.3.3 Circuit to CNF Conversion 91
6.4 Our Approach 91
6.4.1 OR Bi-decomposition 91
6.4.1.1 Decomposition of Completely Specified
Functions 91
6.4.1.2 Decomposition of Incompletely Specified
Functions 97
6.4.2 AND Bi-decomposition 97
6.4.3 XOR Bi-decomposition 98
6.4.3.1 Decomposition of Completely Specified
Functions 98
6.4.4 Implementation Issues 101
6.5 Experimental Results 101
6.6 Summary 103
References 104
Part II Boolean Satisfiability
7 Boundary Points and Resolution 109
Eugene Goldberg and Panagiotis Manolios
7.1 Introduction 109
7.2 Basic Definitions 111
7.3 Properties 112

x Contents
7.3.1 Basic Propositions 112
7.3.2 Elimination of Boundary Points by Adding Resolvents . . . 113
7.3.3 Boundary Points and Redundant Formulas 115
7.4 Resolution Proofs and Boundary Points 115
7.4.1 Resolution Proof as Boundary Point Elimination 116
7.4.2 SMR Metric and Proof Quality 116
7.5 Equivalence Checking Formulas 117
7.5.1 Building Equivalence Checking Formulas 118
7.5.2 Short Proofs for Equivalence Checking Formulas 119
7.6 Experimental Results 120
7.7 Some Background 122
7.8 Completeness of Resolution Restricted to Boundary Point
Elimination 123
7.8.1 Cut Boundary Points 123
7.8.2 The Completeness Result 124
7.8.3 Boundary Points as Complexity Measure 125
7.9 Conclusions and Directions for Future Research 126
References 126
8 SAT Sweeping with Local Observability Don’t-Cares 129
Qi Zhu, Nathan B. Kitchen, Andreas Kuehlmann, and Alberto
Sangiovanni-Vincentelli
8.1 Introduction 129
8.2 Previous Work 130
8.3 Preliminaries 131
8.3.1 A
ND-INVERTER Graphs 131
8.3.2 SAT Sweeping 132
8.4 SAT Sweeping with Observability Don’t Cares 134
8.4.1 Motivating Example 134

8.4.2 Observability Don’t Cares 134
8.4.3 Algorithm 137
8.4.4 Implementation 139
8.4.5 Applications 141
8.5 Results 142
8.6 Conclusions 146
References 147
9 A Fast Approximation Algorithm for MIN-ONE SAT and Its
Application on MAX-SAT Solving 149
Lei Fang and Michael S. Hsiao
9.1 Introduction 149
9.2 Preliminaries 151
9.3 Our Approach 153
9.3.1 RelaxSAT 153
9.3.2 Relaxation Heuristic 155
Contents xi
9.3.3 Discussion on Computation Complexity 156
9.4 Experimental Results 156
9.5 Application Discussion: A RelaxSAT-Based MAX-SAT Solver . . . 161
9.5.1 The New MAX-SAT Solver: RMAXSAT 163
9.5.2 Evaluation of MAX-SAT Solver 165
9.6 Conclusions and Future Works 168
References 169
10 Algorithms for Maximum Satisfiability Using Unsatisfiable Cores . . . 171
Joao Marques-Sila and Jordi Planes
10.1 Introduction 171
10.2 Background 172
10.2.1 The MaxSAT Problem 172
10.2.2 Solving MaxSAT with PBO 173
10.2.3 Relating MaxSAT with Unsatisfiable Cores 173

10.3 A New MaxSAT Algorithm 174
10.3.1 Overview 175
10.3.2 The Algorithm 175
10.3.3 A Complete Example 176
10.4 Experimental Results 178
10.5 Related Work 180
10.6 Conclusions 180
References 181
Part III Boolean Matching
11 Simulation and SAT-Based Boolean Matching for Large Boolean
Networks 185
Kuo-Hua Wang, Chung-Ming Chan, and Jung-Chang Liu
11.1 Introduction 185
11.2 Background 186
11.2.1 Boolean Matching 186
11.2.2 Boolean Satisfiability 187
11.2.3 And-Inverter Graph 187
11.3 Detection of Functional Property Using S&S Approach 188
11.4 Definitions and Notations 189
11.5 Simulation Approach for Distinguishing Inputs 190
11.5.1 Type-1 191
11.5.2 Type-2 192
11.5.3 Type-3 192
11.6 S&S-Based Boolean Matching Algorithm 194
11.6.1 Our Matching Algorithm 194
11.6.2 Recursive-Matching Algorithm 194
xii Contents
11.6.3 Implementation Issues 196
11.6.3.1 Control of Random Vector Generation 196
11.6.3.2 Reduction of Simulation Time 196

11.6.3.3 Analysis of Space Complexity and Runtime 196
11.7 Experimental Results 197
11.8 Chapter Summary 200
References 200
12 Logic Difference Optimization for Incremental Synthesis 203
Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, and Ruchir Puri
12.1 Introduction and Background 203
12.2 Previous Work 205
12.3 DeltaSyn 206
12.3.1 Phase I: Equivalence-Based Reduction 207
12.3.2 Phase II: Matching-Based Reduction 209
12.3.2.1 Subcircuit Enumeration 210
12.3.2.2 Subcircuit Matching 213
12.3.2.3 Subcircuit Covering 217
12.3.3 Phase III: Functional Hashing-Based Reduction 218
12.4 Empirical Validation 220
12.5 Chapter Summary 224
References 224
13 Large-Scale Boolean Matching 227
Hadi Katebi and Igor Markov
13.1 Introduction 227
13.2 Background and Previous Work 229
13.2.1 Definitions and Notation 230
13.2.2 And-Inverter Graphs (AIGs) 230
13.2.3 Boolean Satisfiability and Equivalence Checking 231
13.2.4 Previous Work 231
13.3 Signature-Based Matching Techniques 232
13.3.1 Computing I/O Support Variables 232
13.3.2 Initial refinement of I/O clusters 233
13.3.3 Refining Outputs by Minterm Count 234

13.3.4 Refining I/O by Unateness 234
13.3.5 Scalable I/O Refinement by Dependency Analysis 235
13.3.6 Scalable I/O Refinement by Random Simulation 235
13.3.6.1 Simulation Type 1 236
13.3.6.2 Simulation Type 2 236
13.3.6.3 Simulation Type 3 237
13.4 SAT-Based Search 237
13.4.1 SAT-Based Input Matching 238
Contents xiii
13.4.2 Pruning Invalid Input Matches by SAT
Counterexamples 239
13.4.3 SAT-Based Output Matching 240
13.4.4 Pruning Invalid Output Matches by SAT Counterexamples 241
13.4.5 Pruning Invalid I/O Matches Using Support Signatures . . . 241
13.4.6 Pruning Invalid Input Matches Using Symmetries 241
13.4.7 A Heuristic for Matching Candidates 242
13.5 Empirical Validation 242
13.6 Chapter Summary 246
References 246
Part IV Logic Optimization
14 Algebraic Techniques to Enhance Common Sub-expression
Extraction for Polynomial System Synthesis 251
Sivaram Gopalakrishnan and Priyank Kalla
14.1 Introduction 251
14.1.1 Motivation 252
14.1.2 Contributions 253
14.1.3 Paper Organization 253
14.2 Previous Work 254
14.2.1 Kernel/Co-kernel Extraction 254
14.3 Preliminary Concepts 255

14.3.1 Polynomial Functions and Their Canonical
Representations 255
14.3.2 Factorization 257
14.4 Optimization Methods 257
14.4.1 Common Coefficient Extraction 258
14.4.2 Common Cube Extraction 259
14.4.3 Algebraic Division 260
14.5 Integrated Approach 261
14.6 Experiments 264
14.7 Conclusions 265
References 265
15 Automated Logic Restructuring with aSPFDs 267
Yu-Shen Yang, Subarna Sinha, Andreas Veneris, Robert Brayton,
and Duncan Smith
15.1 Introduction 267
15.2 Background 269
15.2.1 Prior Work on Logic Restructuring 269
15.2.2 Sets of Pairs of Functions to Be Distinguished 269
15.3 Approximating SPFDs 270
15.3.1 Computing aSPFDs for Combinational Circuits 271
xiv Contents
15.3.2 Computing aSPFDs for Sequential Circuits 273
15.3.3 Optimizing aSPFDs with Don’t Cares 274
15.3.3.1 Conflicts in Multiple Expected Traces 275
15.4 Logic Transformations with aSPFDs 277
15.4.1 SAT-Based Searching Algorithm 278
15.4.2 Greedy Searching Algorithm 279
15.5 Experimental Results 280
15.5.1 Logic Restructuring of Combinational Designs 280
15.5.2 Logic Restructuring of Sequential Designs 283

15.6 Summary 285
References 285
16 Extracting Functions from Boolean Relations Using SAT
and Interpolation 287
Jie-Hong Roland Jiang, Hsuan-Po Lin, and Wei-Lun Hung
16.1 Introduction 287
16.2 Previous Work 290
16.3 Preliminaries 290
16.3.1 Boolean Relation 290
16.3.2 Satisfiability and Interpolation 291
16.4 Our Approach 292
16.4.1 Single-Output Relation 292
16.4.1.1 Total Relation 292
16.4.1.2 Partial Relation 293
16.4.2 Multiple Output Relation 294
16.4.2.1 Determinization via Expansion Reduction 294
16.4.2.2 Determinization via Substitution Reduction . . . 295
16.4.3 Deterministic Relation 296
16.4.4 Function Simplification 297
16.4.4.1 Support Minimization 297
16.4.4.2 Determinization Scheduling 298
16.5 Experimental Results 298
16.6 Chapter Summary 305
References 306
17 A Robust Window-Based Multi-node Minimization Technique
Using Boolean Relations 309
Jeff L. Cobb, Kanupriya Gulati, and Sunil P. Khatri
17.1 Introduction 309
17.2 Problem Definition 311
17.3 Previous Work 312

17.4 Preliminaries and Definitions 314
17.4.1 BREL Boolean Relation Minimizer 316
Contents xv
17.5 Approach 317
17.5.1 Algorithm Details 318
17.5.1.1 Selecting Node Pairs 318
17.5.1.2 Building the Subnetwork 320
17.5.1.3 Computing the Boolean Relation R
Y
321
17.5.1.4 Quantification Scheduling 322
17.5.1.5 Endgame 324
17.6 Experimental Results 324
17.6.1 Preprocessing Steps 325
17.6.2 Parameter Selection 325
17.6.2.1 Selecting α 325
17.6.2.2 Selecting k
1
and k
2
327
17.6.2.3 Selecting thresh 327
17.6.3 Comparison of the Proposed Technique with mfsw 328
17.6.4 Additional Experiments 330
17.6.4.1 Running relation After mfsw 330
17.6.4.2 Running relation Twice 331
17.6.4.3 Minimizing Single Nodes 331
17.6.4.4 Effects of Early Quantification 331
17.7 Chapter Summary 332
References 333

Part V Applications to Specialized Design Scenarios
18 Synthesizing Combinational Logic to Generate Probabilities:
Theories and Algorithms 337
Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja
18.1 Introduction and Background 337
18.2 Related Work 341
18.3 Sets with Two Elements that Can Generate Arbitrary Decimal
Probabilities 341
18.3.1 Generating Decimal Probabilities from the Input
Probability Set S ={0.4, 0.5} 341
18.3.2 Generating Decimal Probabilities from the Input
Probability Set S ={0.5, 0.8} 345
18.4 Sets with a Single Element that Can Generate Arbitrary Decimal
Probabilities 348
18.5 Implementation 351
18.6 Empirical Validation 355
18.7 Chapter Summary 356
References 357
xvi Contents
19 Probabilistic Error Propagation in a Logic Circuit Using
the Boolean Difference Calculus 359
Nasir M ohyuddin, Ehsan Pakbaznia, and Massoud Pedram
19.1 Introduction 359
19.2 Error Propagation Using Boolean Difference Calculus 361
19.2.1 Partial Boolean Difference 361
19.2.2 Total Boolean Difference 362
19.2.3 Signal and Error Probabilities 363
19.3 Proposed Error Propagation Model 364
19.3.1 Gate Error Model 364
19.3.2 Error Propagation in 2-to-1 Mux Using BDEC 367

19.3.3 Circuit Error Model 369
19.4 Practical Considerations 370
19.4.1 Output Error Expression 370
19.4.2 Reconvergent Fanout 371
19.5 Simulation Results 373
19.6 Extensions to BDEC 377
19.6.1 Soft Error Rate (SER) Estimation Using BDEC 377
19.6.2 BDEC for Asymmetric Erroneous Transition
Probabilities 379
19.6.3 BDEC Applied to Emerging Nanotechnologies 379
19.7 Conclusions 379
References 380
20 Digital Logic Using Non-DC Signals 383
Kalyana C. Bollapalli, Sunil P. Khatri, and Laszlo B. Kish
20.1 Introduction 383
20.2 Previous Work 386
20.3 Our Approach 387
20.3.1 Standing Wave Oscillator 387
20.3.2 A Basic Gate 389
20.3.2.1 Multiplier 389
20.3.2.2 Low-Pass Filter 391
20.3.2.3 Output Stage 391
20.3.2.4 Complex Gates 392
20.3.3 Interconnects 392
20.4 Experimental Results 393
20.4.1 Sinusoid Generator 393
20.4.2 Gate Optimization 395
20.4.3 Gate Operation 397
20.5 Conclusions 399
References 400

Contents xvii
21 Improvements of Pausible Clocking Scheme for High-Throughput
and High-Reliability GALS Systems Design 401
Xin Fan, Milo
˘
sKrsti
´
c, and Eckhard Grass
21.1 Introduction 401
21.2 Analysis of Pausible Clocking Scheme 402
21.2.1 Local Clock Generators 402
21.2.2 Clock Acknowledge Latency 403
21.2.3 Throughput Reduction 404
21.2.3.1 Demand-Output (D-OUT) Port to Poll-Input
(P-IN) Port Channel 404
21.2.3.2 Other Point-to-Point Channels 406
21.2.3.3 Further Discussion on Throughput Reduction . . 406
21.2.4 Synchronization Failures 407
21.2.4.1 
LClkRx
< T
LClkRx
407
21.2.4.2 
LClkRx
≥ T
LClkRx
408
21.3 Optimization of Pausible Clocking Scheme 409
21.3.1 Optimized Local Clock Generator 409

21.3.2 Optimized Input Port 410
21.3.2.1 Double Latching Mechanism 410
21.3.2.2 Optimized Input Port Controller 411
21.4 Experimental Results 412
21.4.1 Input Wrapper Simulation 412
21.4.2 Point-to-Point Communication 415
21.5 Conclusions 415
References 416
Subject Index 419
Contributors
Kia Bazargan University of Minnesota, Minneapolis, MN USA,
Anna Bernasconi Department of Computer Science, Universit‘a di Pisa, Pisa,
Italy,
Kalyana C. Bollapalli NVIDIA Corporation, San Jose, CA, USA,

Robert Brayton University of California, Berkeley, CA, USA,

Chung-Ming Chan Fu Jen Catholic University, Taipei County, Taiwan,

Satrajit Chatterjee Strategic CAD Labs, Intel Corporation, Hillsboro, OR, USA,

Valentina Ciriani Department of Information Technologies, Universit‘a degli
Studi di Milano, Milano, Italy,
Jeff L. Cobb Texas Instruments, Sugar Land, TX USA,
Xin Fan Innovations for High Performance Microelectronics, Frankfurt (Oder),
Brandenburg, Germany,
Lei Fang Microsoft Corporation, Redmond, WA, USA,
Eugene Goldberg Northeastern University, Boston, MA, USA,

Sivaram Gopalakrishnan Synopsys Inc., Hillsboro, OR, USA,

Eckhard Grass Innovations for High Performance Microelectronics, Frankfurt
(Oder), Brandenburg, Germany,
Kanupriya Gulati Intel Corporation, Hillsboro, OR, USA,

Michael S. Hsiao Virginia Tech, Blacksburg, VA, USA,
xix
xx Contributors
Wei-Lun Hung National Taiwan University, Taipei, Taiwan,

Jie-Hong Roland Jiang National Taiwan University, Taipei, Taiwan,

Priyank Kalla University of Utah, Salt Lake City, UT, USA,
Hadi Katebi University of Michigan, Ann Arbor, MI, USA,

Sunil P. Khatri Department of ECE, Texas A&M University, College Station, TX,
USA,
Laszlo B. Kish Department of ECE, Texas A&M University, College Station, TX,
USA,
Nathan B. Kitchen University of Berkeley, Berkeley, CA, USA,

Victor N. Kravets IBM TJ Watson Research Center, Yorktown Heights, NY, USA,

Smita Krishnaswamy IBM TJ Watson Research Center, Yorktown Heights, NY,
USA,
Miloš Krsti
´
c Innovations for High Performance Microelectronics, Frankfurt
(Oder), Brandenburg, Germany,
Andreas Kuehlmann Cadence Design Systems, Inc., San Jose, CA, USA,

Ruei-Rung Lee National Taiwan University, Taipei, Taiwan,

David J. Lilja University of Minnesota, Minneapolis, MN USA,
Hsuan-Po Lin National Taiwan University, Taipei, Taiwan, centau-

Jung-Chang Liu Fu Jen Catholic University, Taipei County, Taiwan,

Panagiotis Manolios Northeastern University, Boston, MA, USA,

Igor Markov University of Michigan, Ann Arbor, MI, USA,

Joao Marques-Sila University College Dublin, Dublin, Ireland,
Alan Mishchenko Department of EECS, University of California, Berkeley, CA,
USA,
Contributors xxi
Nilesh Modi IBM TJ Watson Research Center, Yorktown Heights, NY, USA,

Nasir Mohyuddin Department of Electrical Engineering – Systems, University of
Southern California, Los Angeles, CA, USA,
Ehsan Pakbaznia Department of Electrical Engineering – Systems, University of
Southern California, Los Angeles, CA, USA,
Massoud Pedram Department of Electrical Engineering – Systems, University of
Southern California, Los Angeles, CA, USA,
Jordi Planes University de Lleida, Lleida, Spain,
Ruchir Puri IBM TJ Watson Research Center, Yorktown Heights, NY, USA,

Weikang Qian University of Minnesota, Minneapolis, MN, USA,

Haoxing Ren IBM TJ Watson Research Center, Yorktown Heights, NY, USA,

Marc D. Riedel University of Minnesota, Minneapolis, MN, USA,

Alberto Sangiovanni-Vincentelli University of Berkeley, Berkeley, CA, USA,

Subarna Sinha Synopsys Inc., Mountain View, CA, USA,

Duncan Smith Vennsa Technologies, Inc., Toronto, ON, Canada,

Gabriella Trucco Department of Information Technologies, Universit‘a degli
Studi di Milano, Milano, Italy,
Andreas Veneris University of Toronto, Toronto, ON, Canada,

Tiziano Villa Department of Computer Science, Universit‘a degli Studi di Verona,
Verona, Italy,
Kuo-Hua Wang Fu Jen Catholic University, Taipei County, Taiwan,

Yu-Shen Yang University of Toronto, Ontario, Canada,
Qi Zhu Intel Corporation, Hillsboro, OR, USA,
Chapter 1
Introduction
Sunil P. Khatri and Kanupriya Gulati
With the advances in VLSI technology, enhanced optimization techniques are
required to enable the design of faster electronic circuits that consume less power
and occupy a smaller area. In the VLSI design cycle, significant optimization oppor-
tunities exist in the logic design stage. In recent times, several research works have
been proposed in the area of logic synthesis, which can prove to be very valuable
for VLSI/CAD engineers. A solid understanding and sound implementation of these
advanced techniques would enable higher levels of optimization, and thus enable
better electronic design. This text is a systematic collection of important recent work

in the field of logic design and optimization.
Conventional logic synthesis consists of the following phases. Given an initial
netlist, technology-independent optimizations [1, 3, 4] are first carried out in order
to optimize various design criteria such as gate, literal, and net count. Both Boolean
and algebraic techniques are used, such as kernel and cube extraction, factorization,
node substitution, don’t care-based optimizations [2]. During the logic decomposi-
tion phase, large gates are decomposed into smaller gates, which allows for efficient
technology mapping and technology-dependent optimizations. Finally, technology
mapping is applied on the decomposed netlist which is followed by technology-
dependent optimizations. This book presents recent research in some of the above
areas.
In order to enhance the scalability and performance of logic synthesis
approaches, newer optimization styles are continually investigated. Boolean satis-
fiability (SAT) plays a big role in some of the recent logic optimization method-
ologies. Therefore, this edited volume also includes some of the latest research in
SAT techniques. Further, several non-CAD systems can be viewed as an instance of
logic optimization, and thus these too can take advantage of the rich body of recent
research in logic synthesis and optimization. Such non-traditional applications of
logic synthesis to specialized design scenarios are also included in this volume.
S.P. Khatri (B)
Department of ECE, Texas A&M University, College Station, TX, USA
e-mail:
S.P. Khatri, K. Gulati (eds.), Advanced Techniques in Logic Synthesis,
Optimizations and Applications, DOI 10.1007/978-1-4419-7518-8_1,
C

Springer Science+Business Media, LLC 2011
1
2 S.P. Khatri and K. Gulati
The approaches described in this text are enhanced and archival versions of the

corresponding original conference publications. The modifications include enhance-
ments to the original approach, more experimental data, additional background and
implementation details, along with as yet unpublished graphs and figures.
The different sections of this volume are described next.
1.1 Logic Decomposition
This section discusses the latest research in logic decomposition. The first chapter
investigates restructuring techniques based on decomposition and factorization. In
this chapter the authors describe new types of factorization that extend Shannon
cofactoring, using projection functions that change the Hamming distance of the
original minterms, to favor logic minimization of the component blocks.
The next chapter uses reachable state analysis and symbolic decomposition to
improve upon the synthesis of sequential designs. The approach described uses
under-approximation of unreachable states of a design to derive incomplete spec-
ification of the combinational logic. The resulting i ncompletely specified functions
are decomposed to optimize t echnology-dependent synthesis. The decomposition
choices are implicitly computed by using recursive symbolic bi-decomposition.
The third chapter in the topic of Boolean decomposition employs fast Boolean
techniques to restructure logic networks. The techniques used are a cut-based view
of a logic network, and heuristic disjoint-support decompositions. Local transfor-
mations to functions with a small number of inputs allow fast manipulations of
truth tables. The use of Boolean methods reduces the structural bias associated with
algebraic methods, while still allowing for high-speed.
The fourth chapter investigates Ashenhurst decomposition wherein both single
and multiple output decomposition can be formulated with satisfiability solving,
Craig interpolation, and functional dependency. In comparison to existing BDD-
based approaches for functional decomposition, Ashenhurst decomposition does not
suffer from memory explosion and scalability issues. A key feature of this approach
is that variable partitioning can be automated and integrated into the decomposi-
tion process without the bound-set size restriction. Further, the approach naturally
extends to nondisjoint decomposition.

The last chapter in the Boolean decomposition section focuses on scala-
bility and quality of Boolean function bi-decomposition. The quality of a bi-
decomposition is mainly determined by its variable partition. Disjoint and bal-
anced decompositions reduce communication and circuit complexity and yield
simple physical design solutions. Furthermore, finding a good or feasible parti-
tion may require costly enumeration, requiring separate decomposability checks.
This chapter uses interpolation and incremental SAT solving to address these
problems.
1 Introduction 3
1.2 Boolean Satisfiability
In the area of Boolean satisfiability, this book presents some key ideas to make
SAT more effective. The first chapter studies resolution proofs using bound-
ary points elimination. Given a CNF formula F, boundary points are complete
assignments that falsify only certain clauses of the formula. Since any resolu-
tion proof has to eventually eliminate all boundary points of F, this approach
focuses on resolution proofs from the viewpoint of boundary point elimina-
tion. The authors use equivalence checking formulas to compare unsatisfiabil-
ity proofs built by a conflict-driven SAT-solver. They show how every resolu-
tion of a specialized proof eliminates a boundary point, and how this enables
building resolution SAT-solvers that are driven by elimination of cut boundary
points.
The next chapter presents a methodology called SAT sweeping for simpli-
fying And-Inverter Graphs (AIGs) by systematically merging graph vertices in
a topological fashion starting from the inputs, using a combination of struc-
tural hashing, simulation, and SAT queries. This chapter presents the details of
a SAT-sweeping approach that exploits local observability don’t cares (ODCs)
to increase the number of vertices merged. In order to enhance the effi-
ciency and scalability of the approach, the authors bound the ODCs and thus
the computational effort to generate them. They demonstrate that the use of
ODCs in SAT sweeping results in significant graph simplification, with great

benefits for Boolean reasoning in functional verification and logic synthesis
techniques.
SAT-solvers find a satisfiable assignment for a propositional formula, but find-
ing the “optimal” solution for a given function is very expensive. The next
chapter discusses MIN-ONE SAT, an optimization problem which requires the
satisfying assignment with the minimal number of ones, which can be easily
applied to minimize an arbitrary linear objective function. The chapter proposes
an approximation algorithm for MIN-ONE SAT that is efficient and achieves
a tight bound on the solution quality. RelaxSAT generates a set of constraints
from the objective function to guide the search, and then these constraints are
gradually relaxed to eliminate the conflicts with the original Boolean SAT for-
mula until a solution is found. The experiments demonstrate that RelaxSAT is
able to handle very large instances which cannot be solved by existing MIN-
ONE algorithms. The authors further show that RelaxSAT is able to obtain
a very tight bound on the solution with one to two orders of magnitude
speedup.
The last chapter in the Boolean satisfiability category presents an algorithm
for MaxSAT that improves existing state-of-the-art solvers by orders of magnitude
on industrial benchmarks. The proposed algorithm is based on efficient identifica-
tion of unsatisfiable subformulas. Moreover, the new algorithm draws a connection
between unsatisfiable subformulas and the maximum satisfiability problem.
4 S.P. Khatri and K. Gulati
1.3 Boolean Matching
Three research works are presented under the Boolean matching category. The
first work proposes a methodology for Boolean matching under permutations of
inputs and outputs that enables incremental logic design by identifying sections of
netlist that are unaffected by incremental changes in design specifications. Identi-
fying and reusing the equivalent subcircuits accelerates design closure. By integrat-
ing graph-based, simulation-driven, and SAT-based techniques, this methodology
makes Boolean matching feasible for large designs.

The second approach in the Boolean matching category is DeltaSyn, a tool and
methodology for generating the logic difference between a modified high-level spec-
ification and an implemented design. By using fast functional and structural analysis
techniques, the approach first identifies equivalent signals between the original and
the modified circuits. Then, by using a topologically guided dynamic matching algo-
rithm, reusable portions of logic close to the primary outputs are identified. Finally,
functional hash functions are employed to locate similar chunks of logic throughout
the remainder of the circuit. Experiments on industrial designs show that together,
these techniques successfully implement incremental changes while preserving an
average of 97% of the pre-existing logic.
The last approach discussed in t he Boolean matching section proposes an incre-
mental learning-based algorithm, along with a Boolean satisfiability search, for solv-
ing Boolean matching. The proposed algorithm utilizes functional properties like
unateness and symmetry to reduce the search space. This is followed by the simu-
lation phase in which three types of input vector generation and checking methods
are used to match the inputs of two target functions. Experimental results on large
benchmark circuits demonstrate that the matching algorithm can efficiently solve
the Boolean matching for large Boolean networks.
1.4 Logic Optimization
The first advanced logic optimization approach presents algebraic techniques to
enhance common sub-expression extraction to allow circuit optimization. Common
sub-expression elimination (CSE) is a useful optimization technique in the synthesis
of arithmetic datapaths described at the RTL level.
The next chapter investigates a comprehensive methodology to automate logic
restructuring in combinational and sequential circuits. This technique algorithmi-
cally constructs the required transformation by utilizing Set of Pairs of Function
to be Distinguished (SPFDs). SPFDs can express more functional flexibility than
traditional don’t cares and have been shown to provide additional degrees of flex-
ibility during logic synthesis. In practice, however, computing SPFDs may suffer
from memory or runtime problems. This approach presents Approximate SPFDs

(ASPFDs) that approximate the information contained in SPFDs by using the results
1 Introduction 5
of test-vector simulation, thereby yielding an efficient and robust optimization plat-
form.
The third chapter presents an approach to enhance the determinization of a
Boolean relation by using interpolation. Boolean relations encapsulate the flexibility
of a design and are therefore an i mportant tool in system synthesis, optimization,
and verification to characterize solutions to a set of Boolean constraints. For phys-
ical realization, a deterministic function often has to be extracted from a relation.
Existing methods are limited in their handling of large problem instances. Exper-
imental results for the interpolation-based relation determinization approach show
that Boolean relations with thousands of variables can be effectively determinized
and the extracted functions are of reasonable quality.
In this section, the fourth approach presented is a scalable approach for dual-node
technology-independent optimization. This technique scales well and can minimize
large designs typical of industrial circuits. The methodology presented first selects
the node pairs to be minimized that are likely to give gains. For each node pair,
a window or a subnetwork is created around the nodes. This windowing is done
in order to allow the approach to scale to larger designs. Once the subnetwork is
created, the Boolean relation, which represents the flexibility of the nodes, is com-
puted. During this process, early quantification is performed which further extends
the scalability of the approach. The Boolean relation is minimized, and the new
nodes replace the original nodes in the original circuit. These steps are repeated
for all selected node pairs. The authors experimentally demonstrate that this tech-
nique produces minimized technology-independent networks that are on average
12% smaller than networks produced by state-of-the-art single-node minimization
techniques.
1.5 Applications to Specialized Design Scenarios
This volume presents applications of logic synthesis in non-traditional CAD areas.
The first approach investigates techniques for synthesizing logic that generates new

arbitrary probabilities from a given small set of probabilities. These ideas can be
used in probabilistic algorithms. Instead of using different voltage levels to generate
different probability values, which can be very expensive, the technique presented
in the chapter alleviates this issue by generating probabilities using combinational
logic.
The next chapter presents a gate-level probabilistic error propagation model
which takes as input the Boolean function of the gate, the signal and error prob-
abilities of the gate inputs, and the gate error probability and produces the error
probability at the output of the gate. The presented model uses Boolean difference
calculus and can be applied to the problem of calculating the error probability at
the primary outputs of a multilevel Boolean circuit. The time complexity of the
approach is linear in the number of gates in the circuit, and the results demonstrate
6 S.P. Khatri and K. Gulati
the accuracy and efficiency of the approach compared to the other known methods
for error calculation in VLSI circuits.
In the third chapter in the applications category, a novel realization of combina-
tional logic circuit is presented. In this approach, logic values 0 and 1 are imple-
mented as sinusoidal signals of the same frequency that are phase shifted by π.The
properties of such sinusoids can be used to identify a logic value without ambiguity,
and hence a realizable system of logic is created. The chapter further presents a
family of logic gates that can operate using such sinusoidal signals. In addition, due
to orthogonality of sinusoid signals with different frequencies, multiple sinusoids
could be transmitted on a single wire simultaneously, thereby naturally allowing the
approach to implement multilevel logic. One advantage of such a logic family is its
immunity from external additive noise and an improvement in switching (dynamic)
power.
The last chapter focuses on asynchronous circuit design issues. In Systems-on-a-
Chip (SOCs) and Networks-on-a-Chip (NoCs), using globally asynchronous locally
synchronous (GALS) system design for pausible clocking is widely popular. This
chapter investigates throughput reduction and synchronization failures introduced

by existing GALS pausible clocking schemes and proposes an optimized scheme
for more reliable GALS system design with higher performance. The approach min-
imizes the acknowledge latency and maximizes the safe timing region for inserting
the clock tree.
References
1. Brayton, R.K., Hachtel, G.D., Sangiovanni-Vincentelli, A.L.: Multilevel logic synthesis. In:
Proceedings of IEEE, 78(2):264–270 (1990)
2. Hassoun, S. (ed.): Logic Synthesis and Verification. San Jose, CA, USA (2001)
3. Sinha, S., Brayton, R.K.: Implementation and use of SPFDs in optimizing Boolean networks.
In: Proceedings of International Conference on Computer-Aided Design, pp. 103–110. Paris,
France (1998)
4. Wurth, B., Wehn, N.: Efficient calculation of Boolean relations for multi-level logic optimiza-
tion. In: Proceedings of European Design and Test Conference, pp. 630–634. (1994)
Part I
Logic Decomposition
Under logic decomposition this book presents five research works. The first chapter
proposes hypergraph partitioning and Shannon decomposition-based techniques for
logic decomposition. The second chapter uses reachable state analysis and sym-
bolic decomposition to improve upon the synthesis of sequential designs. Fast
Boolean decomposition techniques employing a cut-based view of a logic network
and heuristic disjoint-support decompositions are presented in the third work. The
fourth approach performs Ashenhurst decomposition formulated using satisfiability,
Craigs interpolation, and functional dependency. This last chapter in this category
uses interpolation and incremental SAT solving to improve the quality of Boolean
function decomposition.