PIC18F97J60 Family Data Sheet64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with docx

© 2006 Microchip Technology Inc. Advance Information DS39762A
PIC18F97J60 Family
Data Sheet
64/80/100-Pin, High-Performance,
1 Mbit Flash Microcontrollers
with Ethernet
DS39762A-page ii Advance Information © 2006 Microchip Technology Inc.
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
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The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
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FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
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© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
®

8-bit MCUs, KEELOQ
®

code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 1
PIC18F97J60 FAMILY
Ethernet Features:
• IEEE 802.3 compatible Ethernet Controller
• Integrated MAC and 10Base-T PHY
• 8-Kbyte Transmit/Receive Packet Buffer SRAM
• Supports one 10Base-T Port with Automatic Polarity
Detection and Correction
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous
Packets

• Activity Outputs for 2 LED Indicators
•Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware assisted checksum calculation for
various protocols
•MAC:
- Support for Unicast, Multicast and Broadcast
packets
- Programmable Pattern Match of up to 64 bytes
within packet at user-defined offset
- Programmable wake-up on multiple packet
formats
•PHY:
- Wave shaping output filter
- Loopback mode
Flexible Oscillator Structure:
• Selectable System Clock derived from single
25 MHz external source:
- 2.78 to 41.67 MHz
• Internal 31 kHz Oscillator
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if oscillator stops
• Two-Speed Oscillator Start-up
External Memory Bus
(100-pin devices only):
• Address capability of up to 2 Mbytes

• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
Peripheral Highlights:
• High-Current Sink/Source: 25 mA/25 mA on PORTB
and PORTC
• Five Timer modules (Timer0 to Timer4)
• Four External Interrupt pins
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Up to two Master Synchronous Serial Port (MSSP)
modules supporting SPI (all 4 modes) and I
2
C™
Master and Slave modes
• Up to two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
• 10-Bit, up to 16-Channel Analog-to-Digital Converter
module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
• Dual Analog Comparators with Input Multiplexing
• Parallel Slave Port (PSP) module
(100-pin devices only)

Special Microcontroller Features:
• 5.5V Tolerant Inputs (digital-only pins)
• Low-Power, High-Speed CMOS Flash Technology:
- Self-reprogrammable under software control
• C compiler Optimized Architecture for re-entrant code
• Power Management Features:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 134s
• Single-Supply 3.3V In-Circuit Serial Programming™
(ICSP™) via two pins
• In-Circuit Debug (ICD) with 3 Breakpoints via
two pins
• Operating Voltage Range of 2.35V to 3.6V (3.14V to
3.45V using Ethernet module)
• On-Chip 2.5V Regulator
64/80/100-Pin, High-Performance,
1-Mbit Flash Microcontrollers with Ethernet
PIC18F97J60 FAMILY
DS39762A-page 2 Advance Information © 2006 Microchip Technology Inc.
Pin Diagrams
Device
Flash
Program
Memory
(bytes)

SRAM
Data
Memory
(bytes)
Ethernet
TX/RX
Buffer
(bytes)
I/O
10-Bit
A/D (ch)
CCP/
ECCP
MSSP
EUSART
Comparators
Timers
8/16-Bit
PSP
External
Memory Bus
SPI
Master
I
2
C™
PIC18F66J60 64K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F66J65 96K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F67J60 128K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F86J60 64K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N

PIC18F86J65 96K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F87J60 128K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F96J60 64K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F96J65 96K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F97J60 128K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F66J65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
VDD
MCLR

VSS
VDDCORE/VCAP
OSC2/CLKO
OSC1/CLKI
15
16
31
40
39
27 28
29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64
63 62 61
64-Pin TQFP
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
VSS
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1

RC3/SCK1/SCL1
RC2/ECCP1/P1A
RC5/SDO1
V
DDRX
TPIN+
TPIN-
VSSRX
RE2/P2B
RE3/P3C
RE4/P3B
RE5/P1C
RD0/P1B
RD1/ECCP3/P3A
RD2/CCP4/P3D
V
SSPLL
VDDPLL
RBIAS
V
SSTX
TPOUT+
TPOUT-
V
DDTX
VSS
RE1/P2C
RE0/P2D
RG4/CCP5/P1D
RF7/SS1

RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RF5/AN10/CV
REF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
ENVREG
RF1/AN6/C2OUT
AV
DD
AVSS
RA3/AN3/VREF+
RA2/AN2/V
REF-
RA1/LEDB/AN1
RA0/LEDA/AN0
V
SS
VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2/P2A
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
PIC18F67J60

PIC18F66J60
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 3
PIC18F97J60 FAMILY
Pin Diagrams (Continued)
PIC18F86J65
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32
RE2/P2B
RE3/P3C
(2)
RE4/P3B
(2)
RE5/P1C
(2)
RE6/P1B
(2)
RE7/ECCP2
(1)
/P2A
(1)
RD0
V
DD
VSS
RD1
RD2
RE1/P2C
RE0/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D
VSS
VDDCORE/VCAP

RF7/SS1
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
V
SS
OSC2/CLKO
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
ENVREG
RF1/AN6/C2OUT
AV
DD
AVSS
RA3/AN3/VREF+
RA2/AN2/V
REF-
RA1/LEDB/AN1
RA0/LEDA/AN0
V
SS

VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2
(1)
/P2A
(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO1
RH1
RH0
1
2
RH2
RH3
17
18
RH7/AN15/P1B
(2)
RH6/AN14/P1C
(2)
RH5/AN13/P3B
(2)
RH4/AN12/P3C
(2)
RJ5
RJ4
37

50
49
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 7378 77 76 757980
80-Pin TQFP
Pinouts are preliminary and subject to change.
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
RF5/AN10/CV
REF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
VSSPLL
VDDPLL
RBIAS
V

SSTX
TPOUT+
TPOUT-
V
DDTX
VDDRX
TPIN+
TPIN-
V
SSRX
PIC18F87J60
PIC18F86J60
PIC18F97J60 FAMILY
DS39762A-page 4 Advance Information © 2006 Microchip Technology Inc.
Pin Diagrams (Continued)
92
94
93
91
90
89
88
87
86
85
84
83
82
81
80

79
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43

42
41
40
39
28
29
30
31
32
33
34
35
36
37
38
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67

66
75
74
73
58
57
24
23
25
96
98
97
99
27
46
47
48
49
50
55
54
53
52
51
100
100-Pin TQFP
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2

(1)
/P2A
(1)
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
V
SS
OSC2/CLKO
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RC5/SDO1
RJ7/UB
RJ6/LB
RJ2/WRL
RJ3/WRH
RE1/AD9/WR/P2C
RE0/AD8/RD
/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D

V
SS
VDDCORE/VCAP
RF7/SS1
RH2/A18
RH3/A19
RH7/AN15/P1B
(2)
RH6/AN14/P1C
(2)
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
RE2/AD10/CS/P2B
RE3/AD11/P3C
(2)
RE4/AD12/P3B
(2)
RE5/AD13/P1C
(2)
RE6/AD14/P1B
(2)
RE7/AD15/ECCP2
(1)
/P2A
(1)
RD0/AD0/PSP0
V

DD
VSS
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4/SDO2
RD5/AD5/PSP5/SDI2/SDA2
RD6/AD6/PSP6/SCK2/SCL2
RJ0/ALE
RJ1/OE
RH1/A17
RH0/A16
ENVREG
RF1/AN6/C2OUT
AV
DD
AVSS
RA3/AN3/VREF+
RA2/AN2/V
REF-
RA1/LEDB/AN1
RA0/LEDA/AN0
V
SS
VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2
(1)
/P2A

(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RH5/AN13/P3B
(2)
RH4/AN12/P3C
(2)
RJ5/CE
RJ4/BA0
VSS
VSSPLL
VDDPLL
RBIAS
V
SSTX
TPOUT+
TPOUT-
V
DDTX
VDDRX
TPIN+
TPIN-
V
SSRX
RG6
RG5
RF0/AN5
V
DD

RG7
V
SS
RD7/AD7/PSP7/SS2
VDD
PIC18F96J65
PIC18F97J60
Pinouts are preliminary and subject to change.
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
NC
PIC18F96J60
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 5
PIC18F97J60 FAMILY
Table of Contents
1.0 Device Overview 7
2.0 Oscillator Configurations 39
3.0 Power-Managed Modes 45
4.0 Reset 53
5.0 Memory Organization 67
6.0 Flash Program Memory 95
7.0 External Memory Bus 105
8.0 8 x 8 Hardware Multiplier 117
9.0 Interrupts 119
10.0 I/O Ports 135
11.0 Timer0 Module 163
12.0 Timer1 Module 167
13.0 Timer2 Module 173
14.0 Timer3 Module 175
15.0 Timer4 Module 179

16.0 Capture/Compare/PWM (CCP) Modules 181
17.0 Enhanced Capture/Compare/PWM (ECCP) Module 189
18.0 Ethernet Module 205
19.0 Master Synchronous Serial Port (MSSP) Module 255
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) 301
21.0 10-Bit Analog-to-Digital Converter (A/D) Module 325
22.0 Comparator Module 335
23.0 Comparator Voltage Reference Module 341
24.0 Special Features of the CPU 345
25.0 Instruction Set Summary 359
26.0 Development Support 409
27.0 Electrical Characteristics 413
28.0 DC and AC Characteristics Graphs and Tables 449
29.0 Packaging Information 451
Appendix A: Revision History 455
Appendix B: Device Differences 455
Index 457
The Microchip Web Site 469
Customer Change Notification Service 469
Customer Support 469
Reader Response 470
Product Identification System 471
PIC18F97J60 FAMILY
DS39762A-page 6 Advance Information © 2006 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2006 Microchip Technology Inc. Advance Information DS39762A-page 7
PIC18F97J60 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
This family introduces a new line of low-voltage devices
with the foremost traditional advantage of all PIC18
microcontrollers – namely, high computational per-
formance and a rich feature set at an extremely
competitive price point. These features make the
PIC18F97J60 family a logical choice for many
high-performance applications where cost is a primary
consideration.

1.1 Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F97J60 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
1.1.2 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F97J60 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
options include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes, which
allows clock speeds of up to 41.67 MHz.
• An internal RC oscillator with a fixed 31 kHz
output which provides an extremely low-power
option for timing-insensitive applications.
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3 EXPANDED MEMORY
The PIC18F97J60 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 100 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The PIC18F97J60 family also provides plenty of room
for dynamic application data with 3808 bytes of data
RAM.
1.1.4 EXTERNAL MEMORY BUS
In the unlikely event that 128 Kbytes of memory are

inadequate for an application, the 100-pin members of
the PIC18F97J60 family also implement an external
memory bus. This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim. This allows additional memory
options, including:
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.5 EXTENDED INSTRUCTION SET
The PIC18F97J60 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.
1.1.6 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
• PIC18F66J60 • PIC18F87J60
• PIC18F66J65 • PIC18F96J60
• PIC18F67J60 • PIC18F96J65
• PIC18F86J60 • PIC18F97J60
• PIC18F86J65

PIC18F97J60 FAMILY
DS39762A-page 8 Advance Information © 2006 Microchip Technology Inc.
1.2 Other Special Features
• Communications: The PIC18F97J60 family
incorporates a range of serial communication
peripherals, including up to two independent
Enhanced USARTs and up to two Master SSP
modules, capable of both SPI and I
2
C™ (Master
and Slave) modes of operation. In addition, one of
the general purpose I/O ports can be reconfigured
as an 8-bit Parallel Slave Port for direct
processor-to-processor communications.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP (ECCP) modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several
different operations at once. Each of the three
ECCP modules offers up to four PWM outputs,
allowing for a total of twelve PWMs. The ECCP
modules also offer many beneficial features,
including polarity selection, programmable dead
time, auto-shutdown and restart and Half-Bridge
and Full-Bridge Output modes.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and

thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 27.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F97J60 family are available in
64-pin, 80-pin and 100-pin packages. Block diagrams
for the three groups are shown in Figure 1-1,
Figure 1-2 and Figure 1-3.
The devices are differentiated from each other in four
ways:
1. Flash program memory (three sizes, ranging
from 64 Kbytes for PIC18FX6J60 devices to
128 Kbytes for PIC18FX7J60 devices).
2. A/D channels (eleven for 64-pin devices, fifteen
for 80-pin pin devices and sixteen for 100-pin
devices).
3. Serial communication modules (one EUSART
module and one MSSP module on 64-pin
devices, two EUSART modules and one MSSP
module on 80-pin devices and two EUSART
modules and two MSSP modules on 100-pin
devices
4. I/O pins (39 on 64-pin devices, 55 on 80-pin
devices and 70 on 100-pin devices).
All other features for devices in this family are identical.

These are summarized in Table 1-1, Table 1-2 and
Table 1-3.
The pinouts for all devices are listed in Table 1-4,
Table 1-5 and Table 1-6.
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 9
PIC18F97J60 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES)
TABLE 1-2: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (80-PIN DEVICES)
Features PIC18F66J60 PIC18F66J65 PIC18F67J60
Operating Frequency DC – 41.67 MHz DC – 41.67 MHz DC – 41.67 MHz
Program Memory (Bytes) 64K 96K 128K
Program Memory (Instructions) 32764 49148 65532
Data Memory (Bytes) 3808
Interrupt Sources 26
I/O Ports Ports A, B, C, D, E, F, G
I/O Pins 39
Timers 5
Capture/Compare/PWM Modules 2
Enhanced Capture/Compare/PWM Modules 3
Serial Communications MSSP (1), Enhanced USART (1)
Ethernet Communications (10Base-T) Yes
Parallel Slave Port Communications (PSP) No
External Memory Bus No
10-Bit Analog-to-Digital Module 11 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,
Stack Underflow, MCLR
, WDT (PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 64-Pin TQFP
Features PIC18F86J60 PIC18F86J65 PIC18F87J60

Operating Frequency DC – 41.67 MHz DC – 41.67 MHz DC – 41.67 MHz
Program Memory (Bytes) 64K 96K 128K
Program Memory (Instructions) 32764 49148 65532
Data Memory (Bytes) 3808
Interrupt Sources 27
I/O Ports Ports A, B, C, D, E, F, G, H, J
I/O Pins 55
Timers 5
Capture/Compare/PWM Modules 2
Enhanced Capture/Compare/PWM Modules 3
Serial Communications MSSP (1), Enhanced USART (2)
Ethernet Communications (10Base-T) Yes
Parallel Slave Port Communications (PSP) No
External Memory Bus No
10-Bit Analog-to-Digital Module 15 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,
Stack Underflow, MCLR
, WDT (PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 80-Pin TQFP
PIC18F97J60 FAMILY
DS39762A-page 10 Advance Information © 2006 Microchip Technology Inc.
TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-PIN DEVICES)
Features PIC18F96J65 PIC18F97J60 PIC18F86J10
Operating Frequency DC – 41.67 MHz DC – 41.67 MHz DC – 41.67 MHz
Program Memory (Bytes) 64K 96K 128K
Program Memory (Instructions) 32764 49148 65532
Data Memory (Bytes) 3808
Interrupt Sources 29
I/O Ports Ports A, B, C, D, E, F, G, H, J

I/O Pins 70
Timers 5
Capture/Compare/PWM Modules 2
Enhanced Capture/Compare/PWM Modules 3
Serial Communications MSSP (2), Enhanced USART (2)
Ethernet Communications (10Base-T) Yes
Parallel Slave Port Communications (PSP) Yes
External Memory Bus Yes
10-Bit Analog-to-Digital Module 16 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,
Stack Underflow, MCLR
, WDT (PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 100-Pin TQFP
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 11
PIC18F97J60 FAMILY
FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0

FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL


PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch
20
8
8
Table Pointer<21>

inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-4 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8

ECCP2
ROM Latch
ECCP3 CCP4 CCP5
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5
(1)
RC0:RC7
(1)
RD0:RD2
(1)
RE0:RE5
(1)
RF1:RF7
(1)
RG4
(1)
PORTB
RB0:RB7
(1)
Timer4
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation

V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Ethernet
PIC18F97J60 FAMILY
DS39762A-page 12 Advance Information © 2006 Microchip Technology Inc.
FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8

BITOP
8
8
ALU<8>
8
8
3
W
8
8
8
Instruction
Decode &
Control
State Machine
Control Signals
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5
(1)
RC0:RC7
(1)
RD0:RD2
(1)
RE0:RE7
(1)

RF1:RF7
(1)
RG0:RG4
(1)
PORTB
RB0:RB7
(1)
PORTH
RH0:RH7
(1)
PORTJ
RJ4:RJ5
(1)
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
EUSART2
ECCP2 ECCP3
CCP4 CCP5
Timer4
Note 1: See Table 1-5 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
OSC1/CLKI
OSC2/CLKO
V
DD, VSS

Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Data Address<12>
12
Access

BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
PCLATU
PCU
Instruction Bus <16>
STKPTR
Bank

Decode
ROM Latch
Ethernet
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 13
PIC18F97J60 FAMILY
FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W
8
8
8
Instruction
Decode &
Control
Data Address<12>
12
Access

BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL


PCLATH
8
31 Level Stack
Program Counter
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU

Instruction Bus <16>
STKPTR
Bank
State Machine
Control Signals
Decode
System Bus Interface
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5
(1)
RC0:RC7
(1)
RD0:RD7
(1)
RE0:RE7
(1)
RF0:RF7
(1)
RG0:RG7
(1)
PORTB
RB0:RB7

(1)
PORTH
RH0:RH7
(1)
PORTJ
RJ0:RJ7
(1)
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
EUSART2
ECCP2 ECCP3
MSSP2CCP4 CCP5
Timer4
Note 1: See Table 1-6 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator

Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Ethernet
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch
PIC18F97J60 FAMILY
DS39762A-page 14 Advance Information © 2006 Microchip Technology Inc.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS
Pin Name

Pin Number
Pin
Type
Buffer
Type
Description
TQFP
MCLR
7 I ST Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI
OSC1
CLKI
39
I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in internal RC mode; CMOS
otherwise.
External clock source input. Always associated
with pin function OSC1. (See related OSC2/CLKO pin.)
OSC2/CLKO
OSC2
CLKO
40
O
O

—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In internal RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/LEDA/AN0
RA0
LEDA
AN0
24
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDA indicator output.
Analog input 0.
RA1/LEDB/AN1
RA1
LEDB
AN1
23
I/O
O

I
TTL
—
Analog
Digital I/O.
Ethernet LEDB indicator output.
Analog input 1.
RA2/AN2/V
REF-
RA2
AN2
V
REF-
22
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/V
REF+
RA3
AN3
V
REF+
21

I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
28
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
RA5/AN4
RA5
AN4
27
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 15
PIC18F97J60 FAMILY
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
3
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
Enhanced PWM Fault input (ECCP modules); enabled
in software.
RB1/INT1
RB1
INT1
4
I/O
I
TTL

ST
Digital I/O.
External interrupt 1.
RB2/INT2
RB2
INT2
5
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
RB3/INT3
RB3
INT3
6
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
RB4/KBI0
RB4
KBI0
44
I/O
I
TTL

TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1
RB5
KBI1
43
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
42
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3

PGD
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
PIC18F97J60 FAMILY
DS39762A-page 16 Advance Information © 2006 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0

T1OSO
T13CKI
30
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2
P2A
29
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.

RC2/ECCP1/P1A
RC2
ECCP1
P1A
33
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
34
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C™ mode.

RC4/SDI1/SDA1
RC4
SDI1
SDA1
35
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I
2
C data I/O.
RC5/SDO1
RC5
SDO1
36
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1

31
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1 pin).
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1 pin).
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer

Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 17
PIC18F97J60 FAMILY
PORTD is a bidirectional I/O port.
RD0/P1B
RD0
P1B
60
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output B.
RD1/ECCP3/P3A
RD1
ECCP3
P3A
59
I/O
I/O
O
ST

ST
—
Digital I/O.
Capture 3 input/Compare 3 output/PWM 3 output.
ECCP3 PWM output A.
RD2/CCP4/P3D
RD2
CCP4
P3D
58
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM 4 output.
ECCP4 PWM output D.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
PIC18F97J60 FAMILY
DS39762A-page 18 Advance Information © 2006 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/P2D
RE0
P2D
2
I/O
O
ST
—
Digital I/O.
ECCP2 PWM output D.
RE1/P2C
RE1
P2C
1
I/O
O
ST
—
Digital I/O.
ECCP2 PWM output C.
RE2/P2B
RE2
P2B
64

I/O
O
ST
—
Digital I/O.
ECCP2 PWM output B.
RE3/P3C
RE3
P3C
63
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output C.
RE4/P3B
RE4
P3B
62
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output B.
RE5/P1C
RE5
P1C
61

I/O
O
ST
—
Digital I/O.
ECCP1 PWM output C.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 19
PIC18F97J60 FAMILY
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
I/O
I

O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
RF2/AN7/C1OUT
RF2
AN7
C1OUT
16
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
RF3/AN8
RF3
AN8
15
I/O
I
ST
Analog
Digital I/O.

Analog input 8.
RF4/AN9
RF4
AN9
14
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
RF5/AN10/CV
REF
RF5
AN10
CVREF
13
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 10.
Comparator reference voltage output.
RF6/AN11
RF6
AN11
12

I/O
I
ST
Analog
Digital I/O.
Analog input 11.
RF7/SS1
RF7
SS1
11
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
PIC18F97J60 FAMILY

DS39762A-page 20 Advance Information © 2006 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM 5 output.
ECCP1 PWM output D.
V
SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
V
DD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AV
DD 19 P — Positive supply for analog modules.
ENVREG 18 I ST Enable for on-chip voltage regulator.
V
DDCORE/VCAP
VDDCORE
VCAP
10
P

P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
V
SSPLL 55 P — Ground reference for Ethernet PHY PLL.
VDDPLL 54 P — Positive 3.3V supply for Ethernet PHY PLL.
V
SSTX 52 P — Ground reference for Ethernet PHY transmit subsystem.
VDDTX 49 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.
V
SSRX 45 P — Ground reference for Ethernet PHY receive subsystem.
VDDRX 48 P — Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 53 P — Bias current for Ethernet PHY. Must be tied to V
SS via a resistor;
see Section 18.0 “Ethernet Module” for specification.
TPOUT+ 51 O — Ethernet differential signal output.
TPOUT- 50 O — Ethernet differential signal output.
TPIN+ 47 I Analog Ethernet differential signal input.
TPIN- 46 I Analog Ethernet differential signal input.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type

Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 21
PIC18F97J60 FAMILY
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
M
CLR 9 I ST Master Clear (Reset) input. This pin is an active-low Reset to
the device.
OSC1/CLKI
OSC1
CLKI
49
I
I
ST
CMOS
Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in internal RC mode; CMOS
otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC2/CLKO pin.)
OSC2/CLKO
OSC2
CLKO
50
O
O
—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In internal RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/LEDA/AN0
RA0
LEDA
AN0
30
I/O
O
I
TTL
—

Analog
Digital I/O.
Ethernet LEDA indicator output.
Analog input 0.
RA1/LEDB/AN1
RA1
LEDB
AN1
29
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDB indicator output.
Analog input 1.
RA2/AN2/V
REF-
RA2
AN2
V
REF-
28
I/O
I
I
TTL
Analog

Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/V
REF+
RA3
AN3
V
REF+
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
34
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.

RA5/AN4
RA5
AN4
33
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762A-page 22 Advance Information © 2006 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
5
I/O
I

I
TTL
ST
ST
Digital I/O.
External interrupt 0.
Enhanced PWM Fault input (ECCP modules); enabled
in software.
RB1/INT1
RB1
INT1
6
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
RB2/INT2
RB2
INT2
7
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
RB3/INT3
RB3

INT3
8
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
RB4/KBI0
RB4
KBI0
54
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1
RB5
KBI1
53
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB6/KBI2/PGC
RB6

KBI2
PGC
52
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin

Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
© 2006 Microchip Technology Inc. Advance Information DS39762A-page 23
PIC18F97J60 FAMILY
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.

Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2
(1)
P2A
(1)
35
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
RC2/ECCP1/P1A
RC2
ECCP1
P1A
43
I/O
I/O
O
ST

ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
44
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
45
I/O
I
I/O
ST

ST
ST
Digital I/O.
SPI data in.
I
2
C data I/O.
RC5/SDO1
RC5
SDO1
46
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1
37
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.

EUSART1 synchronous clock (see related RX1/DT1 pin).
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1 pin).
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).