PROCEEDINGS OF THE 7TH INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS

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<b>REV 2013 KỶ YẾU </b>

<b>Hội nghị Quốc gia về Điện tử - Truyền thông </b>

Hà Nội, ngày 17-18/12/2013

<b>Chào mừng kỷ niệm 25 năm thành lập Hội Vô tuyến Điện tử Việt Nam </b>

Hội Vô tuyến Điện tử Việt Nam

Chương trình Khoa học Cơng nghệ trọng điểm cấp Nhà nước KC01 Trường Đại học Công nghệ, Đại học Quốc gia Hà Nội

Nhà xuất bản Đại học Quốc Gia Hà Nội

<b>KC01 </b>

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<b>A T C / R E V 2 0 1 4</b>

<b>O c t o b e r 1 5 – 1 7 , 2 0 1 4 </b>

<small> The International Conference on Advanced Technologies for Communications (ATC/REV) is an annual conference series, co-organized by the Radio Electronics Association of Vietnam (REV) and the IEEE Communications Society (IEEE ComSoc). The goal of the series is twofold: to foster an international forum for scientific and technological exchange among Vietnamese and worldwide scientists and engineers in the fields of electronics, communications and related areas, and to gather their high-quality research contributions. </small>

<small> Started in 2008 in Hanoi, the conference has made a great tour across Vietnam, for better promoting its scientific development (2009 - Haiphong, 2010 – Ho Chi Minh City, 2011 - Danang, 2012 – Hanoi, 2013 – Ho Chi Minh City). We now invite you to return to Hanoi city for the 7th meeting – the ATC/REV 2014 – to be held during October 15–17, 2014, and hosted by Posts and Telecommunications Institute of Technology. </small>

<b><small>TECHNICAL PROGRAM </small></b>

<small>The conference program includes the regular tracks and special sessions spread over three days. In addition, a number of tutorial sessions will be scheduled on the day before the conference starts. Authors are invited to submit original unpublished papers. Topics of interest include but are not limited to: </small>

<b><small>Communications track </small></b>

<small> Communication Theory </small>

<small> Information & Coding Theory </small>

<small> Communication Quality, Reliability & Modeling </small>

<small> Communications & Information Security  Wireless Communications </small>

<small> Optical Communication & Networking </small>

<b><small>Microwave & Antennas track </small></b>

<small> Antennas & Propagation </small>

<small> Microwave Theory & Techniques </small>

<small> RF, Microwave Systems and Applications </small>

<b><small>Networks track </small></b>

<small> Ad Hoc & Sensor Networks </small>

<small> Computer Communications </small>

<small> Satellite Communications </small>

<small> Network Operations & Management </small>

<small> Communication Switching & Routing </small>

<small> Analog and Mixed-Signal Circuits </small>

<small> Embedded Systems, IP & Systems Design </small>

<small> Synthesis, Optimization, Verification & Testing </small>

<small> Consumer and Multimedia Systems </small>

<small> Circuits and Systems for Communications </small>

<b><small>Signal Processing track </small></b>

<small> Signal and Image Processing </small>

<small> Speech and Video Processing </small>

<small> Signal Processing for Communications </small>

<b><small>SUBMISSION & POLICIES </small></b>

<small>All papers must be submitted electronically, in PDF format, and uploaded on EDAS. The direct link for paper submission is at o/N16379. The submissions should be formatted with single-spaced, double-column pages using at least 10 pt (or higher) size fonts on A4 or letter pagesin IEEE style format. Detailed formatting and submission instructions will be available on the conference web site ( </small>

<small>Submitted papers (for both regular and special sessions) are subject to a blind review process handled by an international technical program committee. An author of an accepted paper must be registered at full rate (member or non-member of the IEEE or REV) prior to uploading the camera-ready version. The maximum length of the camera-ready version is 6 pages. Accepted and presented papers will be included in the IEEE Xplore Digital Library. The IEEE reserves the right to exclude a paper from distribution after the conference (e.g., removal from IEEE Xplore) if the paper is not presented at the conference. </small>

<b><small>Regular/special paper submission: </small></b>

<small>Manuscript submission: April 30, 2014</small>

<small>Notification of acceptance: Jul. 30, 2014 Camera-ready submission: Aug. 30, 2014 </small>

<b><small>Technical program chairs </small></b>

<i><small>Arumugam Nallanathan, King's College London, UK Trung Q. Duong, Queen’s University Belfast, UK Vo Nguyen Quoc Bao, Posts & Telecom. Inst. Tech., VN </small></i>

<b><small>Australia & the Pacific </small></b>

<i><small>Eryk Dutkiewicz, MQ, Australia Dinh-Thong Nguyen, UTS, Australia </small></i>

<b><small>Middle-East & Africa</small></b>

<i><small>Boualem Boashash, QU, Qatar </small></i>

<b><small>Europe </small></b>

<i><small>Maurice Bellanger, CNAM, France Merouane Debbah, SUPELEC, France Pierre Duhamel, L2S/SUPELEC, France Yacine Ghamri-Doudane, ENSIIE, France Peter Müller, IBM Zurich, Switzerland Matthias Pätzold, UiA, Norway Zebo Peng, LiU, Sweden </small></i>

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<b>CALL FOR PAPER </b>

REV Journal on Electronics and Communications (REV-JEC) is a quarterly peer-reviewed research journal, dedicated to providing a leading edge forum for researchers and professionals to contribute and disseminate innovative research ideas and results in the fields of electronics and communications.

REV-JEC offers three different formats of articles: regular, short and correspondence. While it is required for a regular article to present substantial scientific contributions in sufficient details; a short article should present a complete study with significant contributions, usually more limited in scope than what is found in a regular article; and a correspondence article may offer new ideas, new results or comments that need to be quickly communicated.

We invite submission of high-quality papers presenting original, previously unpublished, research ideas and results on both theoretical and applied aspects in all areas of electronics and communications. These areas include, but are not limited to, the following topics:

<i>Automation and Control track</i>

 Automation Systems  Adaptive Control

 Linear & Nonlinear Control  Optimal Control

 Robotics

<i>Communications track</i>

 Communication Theory  Information & Coding Theory  Communication Quality, Reliability &

Modeling

 Communications & Information Security  Wireless Communications

<i>Electronics track</i>

 Analog & Mixed-Signal Circuits

 Embedded Systems, IP & Systems Design  Synthesis, Optimization, Verification &

Testing

 Consumer & Multimedia Systems  Circuits & Systems for Communications

<i>Microwave & Antennas track</i>

 Antennas & Propagation

 Microwave Theory & Techniques  RF, Microwave Systems & Applications

<i>Networks track</i>

 Ad Hoc & Sensor Networks  Computer Communications  Internet

 Optical Networking  Satellite Communications  High-Speed Networking

 Network Operations & Management  Communication Switching & Routing  Emergency Communications

<i>Signal Processing track</i>

 Signal Processing Theory

 Audio & Acoustic Signal Processing

 Image & Video Signal Processing & Coding  Speech Processing

 Biomedical Signal Processing & Imaging  Signal Processing for Communications &

Networking

 Information Forensics & Security

 Signal Processing Applications & Systems Manuscripts should be written in English. Whenever applicable, submissions should include the following elements: title, authors, affiliations, contacts, abstract, index terms, main text, acknowledgement, and references. Submitted manuscripts should be formatted into A4-size, double-spaced, single-column pages, with main text of 12-point type. Regular research paper submissions should ideally not exceed 30 double-spaced pages in length, including tables and figures. This length corresponds roughly to 7 pages in print (single-spaced, two-column format). Prospective authors should submit their full-text manuscript for publication consideration in a single PDF or Microsoft Word file via email to the journal secretary at Other file formats will not be accepted.

Phone: +84 4 37549271 – Email: – Website:

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<b>ĐIỆN TỬ - TRUYỀN THÔNG </b>

<b>VỚI CÁC NGÀNH CÔNG NGHỆ CAO </b>

<i>17 – 18 tháng 12, 2013 Hà Nội </i>

<b>Đơn vị tổ chức Đơn vị tài trợ</b>

<i><b><small>CÔNGNGHỆ</small>^HỌC</b></i>

<b>KC01</b>

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<b>Hội nghị Quốc gia về </b>

<b>Điện tử - Truyền thông với Các ngành công nghệ cao 2013 </b>

<b>Ban chỉ đạo ________________________________________________________ vi Ban tổ chức ________________________________________________________ vii Ban chương trình và Ban thư ký ______________________________________ viii </b>

<b>Báo cáo mời </b>

Xu hướng phát triển và định hướng quy hoạch tần số cho vô tuyến băng rộng của Việt Nam __________ 1

<i>Ths. Đồn Quang Hoan </i>

Một số chính sách mới của khoa học và công nghệ cho phát triển lĩnh vực công nghệ thông tin và truyền thông _________________________________________________________________________ 2

<i>Prof. Nguyen Van Ngo </i>

<b>Báo cáo tại các phiên </b>

Đánh giá hiệu năng giao thức cây thu thập dữ liệu có sự nhận thức về năng lượng _________________ 19

<i>Vũ Chiến Thắng, Nguyễn Chấn Hùng, Lê Nhật Thăng </i>

Giải pháp bảo mật và xác thực cho văn phòng điện tử _______________________________________ 26

<i>Hồ Văn Hương, Hoàng Chiến Thắng, Nguyễn Quốc Uy </i>

Implementing Rate Adaptive Algorithm in EnergyAware Data Center Network ___________________ 32

<i>Tran Manh Nam, Tran Hoang Vu, Vu Quang Trong, Nguyen Huu Thanh, Pham Ngoc Nam </i>

Nghiên cứu khắc phục ảnh hưởng của trễ truyền thông trong các hệ thống điều khiển có nối mạng ____ 38

<i>Nguyễn Trọng Các, Nguyễn Văn Khang </i>

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<i>Tan-Vinh Le, Binh-Son Le, Trung-Khanh Le, Trong-Tu Bui </i>

System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder _____________ 51

<i>Hai-Phong Phan, Hung K. Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran </i>

Hệ thống cảm biến giọt chất lỏng trong kênh dẫn ___________________________________________ 56

<i>Nguyễn Đắc Hải, Vũ Quốc Tuấn, Phạm Quốc Thịnh, Chử Đức Trình </i>

Heart rate monitor and QRS detection using microcontroller __________________________________ 61

<i>Hoang ChuDuc, Thuan NguyenDuc </i>

Design and implementation of a watermarking method using perceptually important sub-image ______ 66

<i>Nguyen Ngoc Minh, Nguyen Le Cuong </i>

Designing digital filters by method of assigned transition bandwidth ___________________________ 70

<i>Nguyen Xuan Truong </i>

Một phương pháp xây dựng hệ mật mã khối kết hợp sơ đồ Lai-Massey với sơ đồ Feistel và ứng dụng vào hàm băm ______________________________________________________________________ 75

<i>Ngô Đức Thiện, Nguyễn Trung Hiếu, Nguyễn Tồn Thắng, Đặng Hồi Bắc </i>

Trích chọn đặc trưng cho bài toán nhận dạng cảm xúc bằng thuật toán Gabor Wavelet _____________ 81

<i>Lê Đức Tồn, Nguyễn Thị Ngọc Bích, Diệp Nhật Huy, Huỳnh Hữu Thuận </i>

Thiết kế bộ đo lường quán tính sử dụng bộ lọc Kalman mở rộng _______________________________ 88

<i>Nguyễn Quang Vịnh, Trần Xuân Kiên, Bùi Hông Huế </i>

Hệ thống mạng camera xử lý hình ảnh thơng minh phục vụ điều khiển giao thông và giám sát an ninh _ 95

<i>Phạm Hồng Quang, Nguyễn Hữu Tình, Bùi Phú Huy, Tạ Tuấn Anh </i>

Thiết kế lắp đặt hệ thống camera giám sát giao thông đường cao tốc ___________________________ 101

<i>Tạ Tuấn Anh, Phạm Hồng Quang </i>

Thiết kế, chế tạo thiết bị đo lường bức xạ ion hóa _________________________________________ 107

<i>Nguyễn Cảnh Việt, La Minh Tuấn, Trịnh Ngọc Duy, Phạm Quốc Triệu </i>

Development of a Behavior-based Navigation System for Mobile Robot in Unknown Environment __ 112

<i>Thi Thanh Van Nguyen, Manh Duong Phung, Anh Viet Dang, Dinh Tuan Pham, Quang Vinh Tran </i>

Indoor Objects Localization System Using Passive UHF – RFID Technology ___________________ 118

<i>Thi Hao Dao, Quoc Cuong Nguyen, Minh Thuy Le </i>

Numerical Analysis of Square/Hexagonal Photonic Crystal Fiber for Optical Fiber Communication __ 123

<i>Nguyen Hoang Hai, Nguyen Ngoc Minh </i>

Antenna for RFID Cards _____________________________________________________________ 130

<i>Nguyen Minh Tran, Tran Quang Nhuong, Truong Vu Bang Giang, Tran Minh Tuan </i>

A Novel Demultiplexer Based on a 2×2 Butterfly MMI Coupler and a Directional Coupler Using Silicon Waveguides _________________________________________________________________ 134

<i>Cao Dung Truong, Xuan Linh Bui, Duc Han Tran, Tuan Linh Nguyen, Trung Thanh Le </i>

Designing Wideband Microstrip Bandpass Filter for Satellite Receiver Systems _________________ 140

<i>Tran Van Hoi, Bach Gia Duong </i>

Đề xuất một cấu trúc anten tiểu hình cho thiết bị di động 3G _________________________________ 144

<i>Hà Quốc Anh, Nguyễn Quốc Định, Hồng Đình Thun </i>

Low Power Wideband CMOS LNA for Digital TV Tuner ___________________________________ 148

<i>Phat Nguyen-Tan, Cuong Huynh </i>

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iv

Simultaneous correction of random and burst errors using norm syndrome for BCH codes _________ 154

<i>Pham Khac Hoan, Le Van Thai, Vu Son Ha </i>

Implementation of Chaotic Pulse Width-Postion Modulation/Demodulation on PIC Microcontroller _ 159

<i>Nguyen Xuan Quyen, Vu Van Yem </i>

Performance of Cooperative Spectrum Sensing over Nakagami channel ________________________ 164

<i>Viet Duc Tran, Hoang Nguyen Van, Mai Dinh Thai </i>

An tồn mạng điều hành giám sát cơng nghiệp ____________________________________________ 170

<i>Nguyễn Đào Trường, Lê Mỹ Tú, Nguyễn Ngọc Điệp </i>

Performance Evaluation of Underlay Cooperative Cognitive Networks over Fading Channels ______ 175

<i>Khuong Ho-Van, Tuan Dang Anh, Hung Dinh Quoc </i>

Collaborative Relay Beamforming in Two-Way Relay Networks _____________________________ 181

<i>Ha H. Kha, Nguyen D. Chi </i>

Về một phương pháp đánh giá thuật tốn tính RTT trong TCP theo phương pháp hàm thống kê _____ 187

<i>Vũ Tất Thành, Nguyễn Hồng Vũ </i>

Đề xuất anten MIMO băng thông siêu rộng ______________________________________________ 192

<i>Lê Trọng Trung, Nguyễn Quốc Định </i>

Một phương pháp xấp xỉ trên miền thời gian cho xung sóng khúc xạ, tán xạ trên mặt phẳng điện môi _ 196

<i>Đinh Trọng Quang, Trịnh Xuân Thọ, Phạm Hữu Lập, Trần Văn Hà, Nguyễn Minh Thắng, Phạm Tiến Mạnh, Lê Vĩnh Hà </i>

Phương pháp tính tốn diện tích tấm tản nhiệt cho vi mạch khuếch đại công suất _________________ 201

<i>Lê Đại Phong, Phạm Việt Anh, Nguy ễn Quang Huy, Phạm Cao Đại </i>

Thiết kế và mô phỏng lưu lượng kế siêu âm đa tần _________________________________________ 205

<i>Ngô Văn Sỹ, Hồ Anh Trang, Phạm Phan Tuyết Lê </i>

The Design of Integrated Transceiver module for Wireless Data Communication ________________ 210

<i>Nguyen Quang Huy, Luu Van Tuan, Le Dai Phong, Bui Quy Thang, Pham Viet Anh </i>

Enhancing Performance of Digitized Radio over Fiber System using Optically Amplified Coherent Receiver __________________________________________________________________________ 214

<i>Tuan Nguyen Van, Thanh-Tung Ton-That </i>

Cân bằng nhanh bằng NƠRON ________________________________________________________ 220

<i>Nguyễn Hoàng Linh, Lê Danh Cường, Trần Nam Trung </i>

Sự tương đương giữa mã Cyclic cục bộ xây dựng trên nhóm nhân Cyclic và mã Cyclic truyền thống _ 225

<i>Nguyễn Văn Trung, Nguyễn Trung Hiếu, Phạm Việt Trung </i>

Microstrip Antenna for WLAN Applications _____________________________________________ 231

<i>Pham Dinh Toai, Ta Dinh Duc, Truong Vu Bang Giang </i>

Nghiên cứu đề xuất thuật toán so khớp bản đồ sử dụng cho ngành đường sắt ____________________ 234

<i>Nguyễn Văn Nghĩa, Đỗ Việt Dũng </i>

Cải thiện chất lượng giải mã LDPC dựa trên ma trận kiểm tra tương đương và cực tiểu trọng số của syndrome _________________________________________________________________________ 237

<i>Nguyễn Văn Duẫn, Đỗ Quốc Trinh, Nguyễn Tùng Hưng </i>

DPA, Một dạng tấn công SILECHANNEL hiệu quả _______________________________________ 243

<i>Nguyễn Hồng Quang </i>

Ứng dụng công nghệ mới trong kỹ thuật chiếu sáng tàu thủy _________________________________ 246

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<i>Trần Xuân Việt </i>

Xây dựng cơng thức tính độ nhạy trong thiết kế cảm biến đo áp suất buồng đốt động cơ tên lửa _____ 250

<i>Lê Vĩnh Hà, Phạm Quang Minh </i>

Áp dụng lý thuyết trò chơi vào hệ thống 5G sử dụng MIMO kích thước lớn đa người dùng _________ 254

<i>Trần Cao Quyền, Phạm Ngọc Linh </i>

Giải pháp nhận dạng kênh vệ tinh phi tuyến sử dụng mạng nơron _____________________________ 258

<i>Nguyễn Viết Minh, Trần Hồng Quân, Lê Nhật Thăng </i>

Improve energy efficiency in WSN using fuzzy logic ______________________________________ 266

<i>Ngo Van Truc, Nguyen Van Cuong </i>

A 355W class S band compact Wilkinson combiner unit with LDMOS FET power amplifiers for wireless power transmission __________________________________________________________ 272

<i>Chuc Doan Huu, Duong Bach Gia </i>

Nghiên cứu ứng dụng cơng nghệ truyền hình lai ghép băng rộng và quảng bá HbbTV _____________ 277

<i>Trần Nam Trung, Đinh Văn Phong </i>

Công cụ hỗ trợ phân tích và thiết kế tế bào nhớ SRAM _____________________________________ 285

<i>Võ Thanh Trí, Lê Bình Sơn, Bùi Trọng Tú </i>

Một số tấn cơng giao thức trao đổi khóa _________________________________________________ 290

<i>Nguyễn Ngọc Điệp, Nguyễn Quốc Toàn, Nguyễn Đào Trường </i>

Hệ thống thu thập dữ liệu quan trắc qua mạng 3G phục vụ công tác cảnh báo lũ _________________ 295

<i>Nguyễn Văn Đức, Đỗ Trọng Tuấn, Phạm Quốc Việt, Lê Văn Điểm </i>

Implementation of Mobile Vehicle Monitoring System using Android Smartphone _______________ 301

<i>Pham Tien Hung, Hoang Van Dung, Vuong Xuan Hong, Ha Duyen Trung </i>

Multi-GNSS positioning campaign in South-East Asia _____________________________________ 307

<i>Tung Hai Ta, Duc Minh Truong, Tu Thanh Thi Nguyen, Thuan Dinh Nguyen, Hieu Trung Tran, Gustavo Belforte </i>

Novel MIMO Antenna Using CRLH Structure ____________________________________________ 314

<i>Nguyen Ngoc Lan, Ho Manh Cuong, Nguyen Van Duc, Vu Van Yem </i>

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National Conference on Electronics and Communications (REV2013-KC01)

System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder

Hai-Phong Phan, Hung K. Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran

SIS Laboratory, VNU University of Engineering and Technology 144 Xuan Thuy road, Hanoi, Vietnam

Corresponding author’s email:

Abstract— This paper presents an implementation of a LEON3-based System-on-Chip (SoC) testbed, which is aimed at experimentally evaluating and validating the H.264/AVC video encoding Integrated Circuit (IC) developed by SIS Laboratory at VNU University of Engineering and Technology. In addition, the paper also presents a methodology for verifying the design of H264/AVC video encoder in the Hardware/Software co-emulating fashion. The design is implemented on the DE2 development board from Altera Corporation. The testbed can help us to evaluate effectively many aspects of the developed H.264/AVC video encoder.

Keywords— SoC testbed, Harware/Software co-verification, LEON3 processor, H.264 encoder

I. I<small>NTRODUCTION</small>

Because of the high mask set cost for fabricating ASIC (Application-specific Integrated Circuit), it is necessary to verify and evaluate carefully the design at all design phases in order to ensure the fabricated chip is without bug. Prototyping an ASIC design, which has large integration level and high complexity, using FPGA (Field Programmable Gate Array) is indispensable in the design process.

ASIC design is more and more complex. The major challenge the designer must be confronted to design such an IC (Integrated Circuit) is verification. In general, verification consumes at least 50%~80% of the design effort [1]. Verifying the design correctness is considered to be the key barrier against designing more complex VLSIs (Very Large Scale Integration), as well as exploiting leading-edge process technologies. There is not any single design tool that can solve the problem. Instead, a complex chain of tools and techniques, including classical simulation, directed and random verification, and formal techniques, etc., is required to reduce the number of design errors to an acceptable minimum. In this paper, we developed a LEON3-based System-on-Chip (SoC) testbed and the platform-based verification method, which is aimed at experimentally evaluating and validating the H.264/AVC video encoding IC designed by SIS Laboratory at the University of Engineering and Technology, Vietnam National University, Hanoi. This testbed can help us to evaluate effectively many aspects of the designed H.264/AVC video encoder.

The goal of verification is to ensure that the design meets the functional requirements as defined in the functional specification. In the top-down method for ASIC design and verification, the designers first develops a system-level model of the design from the functional specification. The system-level model is normally the high-level behavioral abstraction that is written in a high-level programming language such asC/C++. Alternatively, this model may also be created using the hardware description language (HDL) such as Verilog or VHDL. The behavioral model should be simulated in order to verify that it meets the required functionalities completely and correctly. The behavioral model is then used as a reference to refine and create a synthesizable RTL (Register Transfer Level) model.

Before being synthesized to a structural model (or level model), the RTL model is verified again to ensure that it exactly provides the required functionality and performance. The functional verification of the design at this step must be as complete and thorough as possible. This requires that the test vectors employed during simulation should provide the necessary coverage to ensure the design will meet specifications without bug. Unfortunately, the verification by simulation is difficult to test all cases. While the size of design increases, it might be unfeasible to run the full test-bench on a RTL model because of the huge simulating time. In this case, it is necessary to speed up the simulation using emulator, rapid prototype system, or hardware accelerators or to partition the design into several functional blocks. The modules are extracted from an abstract model of the design, and then individual modules can be verified independently with their associated test-bench. Afterwards, system-level emulation can run in a mixed mode where most modules are simulated with high-level abstract models, while one or some modules are substituted by hardware accelerator(s).

gate-The rest of the paper is organized as follows. gate-The hardware architecture of H.264/AVC video encoder is firstly introduced in Section II. Next, the design and implementation of the SoC testbed are presented in Section III. Section IV presents the methodology for verifying a hardware design by using the proposed SoC testbed. The details of validating the H.264/AVC video encoder and experimental results are presented and discussed in Section V. In Section VI, some conclusions are drawn.

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National Conference on Electronics and Communications (REV2013-KC01)

A. Basic concepts of H.264/AVC video encoding

The H.264/AVC video encoding standard is known as an efficient video encoding standard providing high quality at a very low bitrate in comparison with the previous standards such as MPEG-2 and MPEG-4.

The general architecture of the H.264/AVC encoder, composed of different functional blocks, is depicted in Fig. 1.

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<small>Fig. 1 Functional diagram of the H.264/AVC encoder. </small>

In order to achieve high compression ratio, the H.264/AVC standard has adopted several advances in coding technology to remove spatial and temporal redundancies. These prominent techniques are as follows:

• A new way to handle the quantized transform coefficients has been proposed for trading-off between compression performance and video quality to meet the requirements of applications. Besides that, an efficient method called Context-Adaptive Variable Length Coding (CAVLC) is also used to encode residual data. In this coding technique, VLC tables are switched according to already transmitted syntax elements. Since these VLC tables are specifically designed to match the corresponding image statistic, the entropy coding performance is impressively improved in comparison with schemes using only a single VLC table [2]; • The H.264/AVC adopts variable block size prediction

to provide more flexibility. The intra prediction can be applied either on 4×4 blocks individually or on entire 16×16 macroblocks (MBs). There are nine different prediction modes for 4×4 blocks and four prediction modes for 16×16 blocks. After comparing among the cost functions of all possible modes, the best mode having the lowest cost is selected. On the other hand, the inter-prediction is based on a tree-structure where the motion vector and prediction can adopt various block sizes and partitions ranging from 16×16 MBs to 4×4-blocks. To identify these prediction modes, motion vectors, and partitions, the H.264/AVC specifies a very complex algorithm to derive them from their neighbors; • The forward transform/inverse transform also operate

on blocks of 4×4 pixels to match the smallest block size. The transform is still Discrete Cosine Transform

(DCT) but with some fundamental differences compared to those in previous standards [3]. In [4], the transform unit is composed of both DCT and Walsh Hadamard transforms for all prediction processes; • The in-loop de-blocking filter in the H.264/AVC

depends on the parameters so-called Boundary Strength (BS) to determine whether the current block edge should be filtered. The derivation of the BS is highly adaptive because it relies on the modes and coding conditions of the adjacent blocks.

B. VENGME Hardware Architecture

The “Video Encoder for the Next Generation Multimedia Equipment (VENGME)” project, supported by the Vietnam National University, Hanoi, aims at designing and implementing an H.264/AVC encoder targeting mobile platforms. The current design is optimized for CIF video; however, the architecture can be extended for larger resolutions by enlarging the reference memory and the search window.

One of the factors which affect both computational path and the power consumption is the workload of the system and the data dependencies among the pipeline stages. In the H.264/AVC encoder, the most time consuming part is inter prediction including Integer Motion Estimation (IME),

Compensation (MC). The second time consuming module in the encoder is the Entropy Coding (EC). Therefore, the architecture should be carefully selected to improve the coding throughput and the overall performance. Our proposed designs for Intra-Prediction, Inter-Prediction, Entropy Encoder, and Forward Transformation and Quantization (FTQ) have been presented in [4]-[8].

<small>Fig. 2 VENGME H.264/AVC encoder architecture. </small>

The complete architecture of VENGME encoder uses a stage pipeline scheme, as illustrated in Fig. 2. The first stage is used to load the data needed for the prediction. The second stage includes intra- and inter-predictions. Because FME and MC can reuse the information from IME and the data from the search window SRAM, therefore the IME and FME are merged into the same stage. Inter-prediction and intra-prediction in the same stage can be executed in parallel or separately, thanks to the system controller decision. In the

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