Mobile Yonah uFCPGA with Intel pps

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Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Cover Sheet
Custom
147Tuesday, March 20, 2007

2006/10/26 2006/07/26
Compal Electronics, Inc.
REV:0.5
Mobile Yonah uFCPGA with Intel
Calistoga_GM+ ICH7-M core logic
Schematics Document
2007-03-20
Compal confidential
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A
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B
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Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Block Diagram
Custom
247Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Power On/Off CKT.
File Name : LA-3491P
LPC BUS
Compal confidential
PCBGA 1466
page 22
H_A#(3 31)
page 29
BANK 0, 1, 2, 3
USB Conn x2
533/667MHz
DMI
DC/DC Interface CKT.
Mobile Yonah/Merom
USB2.0
FSB
Clock Generator
ICS9LP306BGLFT
Power Circuit DC/DC

IDE ODD Connector
PCI BUS
uFCPGA-478 CPU
page 31
DDR2-SO-DIMM X2
page 33
Intel Calistoga MCH
page 4page 4,5,6
RTC CKT.
page 15
DDR2 -400/533/667
mBGA-652
page 34
page 4
page 7,8,9,10,11,12
Intel ICH7-M
Thermal Sensor
ADM1032AR
page 13,14
page 18,19,20,21
Power OK CKT.
page 19
Fan Control
Dual Channel
Touch Pad CONN.
Int.KBD
SMSC KBC 1070
page 30
page 30page 32
Page 37 3

、
83940
、、
PCI-E BUS
page 31
LED
SPI
25LF080A
SPI ROM
page 31
H_D#(0 63)
Volga 2.0
AC-LINK/Azalia
page 22
SATA HDD Connector
PATA Slave
page 25
Mini-Card
WLAN
945GM
SATA
page 26
CX20549-12
Audio Conexant
page 27
MODEM AMOM
page 28
AMP & Audio Jack
TPA6017A2
CX20548

page 16
CRT
page 17
LVDS Conn
CardBus Controller
CB-1410
page 24
Slot 0
page 24
page 23
page 23
82562V 10 /100
RJ45/11 CONN
INTEL LAN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev

Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Notes List
347Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
IDSEL #
2
1 0 1 0 0 1 0 0A4
I2C / SMBUS ADDRESSING
C
1 0 1 0 0 0 0 0
D2
CARD BUS
A0
CLOCK GENERATOR (EXT.)
HEX
DDR SO-DIMM 1
D6
ADDRESS

PCI Device ID
DDR SO-DIMM 0
DEVICE
1 1 0 1 0 0 1 0
External PCI Devices
REQ/GNT #
DEVICE
AD22
PIRQ
Voltage Rails
Symbol Note :
: means Digital Ground
: means Analog Ground
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
CONN@ : means ME parts
LP@ : means just build when Low power clock gen. install
NOXDP@ : means just build when XDP function disable.
BATT@ : means need be mounted when 45 level assy or rework stage.
45@ : means need be mounted when 45 level assy or rework stage.
Debug@ : means Mini debug card use
ICH7 R1 SA00000V1F0
ICH7 R3 SA00000V1A0
Calistoga 940GML R3 SA000011C10
Calistoga 945GM R3 SA0000059L0
Calistoga 945GM R1 SA0000059A0
Calistoga 940GML R1 SA000011C00
14@ : means need be mounted when 14.1"
IAT50 945GM FF 46147932L01
IAT50 940GML DF 46147932L02
IAT60 945GM FF 46147932L21

IAT60 940GML DF 46147932L22
VIN
OF F
Power Plane
N/AN/A
ON
AC or battery power rail for power circuit
+CPU_CORE
+0.9V
S3
+1.5VS
OF F
+VCCP
N/A
ON
0.9V switched power rail for DDRII Vtt
S0-S1
ON OFF
ON
N/A
N/A
OF F
Description
1.05V power rail for Processor I/O and MCH/ICH core power
Adapter power supply (18.5V)
N/A
OF F
OF F
Core voltage for CPU
OF FOF F

S5
1.5V switched power rail for PCI-E interface
B+
OF F2.5V switched power rail for MCH video PLL
5V always on power rail
ON
3.3V always on power rail
3.3V switched power rail+3VS
ON*
RTC power ONON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+1.8V
OF F
OF F
ON
ON
+3VALW
OF F
ON
5V switched power rail
ON
+2.5VS
+RTC_VCC
+5VS
ON
ON
ON OFF
+5VALW
ON
1.8V power rail for DDRII

ON*
ON OFF OFF
IAT50 940GML DF 46147932L03 (No WLAN)
IAT60 940GML DF 46147932L23 (No WLAN)
WLAN@ : means need be mounted when have wireless LED Function
WLAN14@ : means need be mounted when have wireless LED Function and 14"
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_A#28
H_THERMDA
H_FERR#
H_ADSTB#0
H_A#23
H_REQ#2
H_A#31
H_REQ#0
H_A#17
H_BNR#

H_A#29
H_DSTBP#0
H_A#8
H_DEFER#
H_REQ#1
H_A#3
H_RS#0
H_DSTBN#1
H_A#6
XDP_BPM#2
H_BPRI#
H_ADS#
H_A#25
XDP_BPM#3
H_RS#1
H_DSTBP#1
H_A#4
H_IERR#
H_HITM#
H_DSTBN#0
H_INTR
H_DSTBN#2
H_A#22
H_A#7
H_REQ#4
XDP_DBRESET#
H_DRDY#
H_A#15
H_A#14
H_A20M#

H_DINV#0
H_DSTBP#2
H_DINV#2
H_DINV#3
H_DINV#1
H_DSTBN#3
H_DSTBP#3
H_NMI
H_A#30
H_A#27
H_A#18
H_A#10
H_BR0#
H_LOCK#
H_A#11
H_A#21
H_A#26
H_A#13
H_A#9
XDP_BPM#0
H_DPSLP#
H_A#20
H_A#16
H_A#12
H_HIT#
H_ADSTB#1
H_THERMTRIP#
H_DBSY#
H_A#19
H_A#24

H_A#5
H_RS#2
H_RESET#
XDP_BPM#1
H_REQ#3
H_SMI#
H_STPCLK#
XDP_TCK
XDP_TRST#
XDP_TMS
H_CPUSLP#
XDP_TDO
XDP_TDI
H_PWRGOOD
XDP_BPM#5
H_DPRSTP#
H_TRDY#
CLK_CPU_BCLK
CLK_CPU_BCLK#
ICH_SMBCLK
ICH_SMBDATA
H_THERMDA
H_THERMDC
THERM#
ICH_SMBDATA
ICH_SMBCLK
THERM#
H_THERMDC
XDP_BPM#4
H_DPWR#

TEST1
TEST2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#7
H_D#6
H_D#4
H_D#5
H_D#11
H_D#10
H_D#8
H_D#9
H_D#15
H_D#14
H_D#12
H_D#13
H_D#19
H_D#18
H_D#16
H_D#17
H_D#23
H_D#22
H_D#20
H_D#21
H_D#27
H_D#26
H_D#24
H_D#25

H_D#31
H_D#30
H_D#28
H_D#29
H_D#35
H_D#34
H_D#32
H_D#33
H_D#39
H_D#38
H_D#36
H_D#37
H_D#43
H_D#42
H_D#40
H_D#41
H_D#47
H_D#46
H_D#44
H_D#45
H_D#51
H_D#50
H_D#48
H_D#49
H_D#55
H_D#54
H_D#52
H_D#53
H_D#59
H_D#58

H_D#56
H_D#57
H_D#63
H_D#62
H_D#60
H_D#61
H_INIT#
H_IGNNE#
H_PROCHOT#
H_PROCHOT# OCP#
H_DPSLP#
H_DPRSTP#
XDP_HOOK1
XDP_HOOK1
XDP_BPM#3
XDP_DBRESET#_R
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_PRE
XDP_DBRESET#XDP_DBRESET#_R
XDP_TDI
XDP_TMS
XDP_TCK
XDP_TRST#
XDP_TCK
XDP_TDO
H_RESET#
XDP_TRST#
XDP_TMS

XDP_TDO
XDP_TDI
H_PWRGOOD_R
H_RESET#_R
XDP_BPM#5
CLK_CPU_XDP#
CLK_CPU_XDP
XDP_BPM#4
XDP_BPM#5
FAN
THERM_SCI#
H_PWRGOOD
ICH_SMBDATA<13,14,15,20,25>
ICH_SMBCLK<13,14,15,20,25>
THERM_SCI# <20>
FAN_PWM<30>
H_D#[0 63] <7>
H_A#[3 31]<7>
H_REQ#[0 4]<7>
H_ADSTB#0<7>
H_ADSTB#1<7>
CLK_CPU_BCLK#<15>
CLK_CPU_BCLK<15>
H_ADS#<7>
H_BNR#<7>
H_BR0#<7>
H_DRDY#<7>
H_HIT#<7>
H_HITM#<7>
H_BPRI#<7>

H_DEFER#<7>
H_LOCK#<7>
H_RESET#<7>
H_RS#[0 2]<7>
H_TRDY#<7>
H_DBSY#<7>
H_DPSLP#<19>
H_DPRSTP#<19,40>
H_DPWR#<7>
H_CPUSLP#<7>
H_THERMTRIP#<7,19>
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_DSTBN#[0 3] <7>
H_DSTBP#[0 3] <7>
H_A20M# <19>
H_FERR# <19>
H_IGNNE# <19>
H_INIT# <19>
H_INTR <19>
H_NMI <19>
H_STPCLK# <19>
H_SMI# <19>
XDP_DBRESET#<20>
H_PROCHOT#<40>
OCP# <20,30,42>
H_PWRGOOD<19>
CLK_CPU_XDP <15>

CLK_CPU_XDP# <15>
+VCCP
+3VS
+3VS
+5VS
+3VS
+VCCP
+VCCP
+3VS
+VCCP+VCCP
+VCCP
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Yonah CPU in mFCPGA479
447Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil
Thermal Sensor ADM1032AR-2
Address:1001_101
PWM Fan Control circuit
Place R2203 within 200ps (~1") to CPU
Change to same as
Chimay 4/6
This shall place near CPU
ITP-XDP Connector
Change value in 5/02
Removed at 5/30.(Follow
Chimay)
Follow datasheet 12/05
S
G
D
Q1
AO6402_TSOP6
3
6
2
4 5
1
R2201 1K_0402_1%
XDP@
1 2
JP3
ACES_85205-0200
CONN@
1

2
U1
ADM1032AR-2_MSOP8
VDD
1
ALERT#
6
THERM#
4
GND
5
D+
2
D-
3
SCLK
8
SDATA
7
R2199 54.9_0402_1%@
1 2
C1455
0.1U_0402_16V7K
XDP@
12
ZD1
RLZ5.1B_LL34
@
12
R12

56_0402_5%

1 2
R2202 200_0402_1%
XDP@
12
R2203
0_0402_5%
XDP@
1 2
R15
56_0402_5%

1 2
ADDR GROUP
CONTROL
HOST CLK
MISC
DATA GROUP
THERMAL
DIODE
LEGACY CPU
YONAH
JP1A
FOX_PZ47903-2741-42_YONAH
CONN@
A3#
J4
A4#
L4

A5#
M3
A6#
K5
A7#
M1
A8#
N2
A9#
J1
A10#
N3
A11#
P5
A12#
P2
A13#
L1
A14#
P4
A15#
P1
A16#
R1
A17#
Y2
A18#
U5
A19#
R3

A20#
W6
A21#
U4
A22#
Y5
A23#
U2
A24#
R4
A25#
T5
A26#
T3
A27#
W3
A28#
W5
A29#
Y4
A30#
W2
A31#
Y1
REQ0#
K3
REQ1#
H2
REQ2#
K2

REQ3#
J3
REQ4#
L5
ADSTB0#
L2
ADSTB1#
V4
BCLK0
A22
BCLK1
A21
ADS#
H1
BNR#
E2
BPRI#
G5
BR0#
F1
DEFER#
H5
DRDY#
F21
HIT#
G6
HITM#
E4
IERR#
D20

LOCK#
H4
RESET#
B1
RS0#
F3
RS1#
F4
RS2#
G3
TRDY#
G2
BPM0#
AD4
BPM1#
AD3
BPM2#
AD1
BPM3#
AC4
DBR#
C20
DBSY#
E1
DPSLP#
B5
DPWR#
D24
PRDY#
AC2

PREQ#
AC1
PROCHOT#
D21
PWRGOOD
D6
SLP#
D7
TCK
AC5
TDI
AA6
TDO
AB3
TEST1
C26
TEST2
D25
TMS
AB5
TRST#
AB6
THERMDA
A24
THERMDC
A25
THERMTRIP#
C7
D0#
E22

D1#
F24
D2#
E26
D3#
H22
D4#
F23
D5#
G25
D6#
E25
D7#
E23
D8#
K24
D9#
G24
D10#
J24
D11#
J23
D12#
H26
D13#
F26
D14#
K22
D15#
H25

D16#
N22
D17#
K25
D18#
P26
D19#
R23
D20#
L25
D21#
L22
D22#
L23
D23#
M23
D24#
P25
D25#
P22
D26#
P23
D27#
T24
D28#
R24
D29#
L26
D30#
T25

D31#
N24
D32#
AA23
D33#
AB24
D34#
V24
D35#
V26
D36#
W25
D37#
U23
D38#
U25
D39#
U22
D40#
AB25
D41#
W22
D42#
Y23
D43#
AA26
D44#
Y26
D45#
Y22

D46#
AC26
D47#
AA24
D48#
AC22
D49#
AC23
D50#
AB22
D51#
AA21
D52#
AB21
D53#
AC25
D54#
AD20
D55#
AE22
D56#
AF23
D57#
AD24
D58#
AE21
D59#
AD21
D60#
AE25

D61#
AF25
D62#
AF22
D63#
AF26
DINV0#
J26
DINV1#
M26
DINV2#
V23
DINV3#
AC20
DSTBN0#
H23
DSTBN1#
M24
DSTBN2#
W24
DSTBN3#
AD23
DSTBP0#
G22
DSTBP1#
N25
DSTBP2#
Y25
DSTBP3#
AE24

A20M#
A6
FERR#
A5
IGNNE#
C4
INIT#
B3
LINT0
C6
LINT1
B4
STPCLK#
D5
SMI#
A3
DPRSTP#
E5
R16 1K_0402_5%@
1 2
R20
56_0402_5%@
1 2
R5 54.9_0402_1%
1 2
D1
CH751H-40_SC76

2 1
U2

TC7SH00FU_SSOP5
INB
1
INA
2
O
4
G
3
P
5
C5
0.1U_0402_16V4Z
1
2
R18
56_0402_5%@
12
E
B
C
Q2
MMBT3904_SOT23@
2
3 1
R13
10K_0402_5%
12
C2
0.1U_0402_16V4Z

1
2
R6 51_0402_1%

1 2
R3 54.9_0402_1%
1 2
R2 54.9_0402_1%
1 2
R10
1K_0402_5%@
1 2
C4
4.7U_0805_10V4Z
1
2
R14
10K_0402_5%
1 2
R4 54.9_0402_1%
1 2
R19
56_0402_5%@
1 2
R7 54.9_0402_1%
1 2
C3
2200P_0402_50V7K
1 2
R17 51_0402_5%

12
JP29
SAMTE_BSH-030-01-L-D-ACONN@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25

OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55

TCK0
57
GND16
59
GND1
2
OBSFN_C0
4
OBSFN_C1
6
GND3
8
OBSDATA_C0
10
OBSDATA_C1
12
GND5
14
OBSDATA_C2
16
OBSDATA_C3
18
GND7
20
OBSFN_D0
22
OBSFN_D1
24
GND9
26

OBSDATA_D0
28
OBSDATA_D1
30
GND11
32
OBSDATA_D2
34
OBSDATA_D3
36
GND13
38
ITPCLK/HOOK4
40
ITPCLK#/HOOK5
42
VCC_OBS_CD
44
RESET#/HOOK6
46
DBR#/HOOK7
48
GND15
50
TD0
52
TRST#
54
TDI
56

TMS
58
GND17
60
R2200
1K_0402_5%
XDP@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COMP3
COMP2
H_PSI#
COMP1
COMP0
CPU_VID1
CPU_VID0
CPU_VID3

CPU_VID4
CPU_VID2
CPU_VID5
CPU_VID6
CPU_BSEL1
CPU_BSEL2
CPU_BSEL0
VSSSENSE
VCCSENSE
VSSSENSE
VCCSENSE
H_PSI#<40>
CPU_VID0<40>
CPU_VID1<40>
CPU_VID2<40>
CPU_VID3<40>
CPU_VID4<40>
CPU_VID5<40>
CPU_VID6<40>
CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>
VCCSENSE<40>
VSSSENSE<40>
+VCCP
+VCC_CORE
+VCCP
V_CPU_GTLREF
V_CPU_GTLREF
+1.5VS

+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Yonah CPU in mFCPGA479
547Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
Close to CPU pin AD26
within 500mils.
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166

00
0
1
CPU_BSEL0
1
1
Length match within 25 mils
The trace width 18 mils space
7 mils
Close to CPU pin
within 500mils.
POWER, GROUNG, RESERVED SIGNALS AND NC
YONAH
JP1B
FOX_PZ47903-2741-42_YONAH
CONN@
PSI#
AE6
GTLREF
AD26
VCCSENSE
AF7
VCCA
B26
VCC
AB20
VCC
AA20
VCC
AF20

VCC
AE20
VCC
AB18
VCC
AB17
VCC
AA18
VCC
AA17
VCC
AD18
VCC
AD17
VCC
AC18
VCC
AC17
VCC
AF18
VCC
AF17
RSVD
T22
RSVD
V3
RSVD
B2
RSVD
C3

VSS
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19

VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14

VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6

VSS
AF6
VSS
AB4
VSS
AC3
VSS
AF3
VSS
AE4
VSS
AB1
VSS
AA2
VSS
AD2
VSS
AE1
VSS
B6
VSS
C5
VSS
F5
VSS
E6
VSS
H6
VSS
J5

VSS
M5
VSS
L6
VSS
P6
VSS
R5
VSS
V5
VSS
U6
VSS
Y6
VSS
A4
VSS
D4
VSS
E3
VSS
H3
VSS
G4
VSS
K4
VSS
L3
VSS
P3

VSS
N4
VSS
T4
VSS
U3
VSS
Y3
VSS
W4
VSS
D1
VSS
C2
VSS
F2
VSS
G1
RSVD
B25
VSSSENSE
AE7
VCCP
K6
VCCP
J6
VCCP
M6
VCCP
N6

VCCP
T6
VCCP
R6
VCCP
K21
VCCP
J21
VCCP
M21
VCCP
N21
VCCP
T21
VCCP
R21
VCCP
V21
VCCP
W21
VCCP
V6
VCCP
G21
VID0
AD6
VID1
AF5
VID2
AE5

VID3
AF4
VID4
AE3
VID5
AF2
VID6
AE2
BSEL0
B22
BSEL1
B23
BSEL2
C21
COMP0
R26
COMP1
U26
COMP2
U1
COMP3
V1
RSVD
C23
RSVD
C24
RSVD
AA1
RSVD
AA4

RSVD
AB2
RSVD
AA3
RSVD
M4
RSVD
N5
RSVD
T2
RSVD
D2
RSVD
F6
RSVD
D3
RSVD
C1
RSVD
AF1
RSVD
D22
VCC
E7
R24
2K_0402_1%

12
R28
54.9_0402_1%

12
C6
0.01U_0402_16V7K

1
2
R25
27.4_0402_1%

12
R21
1K_0402_1%

12
POWER, GROUND
YONAH
JP1C
FOX_PZ47903-2741-42_YONAH
CONN@
VCC
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15

VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12

VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7

VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17

VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VSS
K1
VSS
J2
VSS
M2
VSS
N1
VSS
T1
VSS
R2
VSS
V2

VSS
W1
VSS
A26
VSS
D26
VSS
C25
VSS
F25
VSS
B24
VSS
A23
VSS
D23
VSS
E24
VSS
B21
VSS
C22
VSS
F22
VSS
E21
VSS
B19
VSS
A19

VSS
D19
VSS
C19
VSS
F19
VSS
E19
VSS
B16
VSS
A16
VSS
D16
VSS
C16
VSS
F16
VSS
E16
VSS
B13
VSS
A14
VSS
D13
VSS
C14
VSS
F13

VSS
E14
VSS
B11
VSS
A11
VSS
D11
VSS
C11
VSS
F11
VSS
E11
VSS
B8
VSS
A8
VSS
D8
VSS
C8
VSS
F8
VSS
E8
VSS
G26
VSS
K26

VSS
J25
VSS
M25
VSS
N26
VSS
T26
VSS
R25
VSS
V25
VSS
W26
VSS
H24
VSS
G23
VSS
K23
VSS
L24
VSS
P24
VSS
N23
VSS
T23
VSS
U24

VSS
Y24
VSS
W23
VSS
H21
VSS
J22
VSS
M22
VSS
L21
VSS
P21
VSS
R22
VSS
V22
VSS
U21
VSS
Y21
VCC
B14
VCC
A13
VCC
D14
VCC
C13

VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10

VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
F7
VCC
A7
R27
27.4_0402_1%

12
R23
100_0402_1%
1 2
R26
54.9_0402_1%

12
C7
10U_0805_10V4Z

1
2
R22
100_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet
of
Security Classification

Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
CPU Bypass capacitors
647Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Mid Frequence Decoupling
ESR <= 1.5m ohm
Capacitor > 1980uF
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
Place these capacitors on L8
(North side,Secondary Layer)
02/26 Change C43 C44 C45 to
、、
1.9mm height for PV build short
term solution
C19
10U_0805_6.3V6M

1
2
+
C42
330U_D2E_2.5VM_R7
1
2
C32
10U_0805_6.3V6M
1
2
C24
10U_0805_6.3V6M
1
2
C27
10U_0805_6.3V6M
1
2
C8
10U_0805_6.3V6M
1
2
C22
10U_0805_6.3V6M
1
2
C26
10U_0805_6.3V6M
1

2
C16
10U_0805_6.3V6M
1
2
+
C40
330U_D2E_2.5VM_R7
1
2
C52
0.1U_0402_10V6K
1
2
C11
10U_0805_6.3V6M
1
2
C49
0.1U_0402_10V6K
1
2
C35
10U_0805_6.3V6M
1
2
C9
10U_0805_6.3V6M
1
2

+
C47
330U_D2E_2.5VM_R9
1
2
C18
10U_0805_6.3V6M
1
2
C36
10U_0805_6.3V6M
1
2
C10
10U_0805_6.3V6M
1
2
C30
10U_0805_6.3V6M
1
2
C51
0.1U_0402_10V6K
1
2
C17
10U_0805_6.3V6M
1
2
C23

10U_0805_6.3V6M
1
2
C14
10U_0805_6.3V6M
1
2
C53
0.1U_0402_10V6K
1
2
C39
10U_0805_6.3V6M
1
2
C33
10U_0805_6.3V6M
1
2
C20
10U_0805_6.3V6M
1
2
+
C45
330U_D2E_2.5VM_R7
1
2
C50
0.1U_0402_10V6K

1
2
+
C41
330U_D2E_2.5VM_R7@
1
2
C29
10U_0805_6.3V6M
1
2
C15
10U_0805_6.3V6M
1
2
C38
10U_0805_6.3V6M
1
2
C34
10U_0805_6.3V6M
1
2
C13
10U_0805_6.3V6M
1
2
+
C44
330U_D2E_2.5VM_R7

1
2
+
C43
330U_D2E_2.5VM_R7
1
2
C31
10U_0805_6.3V6M
1
2
C12
10U_0805_6.3V6M
1
2
C37
10U_0805_6.3V6M
1
2
C25
10U_0805_6.3V6M
1
2
C28
10U_0805_6.3V6M
1
2
C21
10U_0805_6.3V6M

1
2
C48
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_SWNG0
H_VREF
DDR_THERM#
V_DDR_MCH_REF
M_OCDOCMP1
PM_EXTTS#1
H_RS#0
H_ADSTB#1
H_SWNG1
H_XRCOMP

CFG3
DMI_TXP1
H_REQ#0
CFG7
CFG5
DDR_CKE0_DIMMA
M_CLK_DDR3
DMI_RXN2
H_HIT#
H_DSTBP#0
H_REQ#4
H_SWNG0
CFG15
DDR_CKE1_DIMMA
M_OCDOCMP0
DMI_TXN1
DMI_TXN0
H_BNR#
H_REQ#2
M_ODT1
DMI_TXP2
H_DSTBP#2
CLK_MCH_3GPLL
CFG13
M_CLK_DDR#0
DMI_RXP2
H_REQ#3
CFG9
H_DINV#2
CLK_MCH_BCLK#

H_REQ#1
H_YSCOMP
MCH_CLKSEL0
DDR_CKE3_DIMMB
H_BPRI#
H_DINV#0
CFG18
CFG4
M_CLK_DDR#1
DMI_RXP1
DMI_RXP0
DMI_TXP0
H_CPUSLP#
H_DPWR#
H_ADS#
H_DSTBP#3
H_DSTBN#3
CFG16
DMI_RXN1
M_OCDOCMP0
CLK_MCH_BCLK
PLTRST_R#
CFG19
CFG12
DDR_CS1_DIMMA#
SMRCOMPN
H_DSTBP#1
H_DINV#3
H_RS#2
H_ADSTB#0

CFG17
CFG8
CFG6
DDR_CKE2_DIMMB
DMI_RXN0
H_LOCK#
H_RESET#
M_ODT3
M_OCDOCMP1
M_CLK_DDR#2
DMI_TXP3
DMI_TXN3
H_DBSY#
H_BR0#
H_DSTBN#1
H_DSTBN#0
CFG20
V_DDR_MCH_REF
H_DSTBN#2
H_RS#1
H_XSCOMP
CFG10
MCH_CLKSEL2
DDR_CS0_DIMMA#
SMRCOMPP
M_CLK_DDR#3
CFG11
DDR_CS3_DIMMB#
DMI_RXN3
H_HITM#

H_DRDY#
DDR_CS2_DIMMB#
M_ODT2
M_ODT0
H_DEFER#
H_TRDY#
H_DINV#1
H_THERMTRIP#
CFG14
M_CLK_DDR2
M_CLK_DDR1
M_CLK_DDR0
H_VREF
H_YRCOMP
DMI_TXN2
DMI_RXP3
PM_EXTTS#1
MCH_CLKSEL1
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#11
H_D#13
H_D#9
H_D#14

H_D#8
H_D#15
H_D#12
H_D#10
H_D#19
H_D#21
H_D#17
H_D#22
H_D#16
H_D#23
H_D#20
H_D#18
H_D#27
H_D#29
H_D#25
H_D#30
H_D#24
H_D#31
H_D#28
H_D#26
H_D#35
H_D#37
H_D#33
H_D#38
H_D#32
H_D#39
H_D#36
H_D#34
H_D#43
H_D#45

H_D#41
H_D#46
H_D#40
H_D#47
H_D#44
H_D#42
H_D#51
H_D#53
H_D#49
H_D#54
H_D#48
H_D#52
H_D#50
H_D#55
H_D#59
H_D#61
H_D#57
H_D#62
H_D#56
H_D#63
H_D#60
H_D#58
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#11
H_A#8
H_A#10

H_A#12
H_A#9
H_A#13
H_A#15
H_A#17
H_A#14
H_A#21
H_A#18
H_A#20
H_A#22
H_A#19
H_A#26
H_A#23
H_A#25
H_A#27
H_A#24
H_A#31
H_A#28
H_A#30
H_A#29
H_A#16
CLK_MCH_REF#
CLK_MCH_REF
MCH_SSCDREFCLK#
MCH_SSCDREFCLK
GMCH_H32
PWROK
PWROK
CLKREQC#GMCH_H32
PM_BMBUSY#

DDR_THERM#
H_SWNG1
CLK_MCH_3GPLL#
H_D#[0 63]<4>
H_A#[3 31] <4>
H_REQ#[0 4] <4>
H_ADSTB#1 <4>
H_ADSTB#0 <4>
CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0 3] <4>
H_DSTBP#[0 3] <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>

H_RS#[0 2] <4>
DMI_TXN0<20>
DMI_TXN1<20>
DMI_TXN2<20>
DMI_TXN3<20>
DMI_TXP0<20>
DMI_TXP1<20>
DMI_TXP2<20>
DMI_TXP3<20>
DMI_RXN0<20>
DMI_RXN1<20>
DMI_RXN2<20>
DMI_RXN3<20>
DMI_RXP0<20>
DMI_RXP1<20>
DMI_RXP2<20>
DMI_RXP3<20>
M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>
M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>
DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>
DDR_CKE0_DIMMA<13>

DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>
M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>
PM_BMBUSY#<20>
H_THERMTRIP#<4,19>
PLT_RST#<18,20,22,24,25,30,31>
MCH_ICH_SYNC#<18>
V_DDR_MCH_REF<13,14>
MCH_CLKSEL0 <15>
CFG5 <11>
CFG7 <11>
CFG9 <11>
CFG11 <11>
CFG12 <11>
CFG13 <11>
MCH_CLKSEL2 <15>
MCH_CLKSEL1 <15>
CFG16 <11>
CFG18 <11>
CFG19 <11>
CFG20 <11>
CLK_MCH_3GPLL <15>
VGATE_INTEL<20,40>
PM_POK<20,30>
DPRSLPVR<20,40>
CLKREQC# <15>

CLK_MCH_REF# <15>
CLK_MCH_REF <15>
MCH_SSCDREFCLK# <15>
MCH_SSCDREFCLK <15>
DDR_THERM#<13,14>
CLK_MCH_3GPLL# <15>
+VCCP
+VCCP+VCCP
+VCCP
+3VS
+1.8V
+1.8V
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Calistoga (1/6)
747Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.
Layout Note:
Route as short
as possible
Description at page11.
Stuff R42 & R43 for A1 Calistoga
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.
T5
PAD
R33 0_0402_5%
1 2
R32
54.9_0402_1%

12
R48
100_0402_1%

12
R39
10K_0402_5%

12
R42
40.2_0402_1%
@
12
C54
0.1U_0402_16V4Z

1
2
R51
200_0402_1%

12
R41
100_0402_1%
12
R34 100_0402_1%

12
DMI
DDR MUXING
CFG
PM
CLKNC
RESERVED
U3B
CALISTOGA_FCBGA1466~D
DMIRXN0
AE35

DMIRXN1
AF39
DMIRXN2
AG35
DMIRXN3
AH39
DMIRXP0
AC35
DMIRXP1
AE39
DMIRXP2
AF35
DMIRXP3
AG39
DMITXN0
AE37
DMITXN1
AF41
DMITXN2
AG37
DMITXN3
AH41
DMITXP0
AC37
DMITXP1
AE41
DMITXP2
AF37
DMITXP3
AG41

SM_CK0
AY35
SM_CK1
AR1
SM_CK2
AW7
SM_CK3
AW40
SM_CK0#
AW35
SM_CK1#
AT1
SM_CK2#
AY7
SM_CK3#
AY40
SM_OCDCOMP0
AL20
SM_OCDCOMP1
AF10
SM_ODT0
BA13
SM_ODT1
BA12
SM_ODT2
AY20
SM_ODT3
AU21
SM_RCOMPN
AV9

SM_RCOMPP
AT9
SM_VREF0
AK1
SM_VREF1
AK41
SM_CKE0
AU20
SM_CKE1
AT20
SM_CKE2
BA29
SM_CKE3
AY29
SM_CS0#
AW13
SM_CS1#
AW12
SM_CS2#
AY21
SM_CS3#
AW21
CFG16
G18
CFG1
K18
CFG2
J18
CFG3
F18

CFG4
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG0
K16
CFG17
H15
CFG18
J25

CFG19
K27
CFG20
J26
G_CLKP
AG33
G_CLKN
AF33
D_REF_CLKN
A27
D_REF_CLKP
A26
D_REF_SSCLKN
C40
D_REF_SSCLKP
D41
NC0
A3
NC1
A39
NC2
A4
NC3
A40
NC4
AW1
NC5
AW41
NC6
AY1

NC7
BA1
NC8
BA2
NC9
BA3
NC10
BA39
NC11
BA40
NC12
BA41
NC13
C1
NC14
AY41
NC15
B2
NC16
B41
NC17
C41
NC18
D1
PM_BMBUSY#
G28
PM_EXTTS0#
F25
PM_EXTTS1#
H26

PM_THERMTRIP#
G6
PWROK
AH33
RSTIN#
AH34
RESERVED1
T32
RESERVED2
R32
RESERVED3
F3
RESERVED4
F7
RESERVED5
AG11
RESERVED6
AF11
RESERVED7
H7
RESERVED8
J19
RESERVED9
A41
RESERVED10
A34
RESERVED11
D28
RESERVED12
D27

RESERVED13
A35
ICH_SYNC#
K28
CLK_REQ#
H32
C55
0.1U_0402_16V4Z

1
2
R31
54.9_0402_1%

12
R40
10K_0402_5%@
12
R37
24.9_0402_1%

12
T4
PAD
T3
PAD
R49
100_0402_1%

12

R50
100_0402_1%

12
R36 0_0402_5%
1 2
R46
221_0603_1%

12
C57
0.1U_0402_16V4Z

1
2
R45
100_0402_1%
12
T7
PAD
C56
0.1U_0402_16V4Z

1
2
R43
40.2_0402_1%
@
12
T1

PAD
R29 80.6_0402_1%

1 2
R30 80.6_0402_1%

1 2
R38
24.9_0402_1%

12
T2
PAD
R35 0_0402_5%@
1 2
R47
221_0603_1%

12
T8
PAD
R44
0_0402_5%
1 2
HOST
U3A
CALISTOGA_FCBGA1466~D
HD0#
F1
HD1#

J1
HD2#
H1
HD3#
J6
HD4#
H3
HD5#
K2
HD6#
G1
HD7#
G2
HD8#
K9
HD9#
K1
HD10#
K7
HD11#
J8
HD12#
H4
HD13#
J3
HD14#
K11
HD15#
G4
HD16#

T10
HD17#
W11
HD18#
T3
HD19#
U7
HD20#
U9
HD21#
U11
HD22#
T11
HD23#
W9
HD24#
T1
HD25#
T8
HD26#
T4
HD27#
W7
HD28#
U5
HD29#
T9
HD30#
W6
HD31#

T5
HD32#
AB7
HD33#
AA9
HD34#
W4
HD35#
W3
HD36#
Y3
HD37#
Y7
HD38#
W5
HD39#
Y10
HD40#
AB8
HD41#
W2
HD42#
AA4
HD43#
AA7
HD44#
AA2
HD45#
AA6
HD46#

AA10
HD47#
Y8
HD48#
AA1
HD49#
AB4
HD50#
AC9
HD51#
AB11
HD52#
AC11
HD53#
AB3
HD54#
AC2
HD55#
AD1
HD56#
AD9
HD57#
AC1
HD58#
AD7
HD59#
AC6
HD60#
AB5
HD61#

AD10
HD62#
AD4
HD63#
AC8
HVREF1
K13
HXRCOMP
E1
HXSCOMP
E2
HYRCOMP
Y1
HYSCOMP
U1
HXSWING
E4
HYSWING
W1
HA3#
H9
HA4#
C9
HA5#
E11
HA6#
G11
HA7#
F11
HA8#

G12
HA9#
F9
HA10#
H11
HA11#
J12
HA12#
G14
HA13#
D9
HA14#
J14
HA15#
H13
HA16#
J15
HA17#
F14
HA18#
D12
HA19#
A11
HA20#
C11
HA21#
A12
HA22#
A13
HA23#

E13
HA24#
G13
HA25#
F12
HA26#
B12
HA27#
B14
HA28#
C12
HA29#
A14
HA30#
C14
HA31#
D14
HREQ#0
D8
HREQ#1
G8
HREQ#2
B8
HREQ#3
F8
HREQ#4
A8
HADSTB#0
B9
HADSTB#1

C13
HRS0#
B4
HRS1#
E6
HRS2#
D6
HCLKN
AG1
HCLKP
AG2
HDINV#0
J7
HDINV#1
W8
HDINV#2
U3
HDINV#3
AB10
HDSTBN#0
K4
HDSTBN#1
T7
HDSTBN#2
Y5
HDSTBN#3
AC4
HDSTBP#0
K3
HDSTBP#1

T6
HDSTBP#2
AA5
HDSTBP#3
AC5
HCPURST#
B7
HADS#
E8
HTRDY#
E7
HDPWR#
J9
HDRDY#
H8
HDEFER#
C3
HHITM#
D4
HHIT#
D3
HLOCK#
B3
HBREQ0#
C7
HBNR#
C6
HBPRI#
F6
HDBSY#

A7
HCPUSLP#
E3
HVREF0
J13
T6
PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_D11
DDR_B_D57
DDR_B_D46
DDR_B_D7
DDR_B_D0
DDR_B_D44
DDR_B_D40
DDR_B_D30
DDR_B_D27

DDR_B_D15
DDR_B_D3
DDR_B_D35
DDR_B_D25
DDR_B_D23
DDR_B_D49
DDR_B_D37
DDR_B_D19
DDR_B_D48
DDR_B_D47
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D62
DDR_B_D60
DDR_B_D9
DDR_B_D2
DDR_B_D52
DDR_B_D50
DDR_B_D22
DDR_B_D56
DDR_B_D51
DDR_B_D39
DDR_B_D28
DDR_B_D17
DDR_B_D45
DDR_B_D6
DDR_B_D61
DDR_B_D58
DDR_B_D1

DDR_B_D54
DDR_B_D41
DDR_B_D31
DDR_B_D12
DDR_B_D5
DDR_B_D38
DDR_B_D32
DDR_B_D20
DDR_B_D16
DDR_B_D14
DDR_B_D33
DDR_B_D63
DDR_B_D59
DDR_B_D42
DDR_B_D55
DDR_B_D53
DDR_B_D43
DDR_B_D29
DDR_B_D26
DDR_B_D13
DDR_B_D4
DDR_B_BS#2
DDR_B_D34
DDR_B_D24
DDR_B_D21
DDR_B_D10
DDR_B_WE#
DDR_B_RAS#
DDR_A_D35
DDR_A_D15

DDR_A_D14
DDR_A_D21
DDR_A_BS#2
DDR_A_D28
DDR_A_D11
DDR_A_D7
DDR_A_WE#
DDR_A_D31
DDR_A_D16
DDR_A_D59
DDR_A_D56
DDR_A_D42
DDR_A_D25
DDR_A_D9
DDR_A_D60
DDR_A_D55
DDR_A_D13
DDR_A_D0
DDR_A_D62
DDR_A_D3
DDR_A_D1
DDR_A_D41
DDR_A_D20
DDR_A_D43
DDR_A_D24
DDR_A_CAS#
DDR_A_D54
DDR_A_D52
DDR_A_D33
DDR_A_D12

DDR_A_D19
DDR_A_D46
DDR_A_D23
DDR_A_D18
DDR_A_D63
DDR_A_D34
DDR_A_D26
DDR_A_D22
SA_RCVENIN#
SA_RCVENOUT#
SB_RCVENIN#
SB_RCVENOUT#
DDR_A_D27
DDR_A_D2
DDR_A_D32
DDR_A_D6
DDR_A_D49
DDR_A_D47
DDR_A_D58
DDR_A_D40
DDR_A_D36
DDR_A_D5
DDR_A_D48
DDR_A_D10
DDR_A_D8
DDR_A_D57
DDR_A_D39
DDR_A_D37
DDR_A_D30
DDR_A_D4

DDR_A_D45
DDR_A_D53
DDR_A_D51
DDR_A_D17
DDR_A_D38
DDR_A_D29
DDR_A_D44
DDR_A_D50
DDR_A_D61
DDR_A_DQS6
DDR_B_DQS7
DDR_B_MA9
DDR_A_MA13
DDR_A_MA7
DDR_A_DM1
DDR_A_MA5
DDR_A_DM7
DDR_B_MA0
DDR_A_DQS7
DDR_A_DM5
DDR_B_MA7
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DM3
DDR_B_DQS1
DDR_B_DM1
DDR_A_BS#0
DDR_A_DQS#6
DDR_B_DQS5
DDR_B_DM0

DDR_A_MA4
DDR_A_MA8
DDR_A_DQS#7
DDR_A_MA10
DDR_A_DQS5
DDR_A_DM2
DDR_A_DQS0
DDR_B_MA2
DDR_B_MA13
DDR_B_DM5
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_BS#1
DDR_A_DQS#1
DDR_A_MA2
DDR_B_MA4
DDR_A_DQS#5
DDR_B_DM6
DDR_B_DQS4
DDR_A_DQS1
DDR_A_MA9
DDR_A_DQS4
DDR_A_DM0
DDR_A_MA0
DDR_B_MA5
DDR_A_DM4
DDR_A_DQS#2
DDR_A_DQS3
DDR_B_MA3
DDR_A_MA11 DDR_B_MA11

DDR_B_BS#0
DDR_A_DM6
DDR_B_MA6DDR_A_MA6
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_A_DQS#0
DDR_A_DM3
DDR_A_MA3
DDR_A_MA12
DDR_B_MA8
DDR_A_DQS2
DDR_B_DQS#0
DDR_B_MA10
DDR_B_DM7
DDR_A_MA1
DDR_B_MA12
DDR_B_DQS#2
DDR_B_DM4
DDR_B_DQS#6
DDR_B_MA1
DDR_B_DQS2
DDR_B_DQS6
DDR_B_DM2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_RAS#
DDR_B_CAS#
DDR_A_BS#1
DDR_A_BS#0<13>

DDR_A_BS#1<13>
DDR_A_BS#2<13>
DDR_A_DM[0 7]<13>
DDR_A_DQS[0 7]<13>
DDR_A_DQS#[0 7]<13>
DDR_A_MA[0 13]<13>
DDR_A_CAS#<13>
DDR_A_RAS#<13>
DDR_A_WE#<13>
DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>
DDR_B_DM[0 7]<14>
DDR_B_DQS[0 7]<14>
DDR_B_DQS#[0 7]<14>
DDR_B_MA[0 13]<14>
DDR_B_CAS#<14>
DDR_B_RAS#<14>
DDR_B_WE#<14>
DDR_A_D[0 63] <13> DDR_B_D[0 63] <14>
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date
Deciphered Date
LA-3491P
0.5
Calistoga (2/6)
847Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
DDR SYS MEMORY A
U3D
CALISTOGA_FCBGA1466~D
SA_DQ0
AJ35
SA_DQ1
AJ34
SA_DQ2
AM31
SA_DQ3
AM33
SA_DQ4
AJ36
SA_DQ5
AK35
SA_DQ6
AJ32
SA_DQ7
AH31
SA_DQ8
AN35
SA_DQ9

AP33
SA_DQ10
AR31
SA_DQ11
AP31
SA_DQ12
AN38
SA_DQ13
AM36
SA_DQ14
AM34
SA_DQ15
AN33
SA_DQ16
AK26
SA_DQ17
AL27
SA_DQ18
AM26
SA_DQ19
AN24
SA_DQ20
AK28
SA_DQ21
AL28
SA_DQ22
AM24
SA_DQ23
AP26
SA_DQ24

AP23
SA_DQ25
AL22
SA_DQ26
AP21
SA_DQ27
AN20
SA_DQ28
AL23
SA_DQ29
AP24
SA_DQ30
AP20
SA_DQ31
AT21
SA_DQ32
AR12
SA_DQ33
AR14
SA_DQ34
AP13
SA_DQ35
AP12
SA_DQ36
AT13
SA_DQ37
AT12
SA_DQ38
AL14
SA_DQ39

AL12
SA_DQ40
AK9
SA_DQ41
AN7
SA_DQ42
AK8
SA_DQ43
AK7
SA_DQ44
AP9
SA_DQ45
AN9
SA_DQ46
AT5
SA_DQ47
AL5
SA_DQ48
AY2
SA_DQ49
AW2
SA_DQ50
AP1
SA_DQ51
AN2
SA_DQ52
AV2
SA_DQ53
AT3
SA_DQ54

AN1
SA_DQ55
AL2
SA_DQ56
AG7
SA_DQ57
AF9
SA_DQ58
AG4
SA_DQ59
AF6
SA_DQ60
AG9
SA_DQ61
AH6
SA_DQ62
AF4
SA_DQ63
AF8
SA_BS0
AU12
SA_BS1
AV14
SA_BS2
BA20
SA_CAS#
AY13
SA_RAS#
AW14
SA_WE#

AY14
SA_RCVENIN#
AK23
SA_RCVENOUT#
AK24
SA_DM0
AJ33
SA_DM1
AM35
SA_DM2
AL26
SA_DM3
AN22
SA_DM4
AM14
SA_DM5
AL9
SA_DM6
AR3
SA_DM7
AH4
SA_DQS0
AK33
SA_DQS1
AT33
SA_DQS2
AN28
SA_DQS3
AM22
SA_DQS4

AN12
SA_DQS5
AN8
SA_DQS6
AP3
SA_DQS7
AG5
SA_DQS0#
AK32
SA_DQS1#
AU33
SA_DQS2#
AN27
SA_DQS3#
AM21
SA_DQS4#
AM12
SA_DQS5#
AL8
SA_DQS6#
AN3
SA_DQS7#
AH5
SA_MA0
AY16
SA_MA1
AU14
SA_MA2
AW16
SA_MA3

BA16
SA_MA4
BA17
SA_MA5
AU16
SA_MA6
AV17
SA_MA7
AU17
SA_MA8
AW17
SA_MA9
AT16
SA_MA10
AU13
SA_MA11
AT17
SA_MA12
AV20
SA_MA13
AV12
T10 PAD
T12 PADT11 PAD
T9 PAD
DDR SYS MEMORY B
U3E
CALISTOGA_FCBGA1466~D
SB_DQ0
AK39
SB_DQ1

AJ37
SB_DQ2
AP39
SB_DQ3
AR41
SB_DQ4
AJ38
SB_DQ5
AK38
SB_DQ6
AN41
SB_DQ7
AP41
SB_DQ8
AT40
SB_DQ9
AV41
SB_DQ10
AU38
SB_DQ11
AV38
SB_DQ12
AP38
SB_DQ13
AR40
SB_DQ14
AW38
SB_DQ15
AY38
SB_DQ16

BA38
SB_DQ17
AV36
SB_DQ18
AR36
SB_DQ19
AP36
SB_DQ20
BA36
SB_DQ21
AU36
SB_DQ22
AP35
SB_DQ23
AP34
SB_DQ24
AY33
SB_DQ25
BA33
SB_DQ26
AT31
SB_DQ27
AU29
SB_DQ28
AU31
SB_DQ29
AW31
SB_DQ30
AV29
SB_DQ31

AW29
SB_DQ32
AM19
SB_DQ33
AL19
SB_DQ34
AP14
SB_DQ35
AN14
SB_DQ36
AN17
SB_DQ37
AM16
SB_DQ38
AP15
SB_DQ39
AL15
SB_DQ40
AJ11
SB_DQ41
AH10
SB_DQ42
AJ9
SB_DQ43
AN10
SB_DQ44
AK13
SB_DQ45
AH11
SB_DQ46

AK10
SB_DQ47
AJ8
SB_DQ48
BA10
SB_DQ49
AW10
SB_DQ50
BA4
SB_DQ51
AW4
SB_DQ52
AY10
SB_DQ53
AY9
SB_DQ54
AW5
SB_DQ55
AY5
SB_DQ56
AV4
SB_DQ57
AR5
SB_DQ58
AK4
SB_DQ59
AK3
SB_DQ60
AT4
SB_DQ61

AK5
SB_DQ62
AJ5
SB_DQ63
AJ3
SB_BS0
AT24
SB_BS1
AV23
SB_BS2
AY28
SB_CAS#
AR24
SB_RAS#
AU23
SB_WE#
AR27
SB_RCVENIN#
AK16
SB_RCVENOUT#
AK18
SB_DM0
AK36
SB_DM1
AR38
SB_DM2
AT36
SB_DM3
BA31
SB_DM4

AL17
SB_DM5
AH8
SB_DM6
BA5
SB_DM7
AN4
SB_DQS0
AM39
SB_DQS1
AT39
SB_DQS2
AU35
SB_DQS3
AR29
SB_DQS4
AR16
SB_DQS5
AR10
SB_DQS6
AR7
SB_DQS7
AN5
SB_DQS0#
AM40
SB_DQS1#
AU39
SB_DQS2#
AT35
SB_DQS3#

AP29
SB_DQS4#
AP16
SB_DQS5#
AT10
SB_DQS6#
AT7
SB_DQS7#
AP5
SB_MA0
AY23
SB_MA1
AW24
SB_MA2
AY24
SB_MA3
AR28
SB_MA4
AT27
SB_MA5
AT28
SB_MA6
AU27
SB_MA7
AV28
SB_MA8
AV27
SB_MA9
AW27
SB_MA10

AV24
SB_MA11
BA27
SB_MA12
AY27
SB_MA13
AR23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEGCOMP
VSYNC
HSYNC
CRT_IREF
LIBG
ENAVDD
LCD_CLK
LCD_DAT
BKLT_CTL

ENABLT
LCD_CLK
LCD_DAT
VSYNCHSYNC
LVDSB1+
LVDSB1-
LVDSBC+
LVDSBC-
LVDSA0+
LVDSA0-
LVDSAC-
LVDSAC+
LVDSA2-
LVDSA2+
LVDSB2+
LVDSB2-
LVDSA1-
LVDSA1+
LVDSB0+
LVDSB0-
ENABLT
COMPS
LUMA
CRMA
CRT_SMBCLK<16>
CRT_SMBDAT<16>
VSYNC<16>
HSYNC<16>
LCD_CLK<17>
LCD_DAT<17>

BKLT_CTL<17>
ENABLT<17,30>
ENAVDD<17>
LVDSB1+<17>
LVDSB1-<17>
LVDSBC-<17>
LVDSBC+<17>
LVDSA0+<17>
LVDSA0-<17>
LVDSAC+<17>
LVDSAC-<17>
LVDSA2-<17>
LVDSA2+<17>
LVDSB2-<17>
LVDSB2+<17>
LVDSA1-<17>
LVDSA1+<17>
LVDSB0-<17>
LVDSB0+<17>
CRT_GRN<16>
CRT_BLU<16>
CRT_RED<16>
+1.5VS_PCIE
+3VS
+3VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS

Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Calistoga (3/6)
947Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
PEGCOMP trace width
and spacing is 18/25 mils.
R54 1.5K_0402_1%
12
R53
100K_0402_5%

1 2
D2
PACDN042_SOT23~D@
2
3

1
R2212 10K_0402_5%
1 2
R2173 0_0402_5%

1 2
R52
24.9_0402_1%
1 2
LVDS
TV CRT
PCI-EXPRESS GRAPHICS
U3C
CALISTOGA_FCBGA1466~D
SDVOCTRL_CLK
H28
SDVOCTRL_DATA
H27
LA_DATA0
B37
LA_DATA1
B34
LA_DATA2
A36
LVREFH
C33
LVREFL
C32
TVDAC_A
A16

TVDAC_B
C18
TVDAC_C
A19
TV_IREF
J20
TV_IRTNA
B16
TV_IRTNB
B18
TV_IRTNC
B19
DDCCLK
C26
DDCDATA
C25
LA_DATA#0
C37
LA_DATA#1
B35
LA_DATA#2
A37
LB_DATA0
F30
LB_DATA1
D29
LB_DATA2
F28
LB_DATA#0
G30

LB_DATA#1
D30
LB_DATA#2
F29
LA_CLK
A32
LA_CLK#
A33
LB_CLK
E26
LB_CLK#
E27
LBKLT_CTL
D32
LBKLT_EN
J30
LCTLA_CLK
H30
LCTLB_DATA
H29
LDDC_CLK
G26
LDDC_DATA
G25
LVDD_EN
F32
LIBG
B38
LVBG
C35

VSYNC
H23
HSYNC
G23
BLUE
E23
BLUE#
D23
GREEN
C22
GREEN#
B22
RED
A21
RED#
B21
CRT_IREF
J22
EXP_COMPI
D40
EXP_COMPO
D38
EXP_RXN0
F34
EXP_RXN1
G38
EXP_RXN2
H34
EXP_RXN3
J38

EXP_RXN4
L34
EXP_RXN5
M38
EXP_RXN6
N34
EXP_RXN7
P38
EXP_RXN8
R34
EXP_RXN9
T38
EXP_RXN10
V34
EXP_RXN11
W38
EXP_RXN12
Y34
EXP_RXN13
AA38
EXP_RXN14
AB34
EXP_RXN15
AC38
EXP_RXP0
D34
EXP_RXP1
F38
EXP_RXP2
G34

EXP_RXP3
H38
EXP_RXP4
J34
EXP_RXP5
L38
EXP_RXP6
M34
EXP_RXP7
N38
EXP_RXP8
P34
EXP_RXP9
R38
EXP_RXP10
T34
EXP_RXP11
V38
EXP_RXP12
W34
EXP_RXP13
Y38
EXP_RXP14
AA34
EXP_RXP15
AB38
EXP_TXN0
F36
EXP_TXN1
G40

EXP_TXN2
H36
EXP_TXN3
J40
EXP_TXN4
L36
EXP_TXN5
M40
EXP_TXN6
N36
EXP_TXN7
P40
EXP_TXN8
R36
EXP_TXN9
T40
EXP_TXN10
V36
EXP_TXN11
W40
EXP_TXN12
Y36
EXP_TXN13
AA40
EXP_TXN14
AB36
EXP_TXN15
AC40
EXP_TXP0
D36

EXP_TXP1
F40
EXP_TXP2
G36
EXP_TXP3
H40
EXP_TXP4
J36
EXP_TXP5
L40
EXP_TXP6
M36
EXP_TXP7
N40
EXP_TXP8
P36
EXP_TXP9
R40
EXP_TXP10
T36
EXP_TXP11
V40
EXP_TXP12
W36
EXP_TXP13
Y40
EXP_TXP14
AA36
EXP_TXP15
AB40

TV_DCONSEL1
J29
TV_DCONSEL0
K30
R2172 0_0402_5%

1 2
R2211 10K_0402_5%
1 2
R58
255_0402_1%
12
R55
10K_0402_5%
12
R57
0_0603_5%

1 2
R2174 0_0402_5%

1 2
R2251
0_0402_5%

1 2
R56
10K_0402_5%
12
5

5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MCH_D2
MCH_A6
MCH_AB1
3GPLL
MCH_CRTDAC
+1.5VS
+1.5VS_PCIE
+1.5VS
+1.5VS+1.5VS_3GPLL
+3VS
+1.5VS_MPLL
+1.5VS
+1.5VS_3GPLL
+1.5VS
+VCCP
+1.5VS_MPLL
+1.5VS_HPLL

+1.5VS+1.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+1.5VS_DPLLB
+1.5VS_DPLLA
+1.5VS_HPLL
+1.5VS_DPLLA +1.5VS_DPLLB
+1.5VS+1.5VS
+1.5VS_DPLLA +1.5VS_DPLLB
+VCCP
+2.5VS +3VS
+1.5VS
+2.5VS
+1.5VS
+1.5VS
+1.5VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date

Deciphered Date
LA-3491P
0.5
Calistoga (4/6)
10 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
W=40 mils
45mA Max. 45mA Max.
PCI-E/MEM/PSB PLL decoupling
Place close to Pin G41
12/28
+
C64
220U_D2_2VM_R9
1
2
C66
10U_0805_6.3V6M
1
2
R70
10_0402_5%@
12
R68
0_0805_5%
12
R65
0_0805_5%
12

R2224
0_0402_5%

12
C85
0.1U_0402_16V4Z

1
2
D4
CH751H-40_SOD323
@
1 2
C79
10U_0805_6.3V6M
1
2
C93
0.22U_0603_10V7K

1
2
C87
0.1U_0402_16V4Z

1
2
C63
0.1U_0402_16V4Z

1
2
L1
CHB1608U301_0603
12
R60
0_0805_5%

12
C74
2200P_0402_50V7K
1
2
R64
0.5_0805_1%
1 2
C91
0.22U_0603_10V7K

1
2
R2221
0_0402_5%

12
L2
CHB1608U301_0603@
12
C90
10U_0805_6.3V6M

1
2
R71
10_0402_5%@
12
C75
0.1U_0402_16V4Z
1
2
+
C67
220U_D2_2VM_R9
1
2
+
C61
330U_D2E_2.5VM
@
1
2
C80
0.1U_0402_16V4Z
@
1
2
L3
BLM11A601S_0603
1 2
C88
10U_0805_6.3V6M

1
2
R2222
0_0402_5%

12
C59
0.1U_0402_16V4Z
1 2
C84
0.47U_0603_10V7K

1
2
C86
10U_0805_6.3V6M
1
2
C76
4.7U_0805_10V4Z

1
2
C92
0.1U_0402_16V4Z

1
2
+
C60

330U_D2E_2.5VM
1
2
R2225
0_0402_5%

12
C94
0.47U_0603_10V7K

1
2
R2223
0_0402_5%

12
C78
0.1U_0402_16V4Z

1
2
C89
0.1U_0402_16V4Z

1
2
C58
0.1U_0402_16V4Z

1

2
R59
0_1206_5%
1 2
C62
0.1U_0402_16V4Z

1
2
C65
10U_0805_6.3V6M
1
2
C77
2.2U_0805_16V4Z

1
2
P O W E R
U3H
CALISTOGA_FCBGA1466~D
VCC_SYNC
H22
VCCTX_LVDS0
B30
VCCTX_LVDS1
C30
VCC3G0
AB41
VCC3G1

AJ41
VCC3G2
L41
VCC3G3
N41
VCC3G4
R41
VCC3G5
V41
VCC3G6
Y41
VCCA_3GBG
G41
VSSA_3GBG
H41
VCCA_3GPLL
AC33
VCCTX_LVDS2
A30
VCCA_LVDS
A38
VSSA_LVDS
B39
VCCA_MPLL
AF2
VCCA_TVBG
H20
VSSA_TVBG
G20
VCCA_TVDACA0

E19
VCCA_TVDACA1
F19
VCCA_TVDACB0
C20
VCCA_TVDACB1
D20
VCCA_TVDACC0
E20
VCCA_TVDACC1
F20
VCCAUX1
AF31
VCCAUX2
AE31
VCCAUX3
AC31
VCCAUX4
AL30
VCCAUX5
AK30
VCCAUX6
AJ30
VCCAUX7
AH30
VCCAUX8
AG30
VCCAUX9
AF30
VCCAUX10

AE30
VCCAUX11
AD30
VCCAUX12
AC30
VCCAUX13
AG29
VCCAUX14
AF29
VCCAUX15
AE29
VCCAUX16
AD29
VCCAUX17
AC29
VCCAUX18
AG28
VCCAUX19
AF28
VCCAUX20
AE28
VTT0
AC14
VTT1
AB14
VTT2
W14
VTT3
V14
VTT4

T14
VTT5
R14
VTT6
P14
VTT7
N14
VTT8
M14
VTT9
L14
VTT10
AD13
VTT11
AC13
VTT12
AB13
VTT13
AA13
VTT14
Y13
VTT15
W13
VTT16
V13
VTT17
U13
VTT18
T13
VTT19

R13
VTT20
N13
VTT21
M13
VTT22
L13
VTT23
AB12
VTT24
AA12
VTT25
Y12
VTT26
W12
VTT27
V12
VTT28
U12
VTT29
T12
VTT30
R12
VTT31
P12
VTT32
N12
VTT33
M12
VTT34

L12
VTT35
R11
VTT36
P11
VTT37
N11
VTT38
M11
VTT39
R10
VTT40
P10
VTT41
N10
VTT42
M10
VTT43
P9
VTT44
N9
VTT45
M9
VTT46
R8
VTT47
P8
VTT48
N8
VTT49

M8
VTT50
P7
VTT51
N7
VTT52
M7
VTT53
R6
VTT54
P6
VTT55
M6
VTT56
A6
VTT57
R5
VTT59
N5
VTT60
M5
VTT61
P4
VTT62
N4
VTT63
M4
VTT64
R3
VTT65

P3
VTT66
N3
VTT67
M3
VTT68
R2
VTT69
P2
VTT70
M2
VTT71
D2
VTT72
AB1
VTT73
R1
VTT74
P1
VTT75
N1
VTT76
M1
VCCA_CRTDAC0
E21
VCCA_CRTDAC1
F21
VSSA_CRTDAC2
G21
VCCA_DPLLA

B26
VCCA_DPLLB
C39
VCCA_HPLL
AF1
VCCD_HMPLL0
AH1
VCCD_HMPLL1
AH2
VCCD_LVDS0
A28
VCCD_LVDS1
B28
VCCD_LVDS2
C28
VCCD_TVDAC
D21
VCCDQ_TVDAC
H19
VCCHV0
A23
VCCHV1
B23
VCCHV2
B25
VCCAUX21
AH22
VCCAUX22
AJ21
VCCAUX23

AH21
VCCAUX24
AJ20
VCCAUX25
AH20
VCCAUX26
AH19
VCCAUX27
P19
VCCAUX28
P16
VCCAUX29
AH15
VCCAUX30
P15
VCCAUX31
AH14
VCCAUX32
AG14
VCCAUX33
AF14
VCCAUX34
AE14
VCCAUX35
Y14
VCCAUX36
AF13
VCCAUX37
AE13
VCCAUX38

AF12
VCCAUX39
AE12
VCCAUX40
AD12
VCCAUX0
AK31
VTT58
P5
D3
CH751H-40_SOD323
@
1 2
R67
0_0805_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A

VCCSM_LF1
VCCSM_LF2
VCCSM_LF5
VCCSM_LF4
CFG18<7>
CFG13<7>
CFG19<7>
CFG16<7>
CFG9<7>
CFG20<7>
CFG11<7>
CFG12<7>
CFG5<7>
CFG7<7>
+VCCP
+1.5VS
+VCCP
+1.8V
+VCCP
+1.8V
+3VS
+1.8V
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Calistoga (5/6)
11 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Place near pin BA15
Place near pin BA23
Place near pin AT41 & AM41
Place near pin AV1 & AJ1
CFG[13:12]
1 = PCIE/SDVO are operating
simu.
CFG7
CFG19
(Default)
CFG20
0 = DMI x 2
CFG18
CFG[19:18] have internal pull down
*
Strap Pin Table
*
10 = All Z Mode Enabled
0 = Reserved
(Default)

1 = Normal Operation
CFG5
SDVO_CTRLDATA
*
1 = DMI Lane Reversal Enable
(Default)
*
1 = Dynamic ODT Enabled (Default)
*
(Default)
00 = Reserved
1 = 1.5V
*
*
1 = DMI x 4
CFG[3:17] have internal pull up
0 = No SDVO Device Present
(Default)
*
*
(Default)
(Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO is
operational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
01 = XOR Mode Enabled
001 = 533MT/s FSB

CFG16
0 = 1.05V
011 = 667MT/s FSB
0 = Lane Reversal Enable
CFG9
1 = SDVO Device Present
CFG[2:0]
1 = Mobile Yonah CPU
11 = Normal Operation
CFG11
0 = Calistoga
1 = Reserved
*
(According to Intel Napa Schematic Checklist & CRB
Rev1.301 document 2.2Kohm pull-down resistor
request)
R78 2.2K_0402_5%@
1 2
C114
10U_0805_6.3V6M
1
2
P O W E R
U3G
CALISTOGA_FCBGA1466~D
VCC0
AA33
VCC1
W33
VCC2

P33
VCC3
N33
VCC4
L33
VCC5
J33
VCC6
AA32
VCC7
Y32
VCC8
W32
VCC9
V32
VCC10
P32
VCC11
N32
VCC12
M32
VCC13
L32
VCC14
J32
VCC15
AA31
VCC16
W31
VCC17

V31
VCC18
T31
VCC19
R31
VCC20
P31
VCC21
N31
VCC22
M31
VCC23
AA30
VCC24
Y30
VCC25
W30
VCC26
V30
VCC27
U30
VCC28
T30
VCC29
R30
VCC30
P30
VCC31
N30
VCC32

M30
VCC33
L30
VCC34
AA29
VCC35
Y29
VCC36
W29
VCC37
V29
VCC38
U29
VCC39
R29
VCC40
P29
VCC41
M29
VCC42
L29
VCC43
AB28
VCC44
AA28
VCC45
Y28
VCC_SM5
AY34
VCC_SM6

AW34
VCC_SM7
AV34
VCC_SM8
AU34
VCC_SM9
AT34
VCC_SM10
AR34
VCC_SM11
BA30
VCC_SM12
AY30
VCC_SM13
AW30
VCC_SM14
AV30
VCC_SM15
AU30
VCC_SM16
AT30
VCC_SM17
AR30
VCC_SM18
AP30
VCC_SM19
AN30
VCC_SM20
AM30
VCC_SM21

AM29
VCC_SM22
AL29
VCC_SM23
AK29
VCC_SM24
AJ29
VCC_SM25
AH29
VCC_SM26
AJ28
VCC_SM27
AH28
VCC_SM28
AJ27
VCC_SM29
AH27
VCC_SM30
BA26
VCC_SM31
AY26
VCC_SM32
AW26
VCC_SM33
AV26
VCC_SM34
AU26
VCC_SM35
AT26
VCC_SM36

AR26
VCC_SM37
AJ26
VCC_SM38
AH26
VCC_SM39
AJ25
VCC_SM40
AH25
VCC_SM41
AJ24
VCC_SM42
AH24
VCC_SM43
BA23
VCC_SM44
AJ23
VCC_SM45
BA22
VCC_SM46
AY22
VCC_SM47
AW22
VCC_SM48
AV22
VCC_SM49
AU22
VCC_SM50
AT22
VCC_SM51

AR22
VCC_SM52
AP22
VCC_SM53
AK22
VCC_SM54
AJ22
VCC_SM55
AK21
VCC_SM56
AK20
VCC_SM57
BA19
VCC_SM58
AY19
VCC_SM59
AW19
VCC_SM60
AV19
VCC_SM61
AU19
VCC_SM62
AT19
VCC_SM63
AR19
VCC_SM64
AP19
VCC_SM65
AK19
VCC_SM66

AJ19
VCC_SM67
AJ18
VCC_SM68
AJ17
VCC_SM69
AH17
VCC_SM70
AJ16
VCC_SM71
AH16
VCC_SM72
BA15
VCC_SM3
AU40
VCC_SM4
BA34
VCC_SM73
AY15
VCC_SM74
AW15
VCC_SM75
AV15
VCC_SM76
AU15
VCC_SM77
AT15
VCC_SM78
AR15
VCC_SM79

AJ15
VCC_SM80
AJ14
VCC_SM81
AJ13
VCC_SM82
AH13
VCC_SM83
AK12
VCC_SM84
AJ12
VCC_SM85
AH12
VCC_SM86
AG12
VCC_SM87
AK11
VCC_SM88
BA8
VCC_SM89
AY8
VCC_SM90
AW8
VCC_SM91
AV8
VCC_SM92
AT8
VCC_SM93
AR8
VCC_SM94

AP8
VCC_SM95
BA6
VCC_SM96
AY6
VCC_SM97
AW6
VCC_SM98
AV6
VCC_SM99
AT6
VCC_SM1
AT41
VCC_SM0
AU41
VCC_SM2
AM41
VCC46
V28
VCC47
U28
VCC48
T28
VCC49
R28
VCC50
P28
VCC51
N28
VCC52

M28
VCC53
L28
VCC54
P27
VCC55
N27
VCC56
M27
VCC57
L27
VCC58
P26
VCC59
N26
VCC60
L26
VCC61
N25
VCC62
M25
VCC63
L25
VCC64
P24
VCC65
N24
VCC66
M24
VCC67

AB23
VCC68
AA23
VCC69
Y23
VCC70
P23
VCC71
N23
VCC72
M23
VCC73
L23
VCC74
AC22
VCC75
AB22
VCC76
Y22
VCC77
W22
VCC78
P22
VCC79
N22
VCC80
M22
VCC81
L22
VCC82

AC21
VCC83
AA21
VCC84
W21
VCC85
N21
VCC86
M21
VCC87
L21
VCC88
AC20
VCC89
AB20
VCC90
Y20
VCC91
W20
VCC92
P20
VCC93
N20
VCC94
M20
VCC95
L20
VCC96
AB19
VCC97

AA19
VCC98
Y19
VCC99
N19
C116
0.47U_0603_10V7K

1
2
C118
0.47U_0603_10V7K

1
2
C111
0.47U_0603_10V7K

1
2
+
C112
220U_D2_4VM@
1
2
C97
0.47U_0603_10V7K

1
2

C99
0.22U_0603_10V7K

1
2
C102
0.1U_0402_16V4Z

1
2
C103
0.1U_0402_16V4Z

1
2
C101
0.22U_0603_10V7K

1
2
+
C109
220U_D2_2VM_R9
1
2
R80 1K_0402_5%@
1 2
C117
0.47U_0603_10V7K

1
2
R79 1K_0402_5%@
1 2
C98
0.47U_0603_10V7K

1
2
+
C115
330U_D2E_2.5VM_R9
@
1
2
C106
10U_0805_6.3V6M
1
2
C104
0.1U_0402_16V4Z

1
2
R77 2.2K_0402_5%@
1 2
C105
0.1U_0402_16V4Z

1

2
R73 2.2K_0402_5%@
1 2
C100
0.22U_0603_10V7K

1
2
C113
10U_0805_6.3V6M
1
2
R75 2.2K_0402_5%@
1 2
P O W E R
U3F
CALISTOGA_FCBGA1466~D
VCC_NCTF1
AC27
VCC_NCTF2
AB27
VCC_NCTF3
AA27
VCC_NCTF4
Y27
VCC_NCTF5
W27
VCC_NCTF6
V27
VCC_NCTF7

U27
VCCAUX_NCTF52
Y15
VCC_NCTF9
R27
VCC_NCTF10
AD26
VCC_NCTF11
AC26
VCC_NCTF12
AB26
VCC_NCTF13
AA26
VCC_NCTF14
Y26
VCC_NCTF15
W26
VCC_NCTF16
V26
VCC_NCTF17
U26
VCC_NCTF18
T26
VCC_NCTF19
R26
VCC_NCTF20
AD25
VCC_NCTF21
AC25
VCC_NCTF22

AB25
VCC_NCTF23
AA25
VCC_NCTF24
Y25
VCC_NCTF25
W25
VCCAUX_NCTF53
W15
VCC_NCTF27
U25
VCC_NCTF28
T25
VCC_NCTF29
R25
VCC_NCTF30
AD24
VCC_NCTF31
AC24
VCC_NCTF32
AB24
VCC_NCTF33
AA24
VCC_NCTF34
Y24
VCC_NCTF35
W24
VCC_NCTF36
V24
VCCAUX_NCTF54

V15
VCC_NCTF38
T24
VCC_NCTF39
R24
VCC_NCTF40
AD23
VCC_NCTF41
V23
VCC_NCTF42
U23
VCC_NCTF43
T23
VCC_NCTF44
R23
VCC_NCTF45
AD22
VCC_NCTF46
V22
VCC_NCTF47
U22
VCC_NCTF48
T22
VCC_NCTF49
R22
VCC_NCTF50
AD21
VCC_NCTF51
V21
VCC_NCTF52

U21
VCC_NCTF53
T21
VCC_NCTF54
R21
VCC_NCTF55
AD20
VCC_NCTF56
V20
VCC_NCTF57
U20
VCC_NCTF58
T20
VCCAUX_NCTF55
U15
VCC_NCTF60
AD19
VCC_NCTF61
V19
VCC_NCTF62
U19
VCC_NCTF63
T19
VCC_NCTF64
AD18
VCC_NCTF65
AC18
VCC_NCTF66
AB18
VCC_NCTF67

AA18
VCC_NCTF68
Y18
VCC_NCTF69
W18
VCC_NCTF70
V18
VCC_NCTF71
U18
VCC_NCTF72
T18
VCC_NCTF0
AD27
VCCAUX_NCTF0
AG27
VCCAUX_NCTF1
AF27
VCCAUX_NCTF2
AG26
VCCAUX_NCTF3
AF26
VCCAUX_NCTF4
AG25
VCCAUX_NCTF5
AF25
VCCAUX_NCTF6
AG24
VCCAUX_NCTF7
AF24
VCCAUX_NCTF8

AG23
VCCAUX_NCTF9
AF23
VCCAUX_NCTF10
AG22
VCCAUX_NCTF11
AF22
VCCAUX_NCTF12
AG21
VCCAUX_NCTF13
AF21
VCCAUX_NCTF14
AG20
VCCAUX_NCTF15
AF20
VCCAUX_NCTF16
AG19
VCCAUX_NCTF17
AF19
VCCAUX_NCTF18
R19
VCCAUX_NCTF19
AG18
VCCAUX_NCTF20
AF18
VCCAUX_NCTF21
R18
VCCAUX_NCTF22
AG17
VCCAUX_NCTF23

AF17
VCCAUX_NCTF24
AE17
VCCAUX_NCTF25
AD17
VCCAUX_NCTF26
AB17
VCCAUX_NCTF27
AA17
VCCAUX_NCTF28
W17
VCCAUX_NCTF29
V17
VCCAUX_NCTF30
T17
VCCAUX_NCTF31
R17
VCCAUX_NCTF32
AG16
VCCAUX_NCTF33
AF16
VCCAUX_NCTF34
AE16
VCCAUX_NCTF35
AD16
VCCAUX_NCTF36
AC16
VCCAUX_NCTF37
AB16
VCCAUX_NCTF38

AA16
VCCAUX_NCTF39
Y16
VCCAUX_NCTF40
W16
VCCAUX_NCTF41
V16
VCCAUX_NCTF42
U16
VCCAUX_NCTF43
T16
VCCAUX_NCTF44
R16
VCCAUX_NCTF45
AG15
VCCAUX_NCTF46
AF15
VCCAUX_NCTF47
AE15
VCCAUX_NCTF48
AD15
VCCAUX_NCTF49
AC15
VCCAUX_NCTF50
AB15
VSS_NCTF0
AE27
VCCAUX_NCTF51
AA15
VSS_NCTF1

AE26
VCC_NCTF59
R20
VCCAUX_NCTF56
T15
VSS_NCTF2
AE25
VSS_NCTF3
AE24
VSS_NCTF4
AE23
VSS_NCTF5
AE22
VSS_NCTF6
AE21
VSS_NCTF7
AE20
VSS_NCTF8
AE19
VSS_NCTF9
AE18
VSS_NCTF10
AC17
VSS_NCTF11
Y17
VSS_NCTF12
U17
VCC_NCTF26
V25
VCCAUX_NCTF57

R15
VCC_NCTF37
U24
VCC_NCTF8
T27
VCC100
M19
VCC101
L19
VCC102
N18
VCC103
M18
VCC104
L18
VCC105
P17
VCC106
N17
VCC107
M17
VCC108
N16
VCC109
M16
VCC110
L16
VCC_SM100
AR6
VCC_SM101

AP6
VCC_SM102
AN6
VCC_SM103
AL6
VCC_SM104
AK6
VCC_SM105
AJ6
VCC_SM106
AV1
VCC_SM107
AJ1
C107
10U_0805_6.3V6M
1
2
R76 2.2K_0402_5%@
1 2
R72 2.2K_0402_5%@
1 2
R74 2.2K_0402_5%@
1 2
R81 1K_0402_5%@
1 2
+
C110
330U_D2E_2.5VM_R9
@
1

2
C108
1U_0603_10V4Z

1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date
Deciphered Date
LA-3491P
0.5
Calistoga (6/6)
12 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
P O W E R
U3I
CALISTOGA_FCBGA1466~D
VSS0
AC41
VSS1
AA41
VSS2
W41
VSS3
T41
VSS4
P41
VSS5
M41
VSS6
J41
VSS7
F41
VSS8
AV40
VSS9

AP40
VSS10
AN40
VSS11
AK40
VSS13
AH40
VSS14
AG40
VSS15
AF40
VSS16
AE40
VSS17
B40
VSS18
AY39
VSS19
AW39
VSS21
AR39
VSS22
AN39
VSS24
AC39
VSS25
AB39
VSS26
AA39
VSS27

Y39
VSS28
W39
VSS29
V39
VSS30
T39
VSS31
R39
VSS32
P39
VSS33
N39
VSS34
M39
VSS35
L39
VSS36
J39
VSS37
H39
VSS20
AV39
VSS23
AJ39
VSS12
AJ40
VSS38
G39
VSS40

D39
VSS41
AT38
VSS42
AM38
VSS43
AH38
VSS44
AG38
VSS45
AF38
VSS46
AE38
VSS47
C38
VSS48
AK37
VSS49
AH37
VSS50
AB37
VSS51
AA37
VSS52
Y37
VSS53
W37
VSS54
V37
VSS55

T37
VSS56
R37
VSS57
P37
VSS58
N37
VSS59
M37
VSS60
L37
VSS61
J37
VSS62
H37
VSS63
G37
VSS64
F37
VSS65
D37
VSS66
AY36
VSS67
AW36
VSS68
AN36
VSS69
AH36
VSS70

AG36
VSS71
AF36
VSS72
AE36
VSS73
AC36
VSS74
C36
VSS75
B36
VSS76
BA35
VSS77
AV35
VSS78
AR35
VSS79
AH35
VSS80
AB35
VSS81
AA35
VSS82
Y35
VSS83
W35
VSS84
V35
VSS85

T35
VSS86
R35
VSS87
P35
VSS88
N35
VSS89
M35
VSS90
L35
VSS91
J35
VSS92
H35
VSS93
G35
VSS94
F35
VSS95
D35
VSS96
AN34
VSS97
AK34
VSS98
AG34
VSS99
AF34
VSS39

F39
VSS100
AE34
VSS101
AC34
VSS102
C34
VSS103
AW33
VSS104
AV33
VSS105
AR33
VSS106
AE33
VSS107
AB33
VSS108
Y33
VSS109
V33
VSS110
T33
VSS111
R33
VSS112
M33
VSS113
H33
VSS114

G33
VSS115
F33
VSS116
D33
VSS117
B33
VSS118
AH32
VSS119
AG32
VSS120
AF32
VSS121
AE32
VSS122
AC32
VSS123
AB32
VSS124
G32
VSS125
B32
VSS126
AY31
VSS127
AV31
VSS128
AN31
VSS129

AJ31
VSS130
AG31
VSS131
AB31
VSS132
Y31
VSS133
AB30
VSS134
E30
VSS135
AT29
VSS136
AN29
VSS137
AB29
VSS138
T29
VSS139
N29
VSS140
K29
VSS141
G29
VSS142
E29
VSS143
C29
VSS144

B29
VSS145
A29
VSS146
BA28
VSS147
AW28
VSS148
AU28
VSS149
AP28
VSS150
AM28
VSS151
AD28
VSS152
AC28
VSS153
W28
VSS154
J28
VSS155
E28
VSS156
AP27
VSS157
AM27
VSS158
AK27
VSS159

J27
VSS160
G27
VSS161
F27
VSS162
C27
VSS163
B27
VSS164
AN26
VSS165
M26
VSS166
K26
VSS167
F26
VSS168
D26
VSS169
AK25
VSS170
P25
VSS171
K25
VSS172
H25
VSS173
E25
VSS174

D25
VSS175
A25
VSS176
BA24
VSS177
AU24
VSS178
AL24
VSS179
AW23
VSS180
AT23
VSS181
AN23
VSS182
AM23
VSS183
AH23
VSS184
AC23
VSS185
W23
VSS186
K23
VSS187
J23
VSS188
F23
VSS189

C23
VSS190
AA22
VSS191
K22
VSS192
G22
VSS193
F22
VSS194
E22
VSS195
D22
VSS196
A22
VSS197
BA21
VSS198
AV21
VSS199
AR21
P O W E R
U3J
CALISTOGA_FCBGA1466~D
VSS200
AN21
VSS201
AL21
VSS202
AB21

VSS203
Y21
VSS204
P21
VSS205
K21
VSS206
J21
VSS207
H21
VSS208
C21
VSS209
AW20
VSS210
AR20
VSS211
AM20
VSS212
AA20
VSS213
K20
VSS214
B20
VSS215
A20
VSS216
AN19
VSS217
AC19

VSS218
W19
VSS219
K19
VSS220
G19
VSS221
C19
VSS222
AH18
VSS223
P18
VSS224
H18
VSS225
D18
VSS226
A18
VSS227
AY17
VSS228
AR17
VSS229
AP17
VSS230
AM17
VSS231
AK17
VSS232
AV16

VSS233
AN16
VSS234
AL16
VSS235
J16
VSS236
F16
VSS237
C16
VSS238
AN15
VSS239
AM15
VSS240
AK15
VSS241
N15
VSS242
M15
VSS243
L15
VSS244
B15
VSS245
A15
VSS246
BA14
VSS247
AT14

VSS248
AK14
VSS249
AD14
VSS250
AA14
VSS251
U14
VSS252
K14
VSS253
H14
VSS254
E14
VSS255
AV13
VSS256
AR13
VSS257
AN13
VSS258
AM13
VSS259
AL13
VSS260
AG13
VSS261
P13
VSS262
F13

VSS266
AC12
VSS267
K12
VSS268
H12
VSS269
E12
VSS270
AD11
VSS271
AA11
VSS272
Y11
VSS273
J11
VSS274
D11
VSS275
B11
VSS276
AV10
VSS277
AP10
VSS278
AL10
VSS279
AJ10
VSS265
D13

VSS264
B13
VSS263
AY12
VSS285
AW9
VSS286
AR9
VSS287
AH9
VSS288
AB9
VSS289
Y9
VSS290
R9
VSS292
G9
VSS291
E9
VSS293
A9
VSS294
AG8
VSS295
AD8
VSS296
AA8
VSS297
U8

VSS298
K8
VSS299
C8
VSS300
BA7
VSS301
AV7
VSS302
AP7
VSS303
AL7
VSS304
AJ7
VSS305
AH7
VSS306
AF7
VSS307
AC7
VSS308
R7
VSS309
G7
VSS310
D7
VSS311
AG6
VSS312
AD6

VSS313
AB6
VSS314
Y6
VSS317
K6
VSS318
H6
VSS319
B6
VSS320
AV5
VSS321
AF5
VSS322
AD5
VSS323
AY4
VSS324
AR4
VSS325
AP4
VSS326
AL4
VSS327
AJ4
VSS328
Y4
VSS329
U4

VSS330
R4
VSS331
J4
VSS332
F4
VSS333
C4
VSS334
AY3
VSS335
AW3
VSS336
AV3
VSS337
AL3
VSS341
AD3
VSS345
AT2
VSS346
AR2
VSS347
AP2
VSS348
AK2
VSS351
AB2
VSS352
Y2

VSS353
U2
VSS354
T2
VSS355
N2
VSS356
J2
VSS357
H2
VSS359
C2
VSS360
AL1
VSS358
F2
VSS349
AJ2
VSS350
AD2
VSS344
G3
VSS343
AA3
VSS342
AC3
VSS340
AF3
VSS338
AH3

VSS280
AG10
VSS281
AC10
VSS282
W10
VSS283
U10
VSS284
BA9
VSS315
U6
VSS316
N6
VSS339
AG3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A

DDR_A_MA11
V_DDR_MCH_REF
DDR_CKE1_DIMMA
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
ICH_SMBCLK
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7
DDR_A_MA12
DDR_A_MA5
DDR_A_WE#
DDR_A_D8
DDR_A_D3
DDR_A_D2
DDR_A_D17
DDR_A_D21
DDR_A_D30
DDR_A_D27
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DM3
DDR_A_DM1
DDR_A_DM2

DDR_A_DM0
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
ICH_SMBDATA
DDR_CKE0_DIMMA
DDR_A_MA8
DDR_CS1_DIMMA#
DDR_A_MA11
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_CAS#
DDR_A_BS#1
DDR_A_RAS#
DDR_A_D15
DDR_A_D20
DDR_A_D9
DDR_A_D16
DDR_A_D28
DDR_A_D26
DDR_A_D31
DDR_A_D37
DDR_A_D36
DDR_A_D39
DDR_A_D29
DDR_A_D34
DDR_A_D49
DDR_A_D48

DDR_A_D54
DDR_A_DM6
DDR_A_DM4
DDR_A_DM5
DDR_A_DM7
DDR_A_MA13
DDR_A_DQS5
DDR_A_BS#0
DDR_A_BS#2
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA4
DDR_A_BS#2
DDR_A_BS#1
DDR_A_MA6
DDR_A_MA9
DDR_CKE0_DIMMA
DDR_A_MA2
DDR_A_MA12
DDR_A_MA5
DDR_A_MA1
DDR_A_CAS#

DDR_A_RAS#
DDR_A_BS#0
DDR_A_MA8
DDR_A_MA3
DDR_A_MA10
DDR_CS0_DIMMA#
M_ODT1
DDR_CS1_DIMMA#
M_ODT1
DDR_A_WE#
M_ODT0
DDR_A_MA13
DDR_A_MA7
M_ODT0
DDR_A_D59
DDR_A_D58
DDR_A_D63
DDR_A_D62
DDR_A_D60
DDR_A_D57
DDR_A_D56
DDR_A_D61
DDR_A_D50DDR_A_D51
DDR_A_D55
DDR_A_D52
DDR_A_D53
DDR_A_D42
DDR_A_D43
DDR_A_D47
DDR_A_D46

DDR_A_D41
DDR_A_D45
DDR_A_D40
DDR_A_D44
DDR_A_D38
DDR_A_D33
DDR_A_D35
DDR_A_D32
DDR_A_D25
DDR_A_D24
DDR_A_D22
DDR_A_D19 DDR_A_D23
DDR_A_D18
DDR_A_D13
DDR_A_D12
DDR_A_D0
DDR_A_D4
DDR_A_D14
DDR_A_D7
DDR_A_D1
DDR_A_D5
DDR_A_D6
DDR_A_D11
DDR_A_D10
DDR_A_DQS#[0 7]<8>
DDR_A_DQS[0 7]<8>
DDR_A_D[0 63]<8>
DDR_A_DM[0 7]<8>
DDR_A_MA[0 13]<8>
DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>
DDR_A_BS#0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
M_ODT1<7>
DDR_CS1_DIMMA#<7>
M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>
DDR_CKE1_DIMMA <7>
DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_CLK_DDR#1 <7>
M_ODT0 <7>
V_DDR_MCH_REF <7,14>
ICH_SMBDATA<4,14,15,20,25>
ICH_SMBCLK<4,14,15,20,25>
M_CLK_DDR1 <7>
DDR_THERM# <7,14>
+1.8V
+0.9V
+3VS
+1.8V
+1.8V
+0.9V
Title
Size Document Number Rev
Date: Sheet
of
Security Classification

Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
DDRII-SODIMM SLOT1
13 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"
Layout Note:
Place near JP34
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
REVERSE
SO-DIMM A
BOT side
C143
0.1U_0402_16V4Z

1
2

C125
2.2U_0805_16V4Z

1
2
R83
10K_0402_5%

12
C121
2.2U_0805_16V4Z

1
2
RP6 56_0404_4P2R_5%
14
23
C133
0.1U_0402_16V4Z

1
2
RP10 56_0404_4P2R_5%
14
23
RP11
56_0404_4P2R_5%
1 4
2 3
C140

0.1U_0402_16V4Z

1
2
C129
0.1U_0402_16V4Z

1
2
C139
0.1U_0402_16V4Z

1
2
C123
2.2U_0805_16V4Z

1
2
C120
0.1U_0402_16V4Z

1
2
C131
0.1U_0402_16V4Z

1
2
RP12 56_0404_4P2R_5%

14
23
RP1
56_0404_4P2R_5%
1 4
2 3
RP3
56_0404_4P2R_5%
1 4
2 3
C135
0.1U_0402_16V4Z

1
2
R82
10K_0402_5%

12
C119
2.2U_0805_16V4Z

1
2
RP7
56_0404_4P2R_5%
1 4
2 3
C127
0.1U_0402_16V4Z

1
2
C141
0.1U_0402_16V4Z

1
2
C142
0.1U_0402_16V4Z

1
2
RP4 56_0404_4P2R_5%
14
23
C136
0.1U_0402_16V4Z

1
2
JP4
FOX_ASOA426-M4R-TRCONN@
VREF
1
VSS
3
DQ0
5
DQ1

7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11

37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3

67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5

97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS

127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS
2
DQ4
4
DQ5
6
VSS
8
DM0
10
VSS
12
DQ6

14
DQ7
16
VSS
18
DQ12
20
DQ13
22
VSS
24
DM1
26
VSS
28
CK0
30
CK0#
32
VSS
34
DQ14
36
DQ15
38
VSS
40
VSS
42
DQ20

44
DQ21
46
VSS
48
NC
50
DM2
52
VSS
54
DQ22
56
DQ23
58
VSS
60
DQ28
62
DQ29
64
VSS
66
DQS3#
68
DQS3
70
VSS
72
DQ30

74
DQ31
76
VSS
78
NC/CKE1
80
VDD
82
NC/A15
84
NC/A14
86
VDD
88
A11
90
A7
92
A6
94
VDD
96
A4
98
A2
100
A0
102
VDD

104
BA1
106
RAS#
108
S0#
110
VDD
112
ODT0
114
NC/A13
116
VDD
118
NC
120
VSS
122
DQ36
124
DQ37
126
VSS
128
DM4
130
VSS
132
DQ38

134
DQ39
136
VSS
138
DQ44
140
DQ45
142
VSS
144
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST

163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS

193
SDA
195
SCL
197
VDDSPD
199
DQS5#
146
DQS5
148
VSS
150
DQ46
152
DQ47
154
VSS
156
DQ52
158
DQ53
160
VSS
162
CK1
164
CK1#
166
VSS

168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
SAO

198
SA1
200
RP5
56_0404_4P2R_5%
1 4
2 3
C128
0.1U_0402_16V4Z

1
2
C134
0.1U_0402_16V4Z

1
2
C137
0.1U_0402_16V4Z

1
2
C132
0.1U_0402_16V4Z

1
2
C130
0.1U_0402_16V4Z

1
2
C138
0.1U_0402_16V4Z

1
2
C122
2.2U_0805_16V4Z

1
2
RP8 56_0404_4P2R_5%
14
23
RP2 56_0404_4P2R_5%
14
23
C126
0.1U_0402_16V4Z

1
2
RP13 56_0404_4P2R_5%
14
23
C124
2.2U_0805_16V4Z

1

2
RP9
56_0404_4P2R_5%
1 4
2 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_MA1
DDR_B_BS#0
DDR_B_CAS#
DDR_B_MA0
DDR_B_RAS#
DDR_B_MA3
DDR_B_MA10
DDR_B_BS#2
DDR_CS2_DIMMB#
DDR_B_BS#1
DDR_CKE2_DIMMB

DDR_CKE3_DIMMB
DDR_B_MA4
DDR_B_MA7
DDR_B_MA9
DDR_B_MA2
DDR_B_MA11
DDR_B_MA5
DDR_B_MA12
DDR_B_MA6
DDR_B_MA8
M_ODT3
DDR_CS3_DIMMB# M_ODT2
DDR_B_MA13
DDR_B_WE#
DDR_B_DQS#4
DDR_B_D14
DDR_B_DQS4
DDR_B_BS#2
DDR_B_D57
DDR_B_MA2
DDR_CKE2_DIMMB
DDR_B_D8
DDR_B_D1
DDR_B_DM3
ICH_SMBDATA
DDR_B_D52
DDR_B_D45
DDR_B_MA3
DDR_B_D37
DDR_B_D59

DDR_B_D40
DDR_B_D6
DDR_B_MA7
DDR_B_D13
DDR_B_D5
DDR_B_D61
DDR_B_DQS#0
DDR_CS3_DIMMB#
M_ODT3
DDR_B_MA11
DDR_B_D46
DDR_B_WE#
DDR_B_D2
DDR_B_D11
DDR_B_MA10
DDR_B_D55
DDR_B_D35
DDR_B_D41
DDR_B_DQS5
M_ODT2
DDR_B_DQS2
DDR_B_DQS#7
DDR_B_MA6
DDR_B_D9
DDR_B_D44
DDR_B_D63
DDR_B_DM7
DDR_B_BS#0
DDR_B_MA5
DDR_B_D56

DDR_B_D4
DDR_B_DQS#3
DDR_B_D10
DDR_B_D12
DDR_B_D22
DDR_B_D48
DDR_B_D36
DDR_B_DQS7
DDR_B_D42
DDR_B_D33
DDR_CKE3_DIMMB
DDR_B_DQS0
DDR_B_D43
DDR_B_MA1
DDR_B_MA8
DDR_B_DQS#2
DDR_B_DQS#5
DDR_B_MA12
DDR_B_DQS3
DDR_B_RAS#
DDR_B_MA4
DDR_B_DM5
DDR_B_D34
ICH_SMBCLK
DDR_B_D47
DDR_B_D7
DDR_B_MA13
DDR_B_D32
DDR_B_DQS1
DDR_B_BS#1

DDR_B_D62
DDR_B_DQS#6
DDR_B_D54
DDR_B_DM4
DDR_B_DQS6
DDR_B_DQS#1
DDR_B_D49
DDR_B_MA9
DDR_B_MA0
DDR_B_D3
DDR_B_D15
DDR_B_CAS#
DDR_B_D23
DDR_CS2_DIMMB#
DDR_B_DM0
DDR_B_DM1
DDR_B_D0
V_DDR_MCH_REF
DDR_B_DM6
DDR_B_D60
DDR_B_D58
DDR_B_D53
DDR_B_DM2
DDR_B_D50
DDR_B_D51
DDR_B_D39
DDR_B_D38
DDR_B_D31
DDR_B_D30
DDR_B_D27

DDR_B_D29
DDR_B_D25
DDR_B_D24
DDR_B_D28
DDR_B_D26
DDR_B_D19
DDR_B_D18
DDR_B_D20
DDR_B_D16DDR_B_D21
DDR_B_D17
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_DQS#[0 7]<8>
DDR_B_DQS[0 7]<8>
DDR_B_D[0 63]<8>
DDR_B_MA[0 13]<8>
DDR_B_DM[0 7]<8>
DDR_CKE3_DIMMB <7>
DDR_CS2_DIMMB# <7>
V_DDR_MCH_REF <7,13>
ICH_SMBCLK<4,13,15,20,25>
ICH_SMBDATA<4,13,15,20,25>
DDR_B_WE#<8>
DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_B_CAS#<8>
M_ODT3<7>
DDR_CKE2_DIMMB<7>

DDR_CS3_DIMMB#<7>
DDR_B_BS#2<8>
DDR_B_BS#0<8>
M_ODT2 <7>
M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_THERM# <7,13>
+0.9V
+1.8V
+3VS
+3VS
+1.8V
+1.8V
+0.9V
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5

DDRII-SODIMM SLOT2
14 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
SO-DIMM B
STANDARD
Bottom side
Layout Note:
Place near JP34
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"
RP20
56_0404_4P2R_5%
1 4
2 3
C166
0.1U_0402_16V4Z

1
2
C152
0.1U_0402_16V4Z

1
2

C161
0.1U_0402_16V4Z

1
2
R84
10K_0402_5%

1 2
JP5
FOX_ASOA426-M2RN-7F CONN@
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3

19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#

49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0

79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#

109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS

139
DQ40
141
DQ41
143
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6

169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD

199
VSS
2
DQ4
4
DQ5
6
VSS
8
DM0
10
VSS
12
DQ6
14
DQ7
16
VSS
18
DQ12
20
DQ13
22
VSS
24
DM1
26
VSS
28
CK0

30
CK0#
32
VSS
34
DQ14
36
DQ15
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VSS
48
NC
50
DM2
52
VSS
54
DQ22
56
DQ23
58
VSS

60
DQ28
62
DQ29
64
VSS
66
DQS3#
68
DQS3
70
VSS
72
DQ30
74
DQ31
76
VSS
78
NC/CKE1
80
VDD
82
NC/A15
84
NC/A14
86
VDD
88
A11

90
A7
92
A6
94
VDD
96
A4
98
A2
100
A0
102
VDD
104
BA1
106
RAS#
108
S0#
110
VDD
112
ODT0
114
NC/A13
116
VDD
118
NC

120
VSS
122
DQ36
124
DQ37
126
VSS
128
DM4
130
VSS
132
DQ38
134
DQ39
136
VSS
138
DQ44
140
DQ45
142
VSS
144
DQS5#
146
DQS5
148
VSS

150
DQ46
152
DQ47
154
VSS
156
DQ52
158
DQ53
160
VSS
162
CK1
164
CK1#
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60

180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
SA0
198
SA1
200
GND
203
GND
204
C145
0.1U_0402_16V4Z

1
2

C167
0.1U_0402_16V4Z

1
2
RP18
56_0404_4P2R_5%
1 4
2 3
C168
0.1U_0402_16V4Z

1
2
C146
2.2U_0805_16V4Z

1
2
RP24
56_0404_4P2R_5%
1 4
2 3
RP26
56_0404_4P2R_5%
14
23
C144
2.2U_0805_16V4Z

1
2
RP22
56_0404_4P2R_5%
1 4
2 3
C156
0.1U_0402_16V4Z

1
2
RP16
56_0404_4P2R_5%
1 4
2 3
C150
2.2U_0805_16V4Z

1
2
RP25 56_0404_4P2R_5%
14
23
RP15 56_0404_4P2R_5%
14
23
C163
0.1U_0402_16V4Z

1

2
RP21 56_0404_4P2R_5%
14
23
C165
0.1U_0402_16V4Z

1
2
C160
0.1U_0402_16V4Z

1
2
C157
0.1U_0402_16V4Z

1
2
C153
0.1U_0402_16V4Z

1
2
RP17 56_0404_4P2R_5%
14
23
C155
0.1U_0402_16V4Z

1
2
C162
0.1U_0402_16V4Z

1
2
C147
2.2U_0805_16V4Z

1
2
C158
0.1U_0402_16V4Z

1
2
R85
10K_0402_5%

12
C148
2.2U_0805_16V4Z

1
2
C154
0.1U_0402_16V4Z

1

2
RP23 56_0404_4P2R_5%
14
23
C151
0.1U_0402_16V4Z

1
2
RP14
56_0404_4P2R_5%
1 4
2 3
C159
0.1U_0402_16V4Z

1
2
RP19 56_0404_4P2R_5%
14
23
C149
2.2U_0805_16V4Z

1
2
C164
0.1U_0402_16V4Z

1

2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_STP_CPU#
CLK_PCI_ICH PCI_ICH
H_STP_PCI#
CLKREF1
CLK_XTAL_IN
CLK_XTAL_OUT
FSB
FSA
PCIE_SATA
PCIE_SATA# CLK_PCIE_SATA#
CLK_PCIE_SATA
PCI_ICH
CLK_ENABLE#
CLK_ENABLE#
PCI_MINI

CLK_14M_ICH
PCI_EC
CK_VDD_48
CK_VDD_REF
CLK_14M_KBC
CLKREF1
CK_VDD_48
CK_VDD_REF
CLKIREF
MCH_3GPLL
MCH_3GPLL#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
ICH_SMBDATA
ICH_SMBCLK
FSB
CLK_PCIE_ICH#
CLK_PCIE_ICH
CPU_XDP
CPU_XDP#
CLKIREF
PCIE_ICH
PCIE_ICH#
CLK_48M_ICH
CLK_DEBUG_PORT PCI_MINI
FSA
PCI_EC
MCH_REF#
MCH_REF
CLK_MCH_REF#

CLK_MCH_REF
MCH_SSCDREFCLK#
MCH_SSCDREFCLKSSCDREFCLK
SSCDREFCLK#
CLK_48M_ICH
CLK_14M_ICH
CLK_PCI_ICH
CLK_14M_KBC
CLK_PCI_EC
CLKREF0
PCI_CBSCLK_33M_CBS
PCI_LPCCLK_33M_LPC
CLKREQC#
CLK_CPU_XDP#
CLK_CPU_XDP
CLK_DEBUG_PORT
CLK_33M_LPC
CLK_33M_CBS
PCI_CLK3
CLK_MCH_BCLK#
CLK_MCH_BCLK
MCH_BCLK#
MCH_BCLK
CPU_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CPU_BCLK
CLK_PCIE_MCARD
CLK_PCIE_MCARD#PCIE_MCARD#
PCIE_MCARD

CLKREQD#
CLKREQD#
CLKREQC#
CPU_BSEL2<5>
MCH_CLKSEL2 <7>
CPU_BSEL1<5>
MCH_CLKSEL1 <7>
CPU_BSEL0<5>
MCH_CLKSEL0 <7>
CLK_48M_ICH<20>
H_STP_PCI#<20>
H_STP_CPU#<20>
CLK_PCI_ICH<18>
ICH_SMBDATA<4,13,14,20,25>
ICH_SMBCLK<4,13,14,20,25>
CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>
CLK_DEBUG_PORT<25>
CLK_PCI_EC<30>
CLK_14M_KBC<30>
CLK_14M_ICH<20>
CLK_ENABLE#<40>
CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>
CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>
CLKREQC# <7>
CLK_MCH_REF#<7>
CLK_MCH_REF<7>
MCH_SSCDREFCLK <7>

MCH_SSCDREFCLK# <7>
CLK_33M_CBS<24>
CLK_33M_LPC<31>
CLK_CPU_XDP# <4>
CLK_CPU_XDP <4>
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
CLK_CPU_BCLK# <4>
CLK_CPU_BCLK <4>
CLK_PCIE_MCARD <25>
CLK_PCIE_MCARD# <25>
CLKREQD# <25>
+3VS
+3VS
+CK_VDD_DP
+CK_VDD_DP
+3VS
+CK_VDD_DP
+3VS
+CK_VDD_MAIN2
+CK_VDD_MAIN1
+3VS
+VCCP
+VCCP
+VCCP
+3VS
+3VS +3VS
+CK_VDD_MAIN1
+3VS
Title

Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Clock generator
15 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Place crystal within
500 mils of CK410
Routing the trace at least 10mil
LCD(Low)/SRC(High)
clock select
High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP
High:Pin44/45 = CLKREQ
Pin44/45 function select
CLK_Ra
CLK_Rb
CLK_Rc
CLK_Rd

CLK_Re
CLK_Rf
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.
When this time, docking PCI express will not work.
CLK_Rc
Stuff
CLK_Rf
CLK_Ra
CLK_Re
CLK_Re
Stuff
CLK_Ra
FSB Frequency Selet:
No Stuff
CLK_Rb
No Stuff
533MHz
CLK_Rf
CLK_Rc
CLK_Re
CLK_Rd
CLK_Ra
CLK_Rd
CLK_Rc
CPU Driven
No Stuff
CLK_Rb
Stuff
CLK_Rd

CLK_Rb
667MHz
*
(Default)
1
1000
CLKSEL1
100
0
PCI
MHz
133
0
Table : ICS954306
SRC
MHz
33.3
CPU
MHz
CLKSEL2
33.31
FSLA
CLKSEL0
166
FSLC
1
FSLB
*
*
Place close to U4

Place near U4
Place these components
near each pin within 40
mils.
Must fine tune12/08
12/05 ICS recommend
CLK_Rf
12/25
12/25
12/25
T32
PAD
R142
10K_0402_5%@
12
C185
5P_0402_50V8C@
12
R119 33_0402_5%

12
R123 24_0402_5%

1 2
C178
0.1U_0402_16V4Z

1
2
R134 24_0402_5%

1 2
Y1
14.31818MHZ_16P

12
R146
10K_0402_5%@
12
R112
1K_0402_5%
1 2
R87 0_0805_5%

1 2
R99
8.2K_0402_5%

12
R133
0_0402_5%

1 2
R98 24_0402_5%

1 2
R102 24_0402_5%

1 2
R135 24_0402_5%
1 2

C186 33P_0402_50V8J

12
R130
1K_0402_5%

1 2
R103
0_0402_5%

1 2
C175
4.7P_0402_50V8C@
12
C172
0.01U_0402_16V7K
1
2
R100
1K_0402_5%

1 2
C174
4.7P_0402_50V8C@
12
C180
4.7P_0402_50V8C@
12
J1
NO SHORT PADS

12
R126 10K_0402_5%NOXDP@
12
C182
0.1U_0402_16V4Z

1
2
R125
1K_0402_5%
1 2
R104 33_0402_5%

12
R115 24_0402_5%
1 2
R136
0_0402_5%
@
12
R92 0_0402_5%LP@
1 2
C170
10U_0805_10V4Z

1
2
R2171 33_0402_5%

12

R118
0_0402_5%

1 2
C190
0.1U_0402_16V4Z@
1
2
R147
10K_0402_5%@
12
R89
2.2_0805_1%

1 2
R2227
0_0402_5%NOXDP@
12
R86 0_0805_5%

1 2
R140 24_0402_5%

1 2
R117
33_0402_5%DEBUG@
12
R113 24_0402_5%
1 2
R144

10K_0402_5%
12
R120
0_0402_5%
@
12
R94 0_0402_5%LP@
1 2
R108 24_0402_5%
1 2
C173
0.01U_0402_16V7K
1
2
R97
56_0402_5%
@
1 2
C176
4.7P_0402_50V8C@
12
C169
5P_0402_50V8C@
12
C191
1000P_0402_50V4Z@
1 2
R129
8.2K_0402_5%

12
R2206 24_0402_5%XDP@
1 2
R12724_0402_5%
12
C1457
4.7P_0402_50V8C@
12
R88
1_0805_1%
1 2
R13124_0402_5%
12
C1461
1000P_0402_50V4Z@
1 2
C1456
4.7P_0402_50V8C@
12
R105
1K_0402_5%
12
R116
1K_0402_5%

1 2
C184
0.1U_0402_16V4Z

1

2
R96 24_0402_5%

1 2
C189
0.1U_0402_16V4Z

1
2
T33
PAD
C179
0.1U_0402_16V4Z

1
2
R95 24_0402_5%

1 2
R106 24_0402_5%
1 2
R121 33_0402_5%

12
R128
0_0402_5%
NOXDP@
12
C187 33P_0402_50V8J

12
C171
0.01U_0402_16V7K
1
2
C177
10U_0805_10V4Z

1
2
R143
10K_0402_5%
12
R141 24_0402_5%

1 2
R122 10K_0402_5%@
12
R124 24_0402_5%

1 2
C188
0.1U_0402_16V4Z

1
2
R114 33_0402_5%

12
R107

910_0402_1%

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
U4
ICS9LP306_TSSOP64
*SEL_PCI1/PCICLK3
1
**SEL_SATA1/PCICLK4
2
**SEL_SATA2/PCICLK5
3
GND
4
VDDPCI
5
PCI/SRC_STOP#
8
PCICLK6
6
**SEL_LCDCLK#/PCICLK_F1
7
FSLA/USB_48MHz
11
SATACLKT
28
DOTT_96MHz
13
VDD48
10

Vtt_PwrGd#/PD
9
SRCCLKC3
27
SRCCLKT3
26
SATACLKC
29
GND
17
GND
12
SRCCLKC1
21
SRCCLKT1
20
LCDCLK_SSC/SRCCLKC0
19
LCDCLK_SST/SRCCLKT0
18
SRCCLKT2
22
CPUCLKC0
51
CPU_STOP#
61
REF0/PCICLK1
60
FSLC/TEST_SEL/REF1
59

VDDREF
55
VDDCPU
50
VDD
16
FSLB/TEST_MODE
15
DOTC_96MHz
14
X2
56
X1
57
SCLK
53
CPUCLKT0
52
*REQ_SEL/PCICLK2
62
*CLKREQB#
63
*CLKREQA#
64
GNDSRC
40
SATA1/SRCCLKC4
31
SATA1/SRCCLKT4
30

SDATA
54
CPUCLKT1
49
CPUCLKC1
48
VDDSRC
24
GNDSRC
25
GNDCPU
47
SRCCLKC2
23
IREF
46
*CPUCLKT2_ITP/CLKREQC#
45
*CPUCLKC2_ITP/CLKREQD#
44
SRCCLKT8
43
SRCCLKC8
42
GNDSATA
32
VDDSRC
41
GND
58

SRCCLKT7
39
SRCCLKC7
38
SRCCLKT6
37
SRCCLKC6
36
SATA2/SRCCLKT5
35
SATA2/SRCCLKC5
34
VDDSATA
33
R111
33_0402_5%

12
R2226 10K_0402_5%NOXDP@
12
R101 33_0402_5%

12
R93
0_0402_5%@
12
C181
10U_0805_10V4Z

1

2
C183
0.1U_0402_16V4Z

1
2
R90
0_0805_5%
1 2
R220910K_0402_5%

12
C1469
0.1U_0402_16V4Z

1
2
R1133 24_0402_5%XDP@
1 2
R145
300_0402_5%
12
A
A
B
B
C
C
D
D

E
E
1 1
2 2
3 3
4 4
SMBCLK
SMBDAT CRT_SMBDAT
CRT_SMBCLK
SMBCLK
SMBDAT
CRT_RED
CRT_HSYNCRFL
CRTL_G
CRT_VSYNCRFL
CRTL_B
CRTL_R
HSYNC
CRT_BLU
CRT_GRN
VSYNC
CRT_RED<9>
CRT_GRN<9>
CRT_BLU<9>
HSYNC<9>
VSYNC<9>
CRT_SMBCLK <9>
CRT_SMBDAT <9>
CRT_VCC
+5VS

+2.5VS
+5VS
+5VS CRT_VCC
+3VS
+3VS
R_CRT_VCC
+5VS +5VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
CRT Connector
16 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
CRT CONNECTOR
12/26
C1482 close to U6,
C1483 close to JP6
0119 HSYNC VSYN

、
C refernece +5VS
C201
0.1U_0402_16V4Z
1
2
L8
FBMA-L11-160808-800LMT_0603
1 2
D9
DAN217_SC59@
2
3
1
C202
10P_0402_50V8J
1
2
C198
22P_0402_50V8J
1
2
U5
74AHCT1G125GW_SOT353-5
A
2
Y
4
OE#
1

G
3
P
5
R156
4.7K_0402_5%
C203
10P_0402_50V8J
1
2
R153
2.2K_0402_5%
12
C199
22P_0402_50V8J
1
2
D5
DAN217_SC59
@
2
3
1
G
D
S
Q4
2N7002_SOT23
2
1 3

R152 0_0402_5%
12
C200
22P_0402_50V8J
1
2
D8
DAN217_SC59@
2
3
1
R150
75_0402_1%

12
L5 BK2125LL121_0805
1 2
C196
10P_0402_50V8J
1
2
C195
10P_0402_50V8J
1
2
R154
2.2K_0402_5%
12
R151 0_0402_5%
12

C205
0.1U_0402_16V4Z
1
2
C1483
0.1U_0402_16V4Z
1
2
C1482
0.1U_0402_16V4Z
1
2
D10
RB411D_SOT23
2 1
C197
10P_0402_50V8J
1
2
C206
220P_0402_25V8K
1
2
D6
DAN217_SC59
@
2
3
1
F1

1A_6VDC_MINISMDC110
21
R148
75_0402_1%

12
C207
220P_0402_25V8K
1
2
L4 BK2125LL121_0805
1 2
L7
FBMA-L11-160808-800LMT_0603
1 2
R155
4.7K_0402_5%
D7
DAN217_SC59
@
2
3
1
L6 BK2125LL121_0805
1 2
JP6
SUYIN_070912FR015S207CR
6
11
1

7
12
2
8
13
3
9
14
4
10
15
5
16
17
G
D
S
Q3
2N7002_SOT23
2
1 3
U6
74AHCT1G125GW_SOT353-5
A
2
Y
4
OE#
1
G

3
P
5
R149
75_0402_1%

12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVDSA2-
LVDSA2+
LVDSA0-
LVDSA0+
LVDSA1-
LVDSA1+
INVTPWM
DISPLAYOFF#
DAC_BRIG

LVDSAC-
LVDSAC+
LVDSB0-
LVDSB0+
LVDSBC-
LVDSBC+
LVDSB1-
LVDSB1+
LVDSB2-
LVDSB2+
LCD_CLK
LCD_DAT
DAC_BRIG
DISPLAYOFF#
INVTPWM
ENAVDD<9>
LVDSA2- <9>
LVDSA0+ <9>
LVDSA2+ <9>
LVDSA0- <9>
LVDSA1- <9>
LVDSA1+ <9>
LVDSAC- <9>
LVDSAC+ <9>
LVDSB0+<9>
LVDSB0-<9>
LVDSBC+<9>
LVDSBC-<9>
LVDSB1+<9>
LVDSB1-<9>

LVDSB2+<9>
LVDSB2-<9>
BKLT_CTL<9>
INV_PWM<30>
LCD_CLK <9>
LCD_DAT <9>
LID_SW#<30,32>
DISPLAYOFF# <30>
ENABLT<9,30>
+5VALW
+LCDVDD
+3VS+LCDVDD
+LCDVDD
INVPWR_B+B+
+3VS
INVPWR_B+
+LCDVDD
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
LCD CONN.
17 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
LVDS CONN
11/21
LVDS connector
LCD/PANEL BD. CONN.
12/28
L9 0_0805_5%

1 2
C217
680P_0402_50V7K
12
R157
100_0402_5%
12
C211
4.7U_0805_10V4Z
1
2
C210
4.7U_0805_10V4Z
1

2
JP7
ACES_88107-4000G
CONN@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12

14
16
18
20
22
24
26
28
30
32
34
36
38
40
R2189
1.8K_0603_1%
G
D
S
Q6
2N7002_SOT23
2
13
R2247
100K_0402_5%

1 2
C209
0.1U_0402_16V4Z
1

2
C212
0.047U_0402_16V7K

R163
3.3K_0402_5%

1 2
R158
47K_0402_5%
1 2
C208
0.1U_0402_16V4Z
1
2
U29
TC7SH08FU_SSOP5
@
B
1
A
2
Y
4
P
5
G
3
R166
0_0402_5%

@
1 2
L10
FBMA-L11-201209-221LMA30T_0805
@
1 2
R162 100K_0402_5%@
12
G
D
S
Q5
SI2301BDS_SOT23
2
1 3
R161
0_0402_5%
1 2
R2190
1K_0402_1%

12
C216
680P_0402_50V7K
12
U7
NC7SZ14M5X_SOT23-5@
A
2
G

3
Y
4
P
5
C214680P_0402_50V7K
12
R160
0_0402_5%
@
1 2
C213
0.1U_0402_16V4Z
1
2
R159
47K_0402_5%
1 2
C215680P_0402_50V7K

1
2
G
D
S
Q7
2N7002LT1G_SOT23
2
13
C218

680P_0402_50V7K
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_ICH
PCI_SERR#
PCI_DEVSEL#
PCI_PCIRST#
PCI_CBE#0
PCI_PERR#
PCI_PIRQG#
PCI_PIRQB#
PCI_STOP#
PCI_CBE#1
PCI_CBE#3
PCI_PIRQF#
PCI_PIRQC#

PCI_REQ2#
PCI_PIRQE#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_CBE#2
PCI_REQ1#
PCI_REQ0#
PCI_PIRQD#
PCI_PIRQA#
PCI_PAR
PCI_TRDY#
PCI_PIRQH#
PCI_PLTRST#
CLK_PCI_ICH
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD7
PCI_AD6
PCI_AD8
PCI_AD9
PCI_AD11
PCI_AD10
PCI_AD14
PCI_AD15
PCI_AD13

PCI_AD12
PCI_AD16
PCI_AD17
PCI_AD19
PCI_AD18
PCI_AD22
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD25
PCI_AD24
PCI_AD28
PCI_AD29
PCI_AD31
PCI_AD30
PCI_AD26
PCI_AD27
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_IRDY#
PCI_PLOCK#
PCI_SERR#
PCI_PERR#
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQH#

PCI_PIRQG#
PCI_PIRQF#
PCI_PIRQE#
PCI_REQ0#
PCI_REQ2#
PCI_REQ5#
PCI_REQ1#
PCI_GNT2#
PCI_REQ4#
PCI_REQ3#
PCI_PCIRST#
PCI_PLTRST#
PCI_REQ5#
PCI_REQ3#
PCI_REQ4#
PCI_RST#
PLT_RST#
GNT5#
GNT5#
ICH_GPIO48
ICH_GPIO48
PCI_AD[0 31]<24>
PCI_PIRQC#<24>
PCI_CBE#0 <24>
PCI_CBE#1 <24>
PCI_CBE#2 <24>
PCI_CBE#3 <24>
PCI_IRDY# <24>
PCI_PAR <24>
PCI_DEVSEL# <24>

PCI_PERR# <24>
PCI_STOP# <24>
PCI_TRDY# <24>
PCI_FRAME# <24>
CLK_PCI_ICH <15>
PCI_SERR# <24,30>
PCI_RST# <24>
PLT_RST# <7,20,22,24,25,30,31>
PCI_GNT2# <24>
PCI_REQ2# <24>
MCH_ICH_SYNC# <7>
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
ICH7-M(1/4)

18 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Place closely pin A9
Boot BIOS destination
The pad must be placed on PCB easily
contact space for BIOS team setting.
LPC@
SPI@ (Default)
PCI@
GNT5# GNT4#
01
10
11
GNT5# and GNT4# have internal pull high 20K
Change to RP before SI phase
12/27
C219
8.2P_0402_50V@
1
2
R168 8.2K_0402_5%

1 2
R170 8.2K_0402_5%

1 2
R180 8.2K_0402_5%

1 2

R190 8.2K_0402_5%

1 2
R185 8.2K_0402_5%

1 2
R178 8.2K_0402_5%

1 2
R2228 8.2K_0402_5%

1 2
R167 8.2K_0402_5%

1 2
R186 8.2K_0402_5%

1 2
R187 8.2K_0402_5%

1 2
R189 8.2K_0402_5%

1 2
R1290
1K_0402_5%
12
U31
TC7SH08FU_SSOP5
@

B
1
A
2
Y
4
P
5
G
3
R171 8.2K_0402_5%

1 2
R172 8.2K_0402_5%

1 2
R176 8.2K_0402_5%

1 2
R177
0_0402_5%

12
R182 8.2K_0402_5%

1 2
Interrupt I/F
PCI
MISC
U8B

ICH7_BGA652~D
FRAME#
F16
GPIO17 / GNT5#
D8
TRDY#
F14
STOP#
F15
GPIO2 / PIRQE#
G8
GPIO3 / PIRQF#
F7
GPIO4 / PIRQG#
F8
GPIO5 / PIRQH#
G7
C/BE0#
B15
C/BE1#
C12
C/BE2#
D12
C/BE3#
C15
IRDY#
A7
PAR
E10
PCIRST#

B18
DEVSEL#
A12
PERR#
C9
PLOCK#
E11
SERR#
B10
PIRQC#
C5
RSVD[4]
AH4
PIRQA#
A3
RSVD[5]
AD9
RSVD[2]
AD5
RSVD[3]
AG4
PIRQB#
B4
PIRQD#
B5
RSVD[1]
AE5
REQ0#
D7
GNT0#

E7
REQ1#
C16
GNT1#
D16
REQ2#
C17
GNT2#
D17
REQ3#
E13
GNT3#
F13
REQ4# / GPIO22
A13
GNT4# / GPIO48
A14
GPIO1 / REQ5#
C8
AD0
E18
AD1
C18
AD2
A16
AD3
F18
AD4
E16
AD5

A18
AD6
E17
AD7
A17
AD8
A15
AD9
C14
AD10
E14
AD11
D14
AD12
B12
AD13
C13
AD14
G15
AD15
G13
AD16
E12
AD17
C11
AD18
D11
AD19
A11
AD20

A10
AD21
F11
AD22
F10
AD23
E9
AD24
D9
AD25
B9
AD26
A8
AD27
A6
AD28
C7
AD29
B6
AD30
E6
AD31
D6
RSVD[6]
AE9
RSVD[7]
AG8
RSVD[8]
AH8
RSVD[9]

F21
MCH_SYNC#
AH20
PLTRST#
C26
PCICLK
A9
PME#
B19
R169 8.2K_0402_5%

1 2
R173 8.2K_0402_5%

1 2
R181 8.2K_0402_5%

1 2
R175 8.2K_0402_5%

1 2
R183 8.2K_0402_5%

1 2
R188 8.2K_0402_5%

1 2
R179 8.2K_0402_5%

1 2

R191
10_0402_5%@
1 2
R174 8.2K_0402_5%

1 2
U30
TC7SH08FU_SSOP5
@
B
1
A
2
Y
4
P
5
G
3
R184
0_0402_5%

12
5
5
4
4
3
3
2

2
1
1
D D
C C
B B
A A
PD_DREQ
H_A20M#
H_INIT#
H_IGNNE#
H_INTR
H_NMI
PD_D9
PD_D2
PD_D15
PD_D0
PD_IOR#
DPRSLP#
LPC_FRAME#
PD_A1
PD_D14
PD_A2
PD_IOW#
PD_D6
PD_A0
PD_D13
PD_D10
PD_D8
PD_D1

PD_D7
PD_D4
LPC_AD3
PD_D12
PD_D3
THRMTRIP_ICH#
PD_D5
LPC_AD0
PD_D11
PD_DACK#
PD_CS#1
SM_INTRUDER#
H_CPUSLP_R#
H_PWRGOOD
H_SMI#
LPC_AD2
PD_CS#3
LPC_AD1
ICH_INTVRMEN
PD_IRQ
PD_IORDY
ICH_RTCX2
ICH_INTVRMEN
RTC_R
H_FERR#
GATEA20
KB_RST#
ICH_RTCX1
CLK_PCIE_SATA#
CLK_PCIE_SATA

SATA_RXN0_C
SATA_RXP0_C
SATA_TXP0_C
SATA_TXN0_C
H_STPCLK#
DPSLP#
ICH_RTCRST#
PD_IORDY
PD_IRQ
PD_D[0 15]
AC97RST#
AC97_SYNC
AC97_SDIN0
AC97_SDOUT
EEP_CS
EEP_SK
EEP_DOUT
EEP_DIN
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
LAN_JCLK
LAN_TXD2
LAN_TXD1
LAN_TXD0
AC97_BITCLK

AC97_BITCLK
LPC_AD[0 3] <25,30,31>
H_A20M# <4>
H_DPRSTP# <4,40>
H_DPSLP# <4>
H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>
H_INIT# <4>
H_INTR <4>
H_SMI# <4>
H_NMI <4>
H_STPCLK# <4>
GATEA20 <30>
KB_RST# <30>
H_THERMTRIP# <4,7>
LPC_FRAME# <25,30,31>
CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>
PD_DACK#<22>
PD_IOW#<22>
PD_IOR#<22>
PD_IORDY<22>
PD_IRQ<22>
PD_DREQ <22>
PD_D[0 15] <22>
SATA_RXP0_C<22>
SATA_TXN0_C<22>
SATA_TXP0_C<22>
ACZ_SDOUT<26>

ACZ_SDIN0<26>
ACZ_SYNC<26>
ACZ_BITCLK<26>
ACZ_RST#<26>
SATA_RXN0_C<22>
PD_A0 <22>
PD_A1 <22>
PD_A2 <22>
PD_CS#1 <22>
PD_CS#3 <22>
LAN_RXD0<23>
LAN_RXD1<23>
LAN_RXD2<23>
LAN_TXD0<23>
LAN_TXD1<23>
LAN_RSTSYNC<23>
LAN_JCLK<23>
LAN_TXD2<23>
+VCCP
+RTCVCC
+RTCVCC
+VCCP
+RTCVCC
+3VS
+3VS
+RTCVCC
+3VL
+3VALW
+3VS
+3VS

+3VALW+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
ICH7-M(2/4)
19 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
W=20mils
Place close to ICH7
EMI
W=20mils
-+
11/21
LPCRQ0# Delete(For SIO Request pin) 11/20
FWH_INIT# Delete 11/20
Change to LAN power plane 12/11
12/26
12/26

R2230
0_0402_5%
12
R212
0_0402_5%@
12
R194
1M_0402_5%

1 2
C1449
33P_0402_50V8J
1
2
C225
1U_0603_10V4Z
1
2
D11
DAN202U_SC70
2
3
1
R211
332K_0402_1%

12
RTC
LAN
SATA

AC-97/AZALIA
LPCCPU
IDE
U8A
ICH7_BGA652~D
RTXC1
AB1
RTCX2
AB2
RTCRST#
AA3
INTVRMEN
W4
INTRUDER#
Y5
EE_CS
W1
EE_SHCLK
Y1
EE_DOUT
Y2
EE_DIN
W3
LAN_CLK
V3
LAN_RSTSYNC
U3
LAN_RXD0
U5
LAN_RXD1

V4
LAN_RXD2
T5
LAN_TXD0
U7
LAN_TXD1
V6
LAN_TXD2
V7
ACZ_BCLK
U1
ACZ_SYNC
R6
ACZ_RST#
R5
ACZ_SDIN0
T2
ACZ_SDIN1
T3
ACZ_SDIN2
T1
ACZ_SDOUT
T4
SATALED#
AF18
SATA0RXN
AF3
SATA0RXP
AE3
SATA0TXN

AG2
SATA0TXP
AH2
SATA2RXN
AF7
SATA2RXP
AE7
SATA2TXN
AG6
SATA2TXP
AH6
SATA_CLKN
AF1
SATA_CLKP
AE1
SATARBIASN
AH10
SATARBIASP
AG10
IORDY
AG16
IDEIRQ
AH16
DDACK#
AF16
DIOW#
AH15
DIOR#
AF15
LAD0

AA6
LAD1
AB5
LAD2
AC4
LAD3
Y6
LDRQ0#
AC3
LDRQ1# / GPIO23
AA5
LFRAME#
AB3
A20GATE
AE22
A20M#
AH28
CPUSLP#
AG27
TP1 / DPRSTP#
AF24
TP2 / DPSLP#
AH25
FERR#
AG26
GPIO49 / CPUPWRGD
AG24
IGNNE#
AG22
INIT3_3V#

AG21
INIT#
AF22
INTR
AF25
RCIN#
AG23
SMI#
AF23
NMI
AH24
STPCLK#
AH22
THERMTRIP#
AF26
DA0
AH17
DA1
AE17
DA2
AF17
DCS1#
AE16
DCS3#
AD16
DD0
AB15
DD1
AE14
DD2

AG13
DD3
AF13
DD4
AD14
DD5
AC13
DD6
AD12
DD7
AC12
DD8
AE12
DD9
AF12
DD10
AB13
DD11
AC14
DD12
AF14
DD13
AH13
DD14
AH14
DD15
AC15
DDREQ
AE15
R196 0_0402_5%

12
R214
1K_0402_5%
1 2
C223
0.1U_0402_16V4Z
1
2
R2213 10K_0402_5%
12
R192
10M_0402_5%
12
R2210
33_0402_5%
1 2
R2195
33_0402_5%

1 2
R210
332K_0402_1%@
12
R198 56_0402_5%

12
C221
15P_0402_50V8J
1 2
JP8

SUYIN_060003FA002TX00NL~D
+
1
-
2
C224
10P_0402_25V8K
@
1
2
R2088.2K_0402_5%
12
R200 10K_0402_5%
12
R213
100_0402_5%

1 2
R2231
0_0402_5%
@
12
U10
AT93C46-10SI-2.7_SO8
CS
1
SK
2
DI
3

DO
4
VCC
8
NC
7
NC
6
GND
5
C222
1U_0603_10V4Z

1 2
R195 10K_0402_5%
12
R204 24.9_0402_1%

1 2
ZZZ1
PCB_MB_rev01
R20133_0402_5%

12
R205 33_0402_5%

1 2
T15
PAD
R202

56_0402_5%

12
Y2
32.768KHZ_12.5P_MC-146

1 4
2 3
R2074.7K_0402_5%
12
JOPEN1
SHORT PADS
1 2
R2197
33_0402_5%

1 2
BATT1
CR2032 RTC BATTERY
BATT@
R209
24.9_0402_1%

1 2
C220
15P_0402_50V8J
1 2
R2196
33_0402_5%

1 2
R199
10_0402_5%
@
1 2
C1448
33P_0402_50V8J
1
2
R203 0_0402_5%

12
R197 0_0402_5%
12
C1447
33P_0402_50V8J
1
2
R193
20K_0402_5%

1 2
T16
PAD
5
5
4
4
3
3

2
2
1
1
D D
C C
B B
A A
LINKALERT#
OCP#
THERM_SCI#
SIRQ
PM_CLKRUN#
THERM_SCI#
CLK_48M_ICH
PM_BMBUSY#
CLK_14M_ICH
H_STP_CPU#
PWROK_ICH7
SLP_S3#
XDP_DBRESET#
CLK_48M_ICH
CLK_14M_ICH
ICH_RI#
SIRQ
SLP_S5#
OCP#
PM_CLKRUN#
SB_SPKR
LINKALERT#

H_STP_PCI#
ICH_SMLINK0
ICH_SMLINK1
DPRSLPVR
ON/OFFBTN#
PM_POK
ICH_SUSCLK
DPRSLPVR
DMI_TXN3
DMI_TXN0
USBRBIAS
DMI_TXP1
USB_OC#2
USB_OC#4
DMI_TXP2
USB_OC#3
DMI_TXN1
DMI_RXN1
USB_OC#1
DMI_TXP3
DMI_RXP1
DMI_RXN3
CLK_PCIE_ICH
DMI_RXN2
DMI_RXN0
DMI_TXP0
DMI_RXP3
CLK_PCIE_ICH#
DMI_TXN2
DMI_RXP0

DMI_RXP2
USB20_N1
USB20_P1
ICH_LOW_BAT#
DMI_IRCOMP
LPC_PD#
PM_RSMRST#
SLP_S4#
USB_OC#0
RUNSCI_EC#
USB_OC#5
XMIT_OFF#
SPI_CS#
SPI_CLK
ICH_SMBCLK ICH_SMB_CLK
ICH_SMB_DATAICH_SMBDATA
ICH_SMB_DATA
ICH_SMBCLK
ICH_SMBDATA
ICH_SMB_CLK
XDP_DBRESET# PWROK_ICH7
USB_OC#6
USB_OC#7
SPI_CS#
SPI_SI
SPI_SO
USB20_N0
USB20_P0
USB_OC#0
USB_OC#1

ICH_PCIE_WAKE#
SPI_SO
LID_OUT#
LID_OUT#
SPI_SI
PCIE_C_TXP2
PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
LAN_RST_R#
LAN_RST_R#
USB_OC#1
USB_OC#3
USB_OC#5
USB_OC#0
USB_OC#4
USB_OC#2
USB_OC#6
USB_OC#7
PM_CLKRUN#<24,30>
H_STP_PCI#<15>
H_STP_CPU#<15>
PM_BMBUSY#<7>
SIRQ<24,30>
THERM_SCI#<4>
SLP_S3# <30,33,39>
SLP_S5# <33,38>
DPRSLPVR <7,40>
DMI_RXN0 <7>
DMI_RXP0 <7>

DMI_TXN0 <7>
DMI_TXP0 <7>
DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>
DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>
DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>
CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
PM_RSMRST# <24,30>
ON/OFFBTN# <32>
CLK_48M_ICH <15>
CLK_14M_ICH <15>
USB20_N1 <29>
USB20_P1 <29>
LOW_BAT# <30>
XDP_DBRESET#<4>
OCP#<4,30,42>
LPC_PD#<30>
SLP_S4# <38>
RUNSCI_EC#<30>
XMIT_OFF# <25,31>
SPI_CS#<31>

SPI_CLK<31>
ICH_SMBCLK<4,13,14,15,25>
ICH_SMBDATA<4,13,14,15,25>
VGATE_INTEL<7,40>
PM_POK<7,30>
SB_SPKR<26>
USB20_N0 <29>
USB20_P0 <29>
USB_OC# <29>
ICH_PCIE_WAKE#<25>
SPI_SO<31>
SPI_SI<31>
LID_OUT# <30>
PCIE_TXP2<25>
PCIE_RXN2<25>
PCIE_RXP2<25>
PCIE_TXN2<25>
PLT_RST# <7,18,22,24,25,30,31>
LAN_RST# <30>
+3VALW
+3VS
+3VALW
+1.5VS
+3VALW
+3VL
+3VALW
+3VALW
+3VS
+3VS
+3VALW

+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
ICH7-M(3/4)
20 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Place closely pin B2 Place closely pin AC1
Within 500 mils
Within 500 mils
R246 should be placed
less than 100 mils from U8
R232 need be removed when ICH7M ES2 samples used,
but need be stuffed when ICH7M ES1 samples used.
R249,R250 and R251 should
be placed close to U8.
R217,R218 change from 2.2Kohm to

10Kohm when Q23,Q24,R206,R204 stuffed.
12/05 Change to +3VS
12/26
12/26
12/26
R222
0_0402_5%
@
1 2
R217
4.7K_0402_5%
T19PAD
T18PAD
R244 0_0402_5%@
1 2
G
D
S
Q10
RHU002N06_SOT323
2
13
R215
10_0402_5%@
12
R241
10K_0402_5%
1 2
R231
1K_0402_5%

1 2
R2232 0_0402_5%
1 2
R246
47_0402_5%
1 2
RP34
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R242
10K_0402_5%
1 2
R223 100_0402_5%

1 2
C227
4.7P_0402_50V8C@
1
2
R245 24.9_0402_1%

1 2
C226
4.7P_0402_50V8C@
1
2
R235

8.2K_0402_5%

1 2
R234
10K_0402_5%
1 2
RP33
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
PCI-EXPRESS
DIRECT MEDIA INTERFACE
USB
SPI
U8D
ICH7_BGA652~D
SPI_CLK
R2
SPI_CS#
P6
SPI_ARB
P1
SPI_MOSI
P5
SPI_MISO
P2
DMI0RXN
V26

DMI0RXP
V25
DMI0TXN
U28
DMI0TXP
U27
DMI1RXN
Y26
DMI1RXP
Y25
DMI1TXN
W28
DMI1TXP
W27
DMI2RXN
AB26
DMI2RXP
AB25
DMI2TXN
AA28
DMI2TXP
AA27
DMI3RXN
AD25
DMI3RXP
AD24
DMI3TXN
AC28
DMI3TXP
AC27

DMI_CLKN
AE28
DMI_CLKP
AE27
DMI_ZCOMP
C25
DMI_IRCOMP
D25
PERn1
F26
PERp1
F25
PETn1
E28
PETp1
E27
PERn2
H26
PERp2
H25
PETn2
G28
PETp2
G27
PERn3
K26
PERp3
K25
PETn3
J28

PETp3
J27
PERn4
M26
PERp4
M25
PETn4
L28
PETp4
L27
PERn5
P26
PERp5
P25
PETn5
N28
PETp5
N27
PERn6
T25
PERp6
T24
PETn6
R28
PETp6
R27
OC0#
D3
OC1#
C4

OC2#
D5
OC3#
D4
OC4#
E5
OC5# / GPIO29
C3
OC6# / GPIO30
A2
OC7# / GPIO31
B3
USBP0N
F1
USBP0P
F2
USBP1N
G4
USBP1P
G3
USBP2N
H1
USBP2P
H2
USBP3N
J4
USBP3P
J3
USBP4N
K1

USBP4P
K2
USBP5N
L4
USBP5P
L5
USBP6N
M1
USBP6P
M2
USBP7N
N4
USBP7P
N3
USBRBIAS#
D2
USBRBIAS
D1
R251 10K_0402_5%
1 2
R220
10K_0402_5%

1 2
R250 10K_0402_5%
1 2
R230
10K_0402_5%@
1 2
C2290.1U_0402_16V4ZWLAN@

12
T21 PAD
T20 PAD
R232
100K_0402_5%@
12
C2280.1U_0402_16V4ZWLAN@
12
R2233 0_0402_5%@
1 2
R2219
47_0402_5%
1 2
T22
PAD
R226
8.2K_0402_5%

1 2
R227
10K_0402_5%

1 2
R219
10K_0402_5%

1 2
R229
10K_0402_5%
12

G
D
S
Q11
RHU002N06_SOT323
2
13
R243 0_0402_5%@
1 2
R248 22.6_0402_1%
1 2
R237
10K_0402_5%
1 2
SATA
POWER MGT
SYS
SMB
GPIO
Clocks
GPIO
GPIO
U8C
ICH7_BGA652~D
RI#
A28
SPKR
A19
SYS_RST#
A22

SUS_STAT#
A27
GPIO0 / BM_BUSY#
AB18
GPIO26
A21
GPIO27
B21
GPIO28
E23
GPIO32 / CLKRUN#
AG18
GPIO33 / AZ_DOCK_EN#
AC19
GPIO34 / AZ_DOCK_RST#
U2
VRMPWRGD
AD22
GPIO11 / SMBALERT#
B23
SUSCLK
C20
SLP_S3#
B24
SLP_S4#
D23
SLP_S5#
F22
PWROK
AA4

GPIO16 / DPRSLPVR
AC22
TP0 / BATLOW#
C21
PWRBTN#
C23
LAN_RST#
C19
RSMRST#
Y4
GPIO21 / SATA0GP
AF19
GPIO19 / SATA1GP
AH18
GPIO36 / SATA2GP
AH19
GPIO37 / SATA3GP
AE19
CLK14
AC1
CLK48
B2
GPIO9
E20
GPIO10
A20
GPIO12
F19
GPIO13
E19

GPIO14
R4
GPIO15
E22
GPIO24
R3
GPIO25
D20
GPIO35 / SATAREQ#
AD21
GPIO38
AD20
GPIO39
AE20
SMBCLK
C22
SMBDATA
B22
LINKALERT#
A26
SMLINK0
B25
SMLINK1
A25
GPIO18 / STPPCI#
AC20
GPIO20 / STPCPU#
AF21
WAKE#
F20

SERIRQ
AH21
THRM#
AF20
GPIO6
AC21
GPIO7
AC18
GPIO8
E21
D12
CH751H-40_SC76

2 1
R249 10K_0402_5%
1 2
R240 0_0402_5%@
1 2
T17 PAD
R218
4.7K_0402_5%
R216
10_0402_5%@
12
R239 0_0402_5%
1 2
R233 10K_0402_5%

1 2
R238

10K_0402_5%
1 2
R224
2.2K_0402_5%
12
R221
0_0402_5%
@
1 2
R228
8.2K_0402_5%
12
R225
2.2K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_V5REF_SUS

ICH_V5REF_RUN
ICH_V5REF_RUN
ICH_V5REF_SUS
ICH_AA2
ICH_Y7
ICH_K7
ICH_C28
ICH_G20
+1.5VS_DMIPLL
VCCSUSHDA
VCCSUSHDA
VCCLAN3_3
+3VALW
+VCCP
+3VS
+1.5VS
+RTCVCC
+1.5VS
+1.5VS
+3VS+5VS
+3VALW+5VALW
+3VS
+1.5VS
+1.5VS
+3VS
+3VS
+3VALW
+3VALW
+1.5VS
+VCCP

+1.5VS
+1.5VS_DMIPLL+1.5VS_DMIPLLR
+3VS
+1.5VS
+3VS
+3VALW
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
ICH7-M(4/4)
21 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Place closely pin
D28,T28,AD28.
Place closely pin AG28 within 100mlis.
Place closely pin AG5.

Place closely pin AG9.
Change 150uF to 220uF 12/04
12/25
12/25
T25PAD
R2235 0_0402_5%
1 2
C252
0.1U_0402_16V4Z

1
2
U8F
ICH7_BGA652~D
V5REF[1]
G10
V5REF[2]
AD17
V5REF_Sus
F6
Vcc1_5_B[1]
AA22
Vcc1_5_B[2]
AA23
Vcc1_5_B[3]
AB22
Vcc1_5_B[4]
AB23
Vcc1_5_B[5]
AC23

Vcc1_5_B[6]
AC24
Vcc1_5_B[7]
AC25
Vcc1_5_B[8]
AC26
Vcc1_5_B[9]
AD26
Vcc1_5_B[10]
AD27
Vcc1_5_B[11]
AD28
Vcc1_5_B[12]
D26
Vcc1_5_B[13]
D27
Vcc1_5_B[14]
D28
Vcc1_5_B[15]
E24
Vcc1_5_B[16]
E25
Vcc1_5_B[17]
E26
Vcc1_5_B[18]
F23
Vcc1_5_B[19]
F24
Vcc1_5_B[20]
G22

Vcc1_5_B[21]
G23
Vcc1_5_B[22]
H22
Vcc1_5_B[23]
H23
Vcc1_5_B[24]
J22
Vcc1_5_B[25]
J23
Vcc1_5_B[26]
K22
Vcc1_5_B[27]
K23
Vcc1_5_B[28]
L22
Vcc1_5_B[29]
L23
Vcc1_5_B[30]
M22
Vcc1_5_B[31]
M23
Vcc1_5_B[32]
N22
Vcc1_5_B[33]
N23
Vcc1_5_B[34]
P22
Vcc1_5_B[35]
P23

Vcc1_5_B[36]
R22
Vcc1_5_B[37]
R23
Vcc1_5_B[38]
R24
Vcc1_5_B[39]
R25
Vcc1_5_B[41]
T22
Vcc1_5_B[42]
T23
Vcc1_5_B[43]
T26
Vcc1_5_B[44]
T27
Vcc1_5_B[45]
T28
Vcc1_5_B[46]
U22
Vcc1_5_B[47]
U23
Vcc1_5_B[48]
V22
Vcc1_5_B[49]
V23
Vcc1_5_B[50]
W22
Vcc1_5_B[52]
Y22

Vcc1_5_B[53]
Y23
Vcc1_5_B[51]
W23
Vcc1_5_B[40]
R26
Vcc3_3[1]
B27
VccDMIPLL
AG28
VccSATAPLL
AD2
Vcc3_3[2]
AH11
Vcc1_05[1]
L11
Vcc1_05[2]
L12
Vcc1_05[3]
L14
Vcc1_05[4]
L16
Vcc1_05[6]
L18
Vcc1_05[5]
L17
Vcc1_05[7]
M11
Vcc1_05[8]
M18

Vcc1_05[9]
P11
Vcc1_05[10]
P18
Vcc1_05[11]
T11
Vcc1_05[12]
T18
Vcc1_05[13]
U11
Vcc1_05[14]
U18
Vcc1_05[15]
V11
Vcc1_05[16]
V12
Vcc1_05[17]
V14
Vcc1_05[18]
V16
Vcc1_05[19]
V17
Vcc1_05[20]
V18
Vcc3_3 / VccHDA
U6
VccSus3_3/VccSusHDA
R7
V_CPU_IO[1]
AE23

V_CPU_IO[2]
AE26
V_CPU_IO[3]
AH26
Vcc3_3[3]
AA7
Vcc3_3[4]
AB12
Vcc3_3[5]
AB20
Vcc3_3[6]
AC16
Vcc3_3[7]
AD13
Vcc3_3[8]
AD18
Vcc3_3[9]
AG12
Vcc3_3[10]
AG15
Vcc3_3[11]
AG19
Vcc3_3[12]
A5
Vcc3_3[14]
B16
Vcc3_3[15]
B7
Vcc3_3[16]
C10

Vcc3_3[13]
B13
Vcc3_3[17]
D15
Vcc3_3[18]
F9
Vcc3_3[19]
G11
Vcc3_3[20]
G12
VccRTC
W5
VccSus3_3[1]
P7
VccSus3_3[2]
A24
VccSus3_3[4]
D19
VccSus3_3[5]
D22
VccSus3_3[6]
G19
VccSus3_3[3]
C24
VccSus3_3[7]
K3
VccSus3_3[8]
K4
VccSus3_3[9]
K5

VccSus3_3[10]
K6
VccSus3_3[11]
L1
Vcc1_5_A[19]
AB17
Vcc1_5_A[20]
AC17
Vcc1_5_A[21]
T7
Vcc1_5_A[22]
F17
Vcc1_5_A[23]
G17
Vcc1_5_A[24]
AB8
Vcc1_5_A[25]
AC8
VccSus1_05[1]
K7
Vcc1_5_A[1]
AB7
Vcc1_5_A[2]
AC6
Vcc1_5_A[3]
AC7
Vcc1_5_A[4]
AD6
Vcc1_5_A[5]
AE6

Vcc1_5_A[6]
AF5
Vcc1_5_A[7]
AF6
Vcc1_5_A[8]
AG5
Vcc1_5_A[9]
AH5
Vcc1_5_A[10]
AB10
Vcc1_5_A[11]
AB9
Vcc1_5_A[12]
AC10
Vcc1_5_A[13]
AD10
Vcc1_5_A[14]
AE10
Vcc1_5_A[15]
AF10
Vcc1_5_A[16]
AF9
Vcc1_5_A[17]
AG9
Vcc1_5_A[18]
AH9
VccSus3_3[19]
E3
VccUSBPLL
C1

VccSus1_05/VccLAN1_05[1]
AA2
VccSus1_05/VccLAN1_05[2]
Y7
VccSus3_3/VccLAN3_3[1]
V5
VccSus3_3/VccLAN3_3[2]
V1
VccSus3_3/VccLAN3_3[3]
W2
VccSus3_3/VccLAN3_3[4]
W7
Vcc3_3[21]
G16
VccSus3_3[12]
L2
VccSus3_3[13]
L3
VccSus3_3[14]
L6
VccSus3_3[15]
L7
VccSus3_3[16]
M6
VccSus3_3[17]
M7
VccSus3_3[18]
N7
VccSus1_05[2]
C28

VccSus1_05[3]
G20
Vcc1_5_A[26]
A1
Vcc1_5_A[27]
H6
Vcc1_5_A[28]
H7
Vcc1_5_A[29]
J6
Vcc1_5_A[30]
J7
C264
0.1U_0402_16V4Z

1
2
C241
0.1U_0402_16V4Z

1 2
C263
0.1U_0402_16V4Z

1
2
C243
0.1U_0402_16V4Z

1

2
C261 0.1U_0402_16V4Z

1 2
+
C231
330U_D2E_2.5VM_R9@
1
2
C245
0.1U_0402_16V4Z

1
2
R254
0.5_0805_1%

1 2
D13
CH751H-40_SC76

21
C256
10U_0805_10V4Z

1
2
C235
0.1U_0402_16V4Z

1
2
C260
0.1U_0402_16V4Z

1
2
C237
0.1U_0402_16V4Z

1
2
R255
0_0805_5%

1 2
D14
CH751H-40_SC76

21
C239
0.1U_0402_16V4Z
@
1
2
C232
1U_0603_10V4Z

1
2

C247
0.1U_0402_16V4Z

1
2
R22370_0402_5% @
12
C242
0.1U_0402_16V4Z

1 2
C233
0.1U_0402_16V4Z

1
2
C238
0.1U_0402_16V4Z

1
2
C254
0.1U_0402_16V4Z

1
2
T24PAD
T27 PAD
C258
0.1U_0402_16V4Z

1
2
+
C230
220U_D2_2VM_R9
1
2
C259
0.1U_0402_16V4Z

1
2
R2234 0_0402_5%@
1 2
C248
0.1U_0402_16V4Z

1
2
C236
0.1U_0402_16V4Z

1
2
U8E
ICH7_BGA652~D
VSS[0]
A4
VSS[1]

A23
VSS[2]
B1
VSS[3]
B8
VSS[4]
B11
VSS[5]
B14
VSS[6]
B17
VSS[7]
B20
VSS[8]
B26
VSS[9]
B28
VSS[10]
C2
VSS[11]
C6
VSS[12]
C27
VSS[13]
D10
VSS[14]
D13
VSS[15]
D18
VSS[16]

D21
VSS[17]
D24
VSS[18]
E1
VSS[19]
E2
VSS[21]
E4
VSS[22]
E8
VSS[23]
E15
VSS[24]
F3
VSS[25]
F4
VSS[26]
F5
VSS[27]
F12
VSS[28]
F27
VSS[29]
F28
VSS[30]
G1
VSS[31]
G2
VSS[32]

G5
VSS[33]
G6
VSS[34]
G9
VSS[35]
G14
VSS[36]
G18
VSS[37]
G21
VSS[38]
G24
VSS[39]
G25
VSS[40]
G26
VSS[41]
H3
VSS[42]
H4
VSS[43]
H5
VSS[44]
H24
VSS[45]
H27
VSS[46]
H28
VSS[47]

J1
VSS[48]
J2
VSS[49]
J5
VSS[50]
J24
VSS[51]
J25
VSS[52]
J26
VSS[53]
K24
VSS[54]
K27
VSS[55]
K28
VSS[56]
L13
VSS[57]
L15
VSS[58]
L24
VSS[59]
L25
VSS[60]
L26
VSS[61]
M3
VSS[62]

M4
VSS[63]
M5
VSS[64]
M12
VSS[65]
M13
VSS[66]
M14
VSS[67]
M15
VSS[68]
M16
VSS[69]
M17
VSS[70]
M24
VSS[71]
M27
VSS[72]
M28
VSS[73]
N1
VSS[74]
N2
VSS[75]
N5
VSS[76]
N6
VSS[77]

N11
VSS[78]
N12
VSS[79]
N13
VSS[80]
N14
VSS[81]
N15
VSS[82]
N16
VSS[83]
N17
VSS[84]
N18
VSS[85]
N24
VSS[86]
N25
VSS[87]
N26
VSS[88]
P3
VSS[89]
P4
VSS[90]
P12
VSS[91]
P13
VSS[92]

P14
VSS[93]
P15
VSS[94]
P16
VSS[95]
P17
VSS[96]
P24
VSS[97]
P27
VSS[98]
P28
VSS[99]
R1
VSS[100]
R11
VSS[101]
R12
VSS[102]
R13
VSS[103]
R14
VSS[104]
R15
VSS[105]
R16
VSS[106]
R17
VSS[107]

R18
VSS[108]
T6
VSS[109]
T12
VSS[110]
T13
VSS[111]
T14
VSS[112]
T15
VSS[113]
T16
VSS[114]
T17
VSS[115]
U4
VSS[116]
U12
VSS[117]
U13
VSS[118]
U14
VSS[119]
U15
VSS[120]
U16
VSS[121]
U17
VSS[122]

U24
VSS[123]
U25
VSS[124]
U26
VSS[125]
V2
VSS[126]
V13
VSS[127]
V15
VSS[128]
V24
VSS[129]
V27
VSS[130]
V28
VSS[131]
W6
VSS[132]
W24
VSS[133]
W25
VSS[134]
W26
VSS[135]
Y3
VSS[136]
Y24
VSS[137]

Y27
VSS[138]
Y28
VSS[139]
AA1
VSS[140]
AA24
VSS[141]
AA25
VSS[142]
AA26
VSS[143]
AB4
VSS[144]
AB6
VSS[145]
AB11
VSS[146]
AB14
VSS[147]
AB16
VSS[148]
AB19
VSS[149]
AB21
VSS[150]
AB24
VSS[151]
AB27
VSS[152]

AB28
VSS[153]
AC2
VSS[154]
AC5
VSS[155]
AC9
VSS[156]
AC11
VSS[157]
AD1
VSS[158]
AD3
VSS[159]
AD4
VSS[160]
AD7
VSS[161]
AD8
VSS[162]
AD11
VSS[163]
AD15
VSS[164]
AD19
VSS[165]
AD23
VSS[166]
AE2
VSS[167]

AE4
VSS[168]
AE8
VSS[169]
AE11
VSS[170]
AE13
VSS[171]
AE18
VSS[172]
AE21
VSS[173]
AE24
VSS[174]
AE25
VSS[175]
AF2
VSS[176]
AF4
VSS[177]
AF8
VSS[178]
AF11
VSS[179]
AF27
VSS[180]
AF28
VSS[181]
AG1
VSS[182]

AG3
VSS[183]
AG7
VSS[184]
AG11
VSS[185]
AG14
VSS[186]
AG17
VSS[187]
AG20
VSS[188]
AG25
VSS[189]
AH1
VSS[190]
AH3
VSS[191]
AH7
VSS[192]
AH12
VSS[193]
AH23
VSS[194]
AH27
R253
10_0402_5%

12
C246

0.1U_0402_16V4Z

1
2
C266
0.1U_0402_16V4Z

1
2
C257
0.01U_0402_16V7K

1
2
R252
100_0402_5%

12
+
C234
220U_D2_2VM_R9

1
2
C249
0.1U_0402_16V4Z

1
2
T23PAD

T26 PAD
C265
0.1U_0402_16V4Z

1
2
R22360_0402_5%
12
C240
0.1U_0402_16V4Z

1
2
C262
1U_0603_10V4Z

1
2
C244
4.7U_0805_10V4Z

1 2
C253
0.1U_0402_16V4Z

1
2
C255
0.1U_0402_16V4Z

1
2
C251
0.1U_0402_16V4Z

1
2
C250
0.1U_0402_16V4Z

1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SATA_TXN0
SATA_TXP0_C SATA_TXP0
SATA_RXP0
SATA_RXN0

SATA_RXP0_C
SATA_RXN0_C
PD_A2
PD_DREQ
PD_D[0 15]
PD_CS#3
PD_IOR#
PD_DACK#
PDIAG#
PD_D14
PD_D15
PD_D13
PD_D10
PD_D12
PD_D11
PD_D9
PD_D8
PD_CS#1
PLT_RST#
PD_A0
PD_A1
PD_IRQ
PD_IOW#
PD_IORDY
PRI_CSEL
PD_D6
PD_D7
PD_D4
PD_D5
PD_D3

PD_D2
PD_D0
PD_D1
IDE_ACT#
IDE_ACT#
SATA_TXN0_C
SATA_TXN0
SATA_RXN0
SATA_TXP0
SATA_RXP0
PD_A2 <19>
PD_IOR# <19>
PD_CS#3 <19>
PD_D[0 15] <19>
PD_DACK# <19>
PD_DREQ <19>
PD_IORDY<19>
PD_IOW#<19>
PD_IRQ<19>
PD_A1<19>
PD_A0<19>
PD_CS#1<19>
PLT_RST#<7,18,20,24,25,30,31>
SATA_RXN0_C<19>
SATA_TXN0_C<19>
SATA_RXP0_C<19>
SATA_TXP0_C<19>
+5VS
+5VS
+5VS

+5VS
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
HDD & ODD
22 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Near ICH7(U26) side.
Near Device(JP45) side.
SATA CONN
CD-ROM Connector
11/21
Placea caps. near ODD CONN.
11/21
12/26
C269

10U_0805_10V4Z
1
2
C272 3900P_0402_50V7K
1 2
C270
0.1U_0402_16V4Z
1
2
JP9
OCTEK_HDD-22SC1G_44P_RVCONN@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
V33
8
V33
9
V33

10
GND
11
GND
12
GND
13
V5
14
V5
15
V5
16
GND
17
Reserved
18
GND
19
V12
20
V12
21
V12
22
+
C1450
330U_D2E_2.5VM_R9
@
1

2
R259
10K_0402_5%

1 2
C267 3900P_0402_50V7K
1 2
R257
100K_0402_5%
1 2
C1454
10U_0805_10V4Z
1
2
C273 3900P_0402_50V7K
1 2
JP10
OCTEK_CDR-50TA1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24

25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
GND
53
GND
54
C1452
1U_0603_10V4Z

1
2
C274
0.1U_0402_16V4Z
12
R256 33_0402_5%
12
R258
470_0402_5%
1 2

C268 3900P_0402_50V7K
1 2
C1453
10U_0805_10V4Z

1
2
C271
0.1U_0402_16V4Z
1
2
C1451
0.1U_0402_16V4Z

1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A

RDP
MDO0-
MDO0+
MDO1+
MDO1-
MDO1+
MDO1-
MDO0+
MDO0-
RDN
RDP
TDN
TDP
MCT1
MCT0 RJ45_GND
TIP
LAN_RXD2
LAN_RXD1
LAN_RXD0 RDN
RDP
TDN
TDP
RDN
RING
TIP
RING
LAN1_XO
LAN1_XI
TDN
RDN

TDP
RDP
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_RSTSYNC
LAN_TXD0
LAN_TXD1
LAN_TXD2
+3V_LAN
ACTLED#
ACTLED#
LINK_LED100#
LINK_LED100#
LANJCLK LAN_JCLK
LAN_RXD2 <19>
LAN_RXD1 <19>
LAN_RXD0 <19>
LAN_RSTSYNC <19>
LAN_TXD2 <19>
LAN_TXD1 <19>
LAN_TXD0 <19>
LAN_JCLK <19>
+3VALW
+3VALW
+3VS
+3VS
+3VLAN
+3VLAN
+3VS

+3VALW
+3VLAN
+3VLAN
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
82562EZ LAN
Custom
23 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
close to U13
RJ11
RJ45
close to U12chip(Intel rule)close to U12chip(Intel rule)
Don't Support wake on LAN R267 R268
、
Support wake on LAN R263,R269
8/18 for EMI

15 mil
12/28
02/07 Follow 82562GT design guide
R261
110_0402_1%@
1 2
C277
33P_0402_50V8J
1
2
R270 47_0402_5%
12
R262
110_0402_1%
1 2
C1471
0.1U_0402_16V4Z
1
2
JP11
SUYIN_100073FR012S100ZL
CONN@
PR1-
2
PR1+
1
PR2+
3
PR3+
4

PR3-
5
PR2-
6
PR4+
7
PR4-
8
Green LED+
9
Green LED-
10
Amber LED+
11
Amber LED-
12
SHLD1
13
SHLD2
14
SHLD4
16
SHLD3
15
R2207
0_0603_5%

1 2
C283
0.1U_0402_16V4Z

@
1
2
C1472
0.1U_0402_16V4Z
1
2
JP13
ACES_85205-0200
CONN@
1
2
C294
470P_1808_3KV
1
2
R269
300_0603_5%
@
1 2
C1477
0.1U_0402_16V4Z
1
2
C279
22P_0402_50V8J

1 2
R263
300_0603_5%

@
1 2
C278
33P_0402_50V8J
1
2
C284
0.1U_0402_16V4Z
1
2
R266
33_0402_5%

1 2
U13
NS0013_16P
RD+
1
RD-
2
CT
3
CT
6
TD+
7
TD-
8
TX-
9

TX+
10
CT
11
CT
14
RX-
15
RX+
16
R2254
0_0603_5%
12
C1474
0.1U_0402_16V4Z
1
2
R2208
0_0603_5%

1 2
RJ11 CABLE
@
R267
300_0603_5%
1 2
R264
33_0402_5%

1 2

R273
75_0402_5%
12
C276
33P_0402_50V8J
1
2
C1470
10U_0805_6.3V4Z

1
2
C1473
0.1U_0402_16V4Z
1
2
C1459
680P_0402_50V7K
1 2
R277 200_0402_5%
1 2
Y3
25MHZ_20P_1BG25000CK1A
1 2
C281
68P_0402_50V8K

1 2
C293
470P_1808_3KV

1
2
U12
82562GT_SSOP48
VCC
1
VCCA
2
RBIAS10
4
RBIAS100
5
VCCA2
7
VCCT
9
TDP
10
TDN
11
VCCT
12
VCCT
14
RDP
15
RDN
16
VCCT
17

VCCR
19
VCCR
23
VCC
25
TOUT
26
LILED#
27
SPDLED#
31
ACTLED#
32
JRXD0
34
JRXD1
35
VCCP
36
JRXD2
37
JCLK
39
VCCP
40
JRSTSYNC
42
JTXD0
43

JTXD1
44
JTXD2
45
X1
46
X2
47
ISOL_TI
28
ISOL_TCK
30
ISOL_EXEC
29
TESTEN
21
ADV10
41
VSS
8
VSS
13
VSS
18
VSS
24
VSS
48
VSSP
33

VSSP
38
VSSA
3
VSSA2
6
VSSR
20
VSSR
22
R274 649_0402_1%
1 2
C1476
0.1U_0402_16V4Z
1
2
C1475
0.1U_0402_16V4Z
1
2
JP12
FOX_JM74613-P2002-7F~D
CONN@
1
1
2
2
GND1
3
GND2

4
L20
FBMA-L11-160808-601LMT 0603
@
12
R275 619_0402_1%
1 2
R265
33_0402_5%

1 2
R268
300_0603_5%
1 2
R272
75_0402_5%
12
L11
FBMA-L11-160808-601LMT 0603
12
R271
0_0402_5%
@
1 2
C282
1000P_1206_2KV7K
12
C1458
680P_0402_50V7K
1 2

C280
22P_0402_50V8J

1 2
C1478
10U_0805_6.3V4Z

1
2
C275
68P_0402_50V8K

12
R260
110_0402_1%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4

S1_A23PCI_AD31
PCI_AD29
PCI_AD30
PCI_AD5
PCI_AD0
PCI_AD17
PCI_AD21
PCI_AD18
PCI_AD28
PCI_AD7
PCI_AD19
PCI_AD8
PCI_AD9
PCI_AD25
PCI_AD27
PCI_AD3
PCI_AD2
PCI_AD22
PCI_AD26
PCI_AD24
PCI_AD12
PCI_AD14
PCI_AD13
PCI_AD23
PCI_AD20
PCI_AD16
PCI_AD10
PCI_AD11
PCI_AD6
PCI_AD15

PCI_AD1
PCI_AD4
VCCD1#
VPPD1
VCCD0#
VPPD0
PCI_AD[0 31]
S1_D8
PCI_AD22
S1_D3
S1_D4
S1_D11
S1_D12
S1_D5
S1_D6
S1_D13
S1_A11
S1_A10
S1_CE2#
S1_D7
S1_IORD#
S1_D15
S1_A6
S1_IOWR#
S1_A17
S1_A9
S1_A24
S1_A7
S1_A25
S1_A3

S1_A2
S1_A4
S1_A5
S1_A0
S1_D0
S1_A1
S1_D9
S1_D1
S1_OE#
VCCD1#
VCCD0#
VPPD1
VPPD0
S1_WP
S1_REG#
S1_A8
S1_CE1#
S1_A12
S1_RST
S1_A15
S1_A22
S1_A23
S1_A21
S1_A14
S1_WAIT#
S1_A20
S1_A16
S1_INPACK#
S1_WE#
S1_A13

S1_BVD1
S1_WP
S1_RDY#
S1_A19
S1_CD2#
S1_BVD2
S1_VS2
S1_CD1#
S1_VS1
CLK_33M_CBS
S1_D2
S1_A18
S1_D14
CLK_33M_CBS
S1_D10
PCI_CBE1#
PCI_CBE3#
PCI_CBE2#
PCI_CBE0#
S1_D14
S1_D5
S1_A6
S1_A12
S1_A3
S1_WAIT#
S1_BVD1
S1_WE#
S1_BVD2
S1_A13
S1_VS2

S1_D0
S1_A4
S1_D4
S1_A1
S1_A8
S1_INPACK#
S1_D15
S1_A19
S1_A24
S1_D6
S1_VS1
S1_A9
S1_A15
S1_CE2#
S1_D3
S1_A16
S1_A20
S1_IORD#
S1_A21
S1_A10
S1_A23
S1_A25
S1_A17
S1_D9
S1_A7
S1_OE#
S1_A18
S1_CE1#
S1_CD2#
S1_D13

S1_CD1#
S1_IOWR#
S1_A11
S1_A5
S1_D11
S1_RST
S1_D7
S1_D1
S1_D2
S1_A2
S1_RDY#
S1_D10
S1_A22
S1_D12
S1_WP
S1_REG#
S1_A14
S1_A0
S1_D8
PLT_RST#
PM_RSMRST#
CLK_33M_CBS<15>
PM_CLKRUN#<20,30>
SIRQ<20,30>
PCI_GNT2#<18>
CBS_SPK# <26>
PCI_AD[0 31]<18>
PCI_TRDY#<18>
PCI_DEVSEL#<18>
PCI_PAR<18>

PCI_STOP#<18>
PCI_FRAME#<18>
PCI_IRDY#<18>
PCI_PIRQC#<18>
PCI_SERR#<18,30>
PCI_RST#<18>
PCI_PERR#<18>
PCI_REQ2#<18>
PCI_CBE#1<18>
PCI_CBE#3<18>
PCI_CBE#2<18>
PCI_CBE#0<18>
PLT_RST#<7,18,20,22,25,30,31>
PM_RSMRST#<20,30>
S1_VCC
S1_VPP
+5V_CB
S1_VCC
S1_VPP
+3V_CB
+3V_CB
S1_VCC
S1_VCC
+3V_CB
S1_VCC
+3V_CB
S1_VCC
S1_VPP
S1_VCC
S1_VPP

+5VALW +5VALW +5VALW +5VALW +5VALW +5VALW
+3V_CB
+5VS
+5V_CB
+3VS
+3VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet
of
0.5
CardBus CTRL CB714
24 47Tuesday, March 20, 2007
Compal Electronics, Inc.
LA-3491P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Change to DAU00 PCI Devices ID
Cardbus >AD22
6/02
6/02
12/05 Follow IAT00 EMI Request
Don't Support wake on LAN L12, L13
Support wake on LAN L?, L?
12/27
C299
4.7U_1206_25VFZ

1
2
C302
680P_0402_50V7K
12
C310
1000P_0402_50V7K
1
2
JP14
FOX_WZ21131-G2-P4_LT
CONN@
GND
1
S1_D3
2
S1_D4
3
S1_D5
4
S1_D6
5
S1_D7
6
S1_CE1#
7
S1_A10
8
S1_OE#
9

S1_A11
10
S1_A9
11
S1_A8
12
S1_A13
13
S1_A14
14
S1_WE#
15
S1_RDY#
16
S1_VCC
17
S1_VPP
18
S1_A16
19
S1_A15
20
S1_A12
21
S1_A7
22
S1_A6
23
S1_A5
24

S1_A4
25
S1_A3
26
S1_A2
27
S1_A1
28
S1_A0
29
S1_D0
30
S1_D1
31
S1_D2
32
S1_WP
33
GND
34
GND
69
GND
71
GND
73
GND
75
GND
77

GND
79
GND
81
GND
83
GND
35
S1_CD1#
36
S1_D11
37
S1_D12
38
S1_D13
39
S1_D14
40
S1_D15
41
S1_CE2#
42
S1_VS1
43
S1_IORD#
44
S1_IOWR#
45
S1_A17
46

S1_A18
47
S1_A19
48
S1_A20
49
S1_A21
50
S1_VCC
51
S1_VPP
52
S1_A22
53
S1_A23
54
S1_A24
55
S1_A25
56
S1_VS2
57
S1_RST
58
S1_WAIT#
59
S1_INPACK#
60
S1_REG#
61

S1_BVD2
62
S1_BVD1
63
S1_D8
64
S1_D9
65
S1_D10
66
S1_CD2#
67
GND
68
GND
70
GND
72
GND
74
GND
76
GND
78
GND
80
GND
82
GND
84

C297
0.1U_0402_16V7K
1
2
C311
1000P_0402_50V7K
1
2
R280 22K_0402
1 2
C306
680P_0402_50V7K
1 2
C1468
0.047U_0402_16V4Z
1
2
C1465
0.01U_0402_16V7K
C305
0.1U_0402_16V7K
1
2
C301
0.1U_0402_16V7K
1
2
C298
0.1U_0402_16V7K
1

2
R282 33_0402_5%
1 2
U14
CP-2211_SSOP16
VCCD0
1
VCCD1
2
3.3V
3
3.3V
4
5V
5
5V
6
GND
7
OC
8
12V
9
VPP
10
VCC
11
VCC
12
VCC

13
VPPD1
14
VPPD0
15
SHDN
16
PQFP 144
22.2 X 22.2 X 1.60
U15
CB1410_LQFP144
REQ#
1
GNT#
2
AD31
3
AD30
4
AD29
5
GND1
6
AD28
7
AD27
8
AD26
9
AD25

10
AD24
11
C/BE3#
12
IDSEL
13
VCC7
14
AD23
15
AD22
16
AD21
17
VCCP1
18
AD20
19
RST#
20
PCLK
21
GND2
22
AD19
23
AD18
24
AD17

25
AD16
26
C/BE2#
27
FRAME#
28
IRDY#
29
VCC6
30
TRDY#
31
DEVSEL#
32
STOP#
33
PERR#
34
SERR#
35
PAR
36
C/BE1#
37
AD15
38
AD14
39
AD13

40
AD12
41
GND3
42
AD11
43
VCCP0
44
AD10
45
AD9
46
AD8
47
C/BE0#
48
AD7
49
VCC5
50
AD6
51
AD5
52
AD4
53
AD3
54
AD2

55
AD1
56
AD0
57
GND4
58
RI_OUT#/PME#
59
MFUNC0
60
MFUNC1
61
SPKOUT
62
VCCI
63
MFUNC2
64
MFUNC3
65
VCC/GRST#
66
MFUNC4
67
MFUNC5
68
MFUNC6
69
SUSPEND#

70
VPPD0
71
VPPD1
72
VCCD0#
73
VCCD1#
74
CCD1#/CD1#
75
CAD0/D3
76
CAD2/D11
77
GND5
78
CAD1/D4
79
CAD4/D12
80
CAD3/D5
81
CAD6/D13
82
CAD5/D6
83
RSVD/D14
84
CAD7/D7

85
VCC4
86
CAD8/D15
87
CC/BE0#/CE1#
88
CAD9/A10
89
VCCSK1
90
CAD10/CE2#
91
CAD11/OE#
92
CAD13/IORD#
93
GND6
94
CAD12/A11
95
CAD15/IOWR#
96
CAD14/A9
97
CAD16/A17
98
CC/BE1#/A8
99
RSVD/A18

100
CPAR/A13
101
VCC3
102
CBLOCK#/A19
103
CPERR#/A14
104
CSTOP#/A20
105
CGNT#/WE#
106
CDEVSEL#/A21
107
CCLK/A16
108
CTRDY#/A22
109
CIRDY#/A15
110
CFRAME#/A23
111
CC/BE2#/A12
112
CAD17/A24
113
GND7
114
CAD18/A7

115
CAD19/A25
116
CVS2/VS2#
117
CAD20/A6
118
CRST#/RESET
119
CAD21/A5
120
CAD22/A4
121
VCC2
122
CREQ#/INPACK#
123
CAD23/A3
124
CC/BE3#/REG#
125
VCCSK0
126
CAD24/A2
127
CAD25/A1
128
CAD26/A0
129
GND8

130
CVS1/VS1#
131
CINT#/READY
132
CSERR#/WAIT#
133
CAUDIO/BVD2
134
CSTSCHG/BVD1
135
CCLKRUN#/WP
136
CCD2#/CD2#
137
VCC1
138
CAD27/D0
139
CAD28/D8
140
CAD29/D1
141
CAD30/D9
142
RSVD/D2
143
CAD31/D10
144
R284 100_0402_5%

1 2
C308
0.1U_0402_16V7K
1
2
C295
4.7U_0805_10V4Z
1
2
R2250 0_0402_5%@
1 2
C300
0.1U_0402_16V4Z
1
2
L21
0_0805_5%
@
1 2
R281
47K_0402_5%
12
C1466
0.01U_0402_16V7K
L22
0_0805_5%
@
1 2
C1464
0.01U_0402_16V7K

C1467
0.047U_0402_16V4Z
1
2
C30710U_1206_16V4Z
1
2
C1463
0.01U_0402_16V7K
C304
0.1U_0402_16V7K
1
2
R287 0_0402_5%
1 2
R279 22K_0402
1 2
C303
4.7U_0805_10V4Z
1
2
R283 43K_0402_5%
C309
15P_0402_50V8J
@
1
2
R278
10K_0603_1%

12
C296
0.1U_0402_16V7K
1
2
L13
0_0805_5%
1 2
R285
10_0402_5%
@
12
L12
0_0805_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCIE_TXN2

XMIT_OFF#
CLK_PCIE_MCARD
PCIE_TXP2
CLK_PCIE_MCARD#
ICH_PCIE_WAKE#
CLKREQD#_MC
PCIE_C_RXP2
PCIE_C_RXN2PCIE_RXN2
PCIE_RXP2
LPC_AD0
LPC_AD3
LPC_AD2
PLT_RST#
LPC_AD1
CLK_PCIE_MCARD<15>
CLK_PCIE_MCARD#<15>
PLT_RST# <7,18,20,22,24,30,31>
ICH_SMBCLK <4,13,14,15,20>
ICH_SMBDATA <4,13,14,15,20>PCIE_TXN2<20>
PCIE_TXP2<20>
WL_LED# <31,32>
CLKREQD#<15>
PCIE_RXP2<20>
PCIE_RXN2<20>
LPC_AD[0 3] <19,30,31>
LPC_FRAME# <19,30,31>
CLK_DEBUG_PORT<15>
ICH_PCIE_WAKE#<20>
XMIT_OFF# <20,31>
STB_LED#<30,31,32>

NUM_LED#<30,31>
CAPS_LED#<30,31>
WL_LED_EC# <30>
+3VS +1.5VS
+1.5VS +3V_MINI
+3VALW
+3VALW
+3VS
+3VL
+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-3491P
0.5
Mini-Card
25 47Tuesday, March 20, 2007
2006/10/26 2006/07/26
Compal Electronics, Inc.
Mini-Express Card WLAN
Mini Card STANDOFF

12/25
12/26
12/26
02/26 Add R2270 for WL_LED_EC# PU
02/26 Add R2271 for use EC detect WLAN active
R299 0_0402_5%DEBUG@
1 2
R293
0_0402_5%DEBUG@
1 2
C317
0.1U_0402_16V4Z
WLAN@
1
2
R300 0_0402_5%DEBUG@
1 2
H28
HOLEA
1
R290
0_0402_5%DEBUG@
1 2
R289
0_0402_5%DEBUG@
1 2
R2271 0_0402_5%
WLAN@
1 2
C316

4.7U_0805_10V4Z
WLAN@
1
2
R288
0_0402_5%
WLAN@
1 2
C313
4.7U_0805_10V4Z
WLAN@
1
2
R2263 0_0402_5%@
1 2
R302 0_0402_5%DEBUG@
1 2
R294 0_0402_5%DEBUG@
1 2
JP15
MOLEX 67910-0002 52P
CONN@
1
1
2
2
3
3
4
4

5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19

20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34

35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49

50
50
51
51
52
52
GND1
53
GND2
54
L14
FBMA-L11-201209-102LMA10T
WLAN@
1 2
R297 0_0402_5%
WLAN@
1 2
C315
0.1U_0402_16V4Z
WLAN@
1
2
R301 0_0402_5%DEBUG@
1 2
C312
0.1U_0402_16V4Z
WLAN@
1
2
H27

HOLEA
1
C314
0.01U_0402_16V7K
WLAN@
1
2
R295 0_0402_5%
WLAN@
1 2
R291
0_0402_5%DEBUG@
1 2
R292
0_0402_5%DEBUG@
1 2
R2270
10K_0402_5%
WLAN@
12