Đề thi môn: ASSIGNMENT - 5 doc

1

Thuan Xuan Nguyen
Department of Electronics and Telecommunications
University of Science, Ho Chi Minh City
Vietnam National University, Ho Chi Minh City
Tel: (+84) 906 834 817
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ASSIGNMENT #5
Edited: Monday, April 25 2011

Exercise 1, 7: Use Vietnamese only.

1. Based on Section 6.3 – Circuit Pitfalls (page 379/1003), explain those concepts by using
images and examples.
a. Threshold Drops
b. Ratio Failures
c. Leakage
d. Charge Sharing
e. Power Supply Noise
f. Hot spots
g. Minority Carrier Injection
h. Back-gate Coupling
i. Diffusion Input Noise
Sensitivity
j. Process sensitivity

2. Design a fast 6-input OR gate in each of the following circuit families. Sketch an
implementation using two stages of logic (e.g., NOR6 + INV, NOR3 + NAND2, etc.). Label
each gate with the width of the pMOS and nMOS transistors. Each input can drive no more
than 30 lamda of transistor width. The output must drive a 60/30 inverter (i.e., an inverter with
a 60 lamda-wide pMOS and 30 lamda-width nMOS transistor). Use logical effort to choose
the topology and size for least average delay. Estimate this delay using logical effort. When
estimating parasitic delays, count only the diffusion capacitance on the output node.
a. Static CMOS
b. Pseudo-nMOS with pMOS transistors ¼ the strength of the pull-down stack
c. Domino (a footed dynamic gate followed by a HI-skewed inverter); only optimize the
delay from rising input to rising output

3. Prove that the P/N ratio that gives lowest average delay in a logic gate is a square root of the
ratio that gives equal rise and fall delays.

4. Sketch a pseudo-nMOS gate that implements the function
   

    

   











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Calculate the g
u
, g
d
, g
avg
, p
u

, p
d
, p
avg
of this circuit.

5. Sketch a 3-input dual-rail domino majority/minority gate. This is often used in domino full
adder cells. Recall that the majority function is true if more that half of the inputs are true.

6. Sketch 3-input XOR functions using each of the following circuit techniques and give the
comparison of them (ref. 6.6. Comparison of Circuit Families):
a. Static CMOS
b. Pseudo-nMOS
c. Dual-rail domino
d. CPL
e. EEPL
f. DCVSPG
g. SRPL
h. PPL
i. DPL
j. LEAP
2

7. In May, 2011, Intel made one its most significant technology announcements ever today by
stating it will base upcoming processors on 3D transistors. So, what is a 3D transistor exactly
and why is it important? Represent your answer in about 500 words (use images to illustrate
your answer).