Logic Cadence VHDL and Verilog Simulation Guide and Tutorial doc

Cadence VHDL/Verilog Simulation Guide and Tutorial
for use at the University of Cincinnati
Wei Yang
January 2003
(Updated Jan 04, H. Carter)
This guide describes, via a tutorial, how to set up the personal environment (paths and
evnrionment variables), and simulate VHDL (or Verilog) models using the Cadence
tools. The tutorial describes VHDL simulation, but Verilog simulation should be
identical except that the model files traditionally end in .v rather than .vhd or .vhdl. The
Cadence simulator can simulate either or both VHDL and Verilog models.
The Cadence tools were initially acquired in 2001 and have been gaining increasing use
as educators and researchers in the Electrical and Computer Engineering and Computer
Science (ECECS) department have become familiar with them. All of the Cadence tools
and documentation are located in /opt/CAD/Cadence/ and can be executed only from
Sun workstations served by the department servers. Since these tools are commercially
licensed, please do not point any URL's to them from public websites.
This guide is presented in three sections:
1. How to set up your environment to view the documents and run the simulator tools.
You can skip this section if your environment is already set up to access the Cadence
tools.
2. Executing the VHDL/Verilog simulator. Two approaches can be used to simulate
VHDL/Verilog models: 1) manually executing a series of three programs to compile,
elaborate, and simulate the models, or 2) using a GUI to perform the simulation. We
describe both methods.
3. How to visualize the simulation results.
How to Set Up Your Environment to Access Cadence Tools and
Documents
The Cadence tool set actually consists of a set of tool suites. For example, there is the
integrated circuit design suite which resides in the IC directory. For out purposes, we are
interested in the VHDL/Verilog simulation tools which are in the LDV directory.
For the instructions given below on adding path and enviornment information to the

initialization files, all Cadence tools are included just in case you will unltimately need
other than simulation tools in the future.
Using a standard text editor like emacs or vi, add the following lines to your .cshrc or .
cshrc.local initialization file after the first set path command (which looks something
like set path=(/bin /usr/bin /usr/ucb /etc .) . You will be using csh or tcsh (preferred)
as your working shell. If you usually use sh or bash, you should execute tcsh when you
execute Cadence tools.
Accessing Cadence Documentation
Before we simulate a model, it may be helpful to describe how to access the
documentation. To read Cadence documentation online, execute cdsdoc.
A small window should appear that looks like:
set path=($path /usr/local/bin) # to access netscape (reqd by cdsdoc)
set path=($path /opt/gnu/bin) # to access emacs
set path=($path /opt/X11/bin) # to access X11 tools
set cpath="/opt/CAD/Cadence"
set path=($cpath/LDV/tools/bin $path) # VHDL simulator
set path=($cpath/IC/tools/dfII/bin $path)
set path=($cpath/IC/tools/bin $path)
set path=($cpath/DSM-SE/tools/bin $path)
set path=($cpath/ICC/tools/bin $path)
set path=($cpath/NCSU_CDK/bin $path)
set path=($cpath/NEOCELL/tools/NeoCell/bin $path)
set path=($cpath/PSD/tools/bin $path)
set path=($cpath/SPR/tools/bin $path) # Place and Route
set path=($cpath/SPR/BuildGates/v4.0-s008/bin $path) # BuildGates
Synth
set path=($cpath/SPW/tools/bin $path)
set path=($cpath/VCC/tools/bin $path)
setenv CLS_CDSD_COMPATIBILITY_LOCKING NO
setenv DD_DONT_DO_OS_LOCKS set

unsetenv LM_LICENSE_FILE
Select the tool suite you want to view documentation in the top selector. I find the “Docs
by type” to be the best viewing style. Expand “Manuals” in the window to see the list of
documentation available. Select the document you want and it will display as a pdf file.
Setting up to Execute the Cadence VHDL/Verilog Simulator
Before executing the simulator for the first time, it is necessary to create the working
directory and two small files to inform the simulator where some key information is
located.
1. Create a project directory named, say, project, in your home directory.
mkdir project
You will do all of your simulation work in this directory. For our example here,
we assume project is a subdirectory of /home/youraccount/eces681.
2. cd to /home/youraccount/eces681/project and create directory worklib
cd project
mkdir worklib
3. In the project directory, create a file named cds.lib with the following two
lines:
4. In the project directory, create a file named hdl.var which has two lines as
follows:
5. Finally, create your VHDL or Verilog files in the project directory. If the
models were developed elsewhere, move them to the project directory.
At this point you should copy all of the files in
/ to your project directory. The
rest of this tutorial uses these files.
Executing the Cadence VHDL/Verilog Simulator
Now we're ready to simulate. There are two ways to do it: 1) manually where we execute
a sequence of three programs that compile, elaborate, and simulate the model, or 2) use a
graphical interface to execute the three programs. The graphical interface approach also
provides a graphical capability to view the simulation results.
At this point you should copy

Manual Approach
Assume the model to be simulated consists of three files: packages.vhd,
testbench.vhd, and dtmf_recvr_core.vhd . The testbench model described in
testbench.vhd instantiates the dtmf_recvr model described in dtmf_recvr_core.vhd as
a component. Both testbench and dtmf_recvr use objects and types described in
packages.vhd.
Further, let the top- most entity of the model be dtmf_recvr_core_test which has a single
architecture called behavior. Then simulate the model as follows:
1. Compile the model.
ncvhdl –messages packages.vhd dtmf_recvr_core.vhd testbench.vhd
1. The -message option produces additional information as the program executes.
2. -linedebug adds information in the compiled components to enable debugging
during execution.
3. The files shown in the command line must be in appropriate compilation order.

You should see the output:
Include /opt/CAD/Cadence/LDV/tools/inca/files/cds.lib
define worklib ./worklib
define WORK worklib
define VHDL_SUFFIX(.vhd,.vhdl)
ncvhdl: v03.20.(s013): (c) Copyright 1995 - 2001 Cadence Design
Systems, Inc.
packages.vhd:
errors: 0, warnings: 0
dtmf_recvr_core.vhd:
errors: 0, warnings: 0
testbench.vhd:
errors: 0, warnings: 0
WORKLIB.TDSP_P (package):
streams: 1, words: 2259

WORKLIB.ARB_P (package):
streams: 1, words: 76
<additional 40 or so similar lines>
WORKLIB.DTMF_RECVR_CORE_TEST (entity):
streams: 1, words: 3
WORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIOR (architecture):
streams: 1, words: 459
WORKLIB.DTMF_RECVR_CORE_TEST:GATE_TEST (architecture):
streams: 1, words: 460
2. Elaborate the model
Elaboration consists of connecting the units that were compiled, and establishing
some initial conditions. Note that the top compiled unit is listed in the output
above as the second- to-last item:
(WORKLIB. DTMF_RECVR_CORE_TEST:BEHAVIOR )
ncelab -messages worklib.dtmf_recvr_core_test:behavior
The following output is displayed:
ncelab: v03.20.(s013): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
Elaborating the design hierarchy:
ncelab: *W,CUDEFB: default binding occurred for component instance
(:dtmf_recvr_core_test(behavior):TOP) with design unit
(WORKLIB.DTMF_RECVR_CORE:RTL).
ncelab: *W,CUDEFB: default binding occurred for component instance
(:dtmf_recvr_core_test(behavior):TOP@dtmf_recvr_core(rtl):ROM_INST) with
design unit (WORKLIB.ROM_512X16:BEHAVIORAL).
<additional 20 or so lines>
ncelab: *W,CUDEFB: default binding occurred for component instance
(:dtmf_recvr_core_test(behavior):TOP@dtmf_recvr_core(rtl):
TEST_CONTROL_INST) with design unit
(WORKLIB.TEST_CONTROL:RTL).
Building instance specific data structures.

Design hierarchy summary:
Instances Unique
Components: 27 26
Default bindings: 15 -
Processes: 130 130
Signals: 292 292
Writing initial simulation snapshot:
WORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIOR
3. Simulate the Model
We now have a single, elaborated model in worklib with the name
dtmf_recvr_core_test:behavior as shown in the last line of output from the
elaboration execution. To simulate the model, execute:
ncsim worklib.dtmf_recvr_core_test:behavior
The following output is displayed:
ncsim: v03.20.(s013): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
ncsim> source /opt/CAD/Cadence/LDV-3.2/tools/inca/files/ncsimrc
ncsim> run
ASSERT/WARNING (time 0 FS) from package ieee.STD_LOGIC_ARITH, this builtin
function called from function @ieee.std_logic_signed:"/="
Built-in relational argument contains a ('U', 'X', 'W', 'Z', '-') in an operand.
ASSERT/WARNING (time 0 FS) from package ieee.STD_LOGIC_ARITH, this builtin
function called from function @ieee.std_logic_signed:"="
Built-in relational argument contains a ('U', 'X', 'W', 'Z', '-') in an operand.
<some more lines>
ASSERT/WARNING (time 902 NS) from package ieee.STD_LOGIC_ARITH, this
builtin function called from function @ieee.std_logic_signed:"="
Built-in relational argument contains a ('U', 'X', 'W', 'Z', '-') in an operand.
ASSERT/WARNING (time 902 NS) from package ieee.STD_LOGIC_ARITH, this
builtin function called from function @ieee.std_logic_signed:"="
Built-in relational argument contains a ('U', 'X', 'W', 'Z', '-') in an operand.

Found digit 1
Found digit 8
Found digit 0
Found digit 0

DTMF TESTING SUCCESSFULLY COMPLETED!

ASSERT/FAILURE (time 12722660 NS) from process :main (architecture
worklib.dtmf_recvr_core_test:behavior)
Assertion violation.
Assertion at 12722660 NS + 5
./testbench.vhd:203 assert FALSE severity FAILURE;
ncsim> exit
Note that the assertion violation is not a logical error. Rather, it is a standard way
in a VHDL model to test for a termination condition to stop the simulation.
Graphical Interface Approach
There is graphical interface approach called nclaunch which integrates the three manual
steps described above.
While in your project directory, run the command
nclaunch -new
which will bring up the window:
Now, set each directory and work library as shown (replacing “hcarter” with your
home directory name). If you have not created a cds.lib or hdl.var file, select “new”
as appropriate. Further, you can create a working library (“worklib” in this example)
by selecting “New” next to the “Select the work library” area.
Select Ok to confirm. The following window appears:
We will now execute the three phases to simulate a VHDL model: Analyze (i.e.,
compile) the VHDL files, elaborate the model, and simulate the model.
1. Analyze the vhdl file.
Select each VHDL file in turn, holding down the ctrl key to multiply select the

three VHDL files. The files must be selected in compilation order (see the
discussion above on the arguments on the command line for ncvhdl). For this
tutorial, select the files in the order: packages.vhd, dtmf_recvr_core.vhd,
and testbench.vhd.
Select “Tool -> Analyzer”, and “Tool -> Enable line debug” . Click OK to begin
compiling.Watch the bottom message window for errors during compilation.
Alternatively, you can click on the first button to the right after “Tools” in the
second menu bar to begin compilation.
2. Elaborate the design
If no compilation errors occur, click on the “+” next to “worklib” in the right sub-
window. You will see the entities names for each design unit. Expand
dtmf_recvr_core_test design unit to reveal the architecture named “behavior”.
Click on “behavior” as the top level design unit to be elaborated. Select
“Tools”- >”elaborator”, or click on the third button to the right of “Tools” (looks
like a paperclip) to begin elaboration.
3. Simulate the Design
Elaboration produces a “Snapshots “ folder. Exand it to reveal the name of the
simulation snapshot: worklib.dtmf_recvr_core_test:behavior. Select the
snapshot, then select “Tools -> Simulator” from the menu (or, alternatively, select
the fourth button to the right of “Tools” on the second menu bar). Observe the
message window to view the results of simulation.
To observer the signal, just choose the signals, right click mouse, choose “wave
trace”. Then click the “play” button, you will get the waveform window.
Note, to simulate the circuit, you need a testbench.