Bài giảng điện tử môn tin học: Field Programmable Gate Arrays doc

ELEC-2005
Electronics in High Energy Physics
Winter Term: Introduction to Electronics in HEP
Field Programmable Gate Arrays
Part 1
Stefan Haas

CERN Technical Training 2005
Stefan Haas, 1 F
eb. 2005
ELEC-2005 2
Part 2
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VHDL
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Introduction
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Examples
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Design Flow
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Entry Methods
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Simulation
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Synthesis
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Place & Route
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IP Cores
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CERN Tools & Support
Part 1
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Programmable Logic
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CPLD
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FPGA
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Architecture
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Examples
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Features
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Vendors and Devices
coffee break
Outline
Programmable Logic
Stefan Haas, 1 F
eb. 2005
ELEC-2005 4
Programmable Logic
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Programmable digital integrated circuit
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Standard off-the-shelf parts
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Desired functionality is implemented by configuring
on-chip logic blocks and interconnections

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Advantages (compared to an ASIC):
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Low development costs
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Short development cycle
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Device can (usually) be reprogrammed
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Types of programmable logic:
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Complex PLDs (CPLD)
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Field programmable Gate Arrays (FPGA)
CPLD
Architecture and Examples
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eb. 2005
ELEC-2005 6
PLD - Sum of Products
A B C
CBACBAf ••+••=
1
CBABAf ••+•=
2
AND plane
Programmable AND array followed by fixed fan-in OR gates
Programmable switch or fuse
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eb. 2005

ELEC-2005 7
PLD - Macrocell
Can implement combinational or sequential
logic
A
B
C
Flip-flop
Select
Enable
D Q
Clock
AND plane
MUX
1
f
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CPLD Structure
Integration of several PLD blocks with a programmable
interconnect on a single chip
PLD
Block
PLD
Block
PLD
Block
PLD
Block

Interconnection Matrix
Interconnection Matrix
I/O Block
I/O Block
I/O Block
I/O Block
PLD
Block
PLD
Block
PLD
Block
PLD
Block
I/O Block
I/O Block
I/O Block
I/O Block
•

•

•

Interconnection Matrix
Interconnection Matrix
•

•

•

•

•

•

•

•

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Stefan Haas, 1 F
eb. 2005
ELEC-2005 9
CPLD Example - Altera MAX7000
EPM7000 Series Block Diagram
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eb. 2005
ELEC-2005 10
CPLD Example - Altera MAX7000
EPM7000 Series Device Macrocell
FPGA Architecture
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eb. 2005
ELEC-2005 12
FPGA - Generic Structure
FPGA building blocks:

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Programmable logic blocks
Implement combinatorial and
sequential logic
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Programmable interconnect
Wires to connect inputs and
outputs to logic blocks
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Programmable I/O blocks
Special logic blocks at the
periphery of device for external
connections
I/O
I/O
Logic block
Interconnection switches
I/O
I/O
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eb. 2005
ELEC-2005 13
Other FPGA Building Blocks
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Clock distribution
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Embedded memory blocks
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Special purpose blocks:
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DSP blocks:
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Hardware multipliers, adders and registers
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Embedded microprocessors/microcontrollers
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High-speed serial transceivers
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eb. 2005
ELEC-2005 14
FPGA – Basic Logic Element
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LUT to implement combinatorial logic
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Register for sequential circuits
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Additional logic (not shown):
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Carry logic for arithmetic functions
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Expansion logic for functions requiring more than 4 inputs
LUT
LUT
Out
Select
D Q
A
B
C
D

Clock
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eb. 2005
ELEC-2005 15
Look-Up Tables (LUT)
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Look-up table with N-inputs can be used to implement any
combinatorial function of N inputs
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LUT is programmed with the truth-table
LUT
LUT
A
B
C
D
Z
A
B
C
D
Z
Truth-table Gate implementation
LUT implementation
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eb. 2005
ELEC-2005 16
LUT Implementation
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Example: 3-input LUT

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Based on multiplexers
(pass transistors)
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LUT entries stored in
configuration memory
cells
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
X1
X2
X3
F
Configuration memory
cells
Stefan Haas, 1 F

eb. 2005
ELEC-2005 17
Programmable Interconnect
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Interconnect hierarchy (not shown)
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Fast local interconnect
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Horizontal and vertical lines of various lengths
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
Switch
Matrix
Switch
Matrix
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ELEC-2005 18
Switch Matrix Operation
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6 pass transistors per switch
matrix interconnect point
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Pass transistors act as
programmable switches
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Pass transistor gates are driven
by configuration memory cells
After Programming
Before Programming
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eb. 2005
ELEC-2005 19
Special Features
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Clock management
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PLL,DLL
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Eliminate clock skew between external clock input
and on-chip clock
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Low-skew global clock distribution network
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Support for various interface standards
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High-speed serial I/Os
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Embedded processor cores
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DSP blocks
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ELEC-2005 20
Configuration Storage Elements
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Static Random Access Memory (SRAM)
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each switch is a pass transistor controlled by the state of an SRAM bit
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FPGA needs to be configured at power-on
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Flash Erasable Programmable ROM (Flash)
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each switch is a floating-gate transistor that can be turned off by
injecting charge onto its gate. FPGA itself holds the program
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reprogrammable, even in-circuit
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Fusible Links (“Antifuse”)
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Forms a forms a low resistance path when electrically programmed
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one-time programmable in special programming machine
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radiation tolerant
Example: Altera Stratix Series
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eb. 2005
ELEC-2005 22

Floorplan
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ELEC-2005 23
Logic Element
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eb. 2005
ELEC-2005 24
Logic Array Block (LAB)
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LAB regroups 10 logic
elements with a fast
local interconnect
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Interconnect structure
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Direct link between LABs
and adjacent blocks
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Row interconnects
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4, 8, and 24 blocks left or
right
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Column interconnects
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4, 8, and 16 blocks up or
down
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ELEC-2005 25
Embedded Memory
Dual-Port RAM
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M512 – 512 x 1
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M4K – 4096 x 1
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M-RAM – 64K x 8