Hướng dẫn sử dụng phần mềm Modelsim

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TRƯỜNG ĐẠI HỌC BÁCH KHOA HÀ NỘI
VIỆN ĐIỆN TỬ VIỄN THÔNG
IC Design Lab
Introduction
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1. Introduction
Contents
2. Design Project
3. Simulation
4. Synthesize the design

1. Introduction
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1. Introduction
Modelsim Quartus
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1. Introduction
1.1 Modelsim
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ModelSim is a verification and simulation tool for
VHDL, Verilog, SystemVerilog, and mixed-language
designs.
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Software : ModelSim-Altera 6.6d Starter Edition
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References :
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Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform
Editor (Altera).
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ModelSim Tutorial (Mentor Graphics).
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1. Introduction
1.2 Quartus
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Quartus .
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Software : Quartus II 11.1 Web Edition
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References :
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Quartus Tutorial .
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1. Introduction
Contents
2. Design Project
3. Simulation

4. Synthesize the design

2. Design Project
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2. Design Project
Simple example : f(x1, x2, x3) = x1x2 + x2x3 + x3x1
Verilog code :
module majority(x1, x2 ,x3 ,f);

input x1, x2, x3;
output f;
assign f = (x1&x2)|(x2&x3)|(x3&x1);
endmodule;
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2. Design Project
Open the ModelSim simulator. In the displayed window
select File > New > Project
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2. Design Project
A Create Project pop-up box will appear…
1.Enter the name of
the project
Choose Project
Location
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2. Design Project

Create new file…
1
2
3
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2. Design Project
Double click
Text Editor
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2. Design Project
Or add existing file…
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2. Design Project
After completed coding, select Compile > Compile all
Compile of majority.v was successfull
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1. Introduction
Contents
2. Design Project
3. Simulation
4. Synthesize the design
3. Simulation
3. Simulation 3. Simulation
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3. Simulation
3.1. Simulate without testbench
3.2. Simulate with testbench
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3. Simulation
3.1. Simulate without testbench
Select Simulate > Start simulation…, Start Simulation
window will appear…
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3. Simulation
Simulation window…
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3. Simulation
Create waveforms for Simulation…
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3. Simulation
Modify waveforms for Simulation…
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3. Simulation
Waveform window…
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3. Simulation
Waveform window…
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3. Simulation
With output signal…
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3. Simulation
Simulate…Select Run all
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3. Simulation
Result…
To stop simulation, slect Simulate -> End simulation
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3. Simulation
3.2. Simulate with testbench
Create testbench file to project